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Add initializetion of NVCTL register with EEPROM stored value.

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This fix hazardous very slow work for one of my cards.

MFC after:	1 week
This commit is contained in:
Semen Ustimenko 2001-06-23 19:30:26 +00:00
parent f1a1584029
commit 1d57ebcdbf
5 changed files with 45 additions and 0 deletions
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3
sys/dev/tx/if_tx.c
View File

@ -781,6 +781,9 @@ epic_common_attach(sc)
for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
/* Set Non-Volatile Control Register from EEPROM */
CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
/* Set defaults */
sc->tx_threshold = TRANSMIT_THRESHOLD;
sc->txcon = TXCON_DEFAULT;

13
sys/dev/tx/if_txreg.h
View File

@ -206,6 +206,19 @@
#define RXCON_DEFAULT (RXCON_EARLY | \
RXCON_RECEIVE_MULTICAST_FRAMES | \
RXCON_RECEIVE_BROADCAST_FRAMES)
/*
* EEPROM structure
* SMC9432* eeprom is organized by words and only first 8 words
* have distinctive meaning (according to datasheet)
*/
#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */
#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */
#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */
#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */
#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */
#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */
#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */
#define EEPROM_SSID 0x0006 /* Subsystem Id */
/*
* Structures definition and Functions prototypes

13
sys/dev/tx/if_txvar.h
View File

@ -206,6 +206,19 @@
#define RXCON_DEFAULT (RXCON_EARLY | \
RXCON_RECEIVE_MULTICAST_FRAMES | \
RXCON_RECEIVE_BROADCAST_FRAMES)
/*
* EEPROM structure
* SMC9432* eeprom is organized by words and only first 8 words
* have distinctive meaning (according to datasheet)
*/
#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */
#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */
#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */
#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */
#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */
#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */
#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */
#define EEPROM_SSID 0x0006 /* Subsystem Id */
/*
* Structures definition and Functions prototypes

3
sys/pci/if_tx.c
View File

@ -781,6 +781,9 @@ epic_common_attach(sc)
for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
/* Set Non-Volatile Control Register from EEPROM */
CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
/* Set defaults */
sc->tx_threshold = TRANSMIT_THRESHOLD;
sc->txcon = TXCON_DEFAULT;

13
sys/pci/if_txvar.h
View File

@ -206,6 +206,19 @@
#define RXCON_DEFAULT (RXCON_EARLY | \
RXCON_RECEIVE_MULTICAST_FRAMES | \
RXCON_RECEIVE_BROADCAST_FRAMES)
/*
* EEPROM structure
* SMC9432* eeprom is organized by words and only first 8 words
* have distinctive meaning (according to datasheet)
*/
#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */
#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */
#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */
#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */
#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */
#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */
#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */
#define EEPROM_SSID 0x0006 /* Subsystem Id */
/*
* Structures definition and Functions prototypes