Create driver file templates, kernel module Makefile and add initial
version of register definitions for ISP1761 and SAF1761 compatible chips. Sponsored by: DARPA, AFRL
This commit is contained in:
Hans Petter Selasky
parent
373ca6f9ff
commit
1d6b6e9d46
33
sys/dev/usb/controller/saf1761_dci.c
Normal file
33
sys/dev/usb/controller/saf1761_dci.c
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <dev/usb/controller/saf1761_dci.h>
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#include <dev/usb/controller/saf1761_dci_reg.h>
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36
sys/dev/usb/controller/saf1761_dci.h
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36
sys/dev/usb/controller/saf1761_dci.h
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@ -0,0 +1,36 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SAF1761_DCI_H_
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#define _SAF1761_DCI_H_
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#endif /* _SAF1761_DCI_H_ */
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34
sys/dev/usb/controller/saf1761_dci_fdt.c
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34
sys/dev/usb/controller/saf1761_dci_fdt.c
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@ -0,0 +1,34 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <dev/usb/controller/saf1761_dci.h>
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#include <dev/usb/controller/saf1761_dci_reg.h>
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156
sys/dev/usb/controller/saf1761_dci_reg.h
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156
sys/dev/usb/controller/saf1761_dci_reg.h
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@ -0,0 +1,156 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2014 Hans Petter Selasky
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SAF1761_DCI_REG_H_
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#define _SAF1761_DCI_REG_H_
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/* Global registers */
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#define SOTG_VEND_ID 0x370
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#define SOTG_PROD_ID 0x372
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#define SOTG_CTRL_SET 0x374
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#define SOTG_CTRL_CLR 0x376
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#define SOTG_CTRL_OTG_DISABLE (1 << 10)
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#define SOTG_CTRL_OTG_SE0_EN (1 << 9)
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#define SOTG_CTRL_BDIS_ACON_EN (1 << 8)
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#define SOTG_CTRL_SW_SEL_HC_DC (1 << 7)
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#define SOTG_CTRL_VBUS_CHRG (1 << 6)
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#define SOTG_CTRL_VBUS_DISCHRG (1 << 5)
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#define SOTG_CTRL_VBUS_DRV (1 << 4)
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#define SOTG_CTRL_SEL_CP_EXT (1 << 3)
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#define SOTG_CTRL_DM_PULL_DOWN (1 << 2)
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#define SOTG_CTRL_DP_PULL_DOWN (1 << 1)
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#define SOTG_CTRL_DP_PULL_UP (1 << 0)
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#define SOTG_STATUS 0x378
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#define SOTG_STATUS_B_SE0_SRP (1 << 8)
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#define SOTG_STATUS_B_SESS_END (1 << 7)
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#define SOTG_STATUS_RMT_CONN (1 << 4)
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#define SOTG_STATUS_ID (1 << 3)
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#define SOTG_STATUS_DP_SRP (1 << 2)
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#define SOTG_STATUS_A_B_SESS_VLD (1 << 1)
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#define SOTG_STATUS_VBUS_VLD (1 << 0)
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#define SOTG_IRQ_LATCH_SET 0x37C
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#define SOTG_IRQ_LATCH_CLR 0x37E
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#define SOTG_IRQ_ENABLE_SET 0x380
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#define SOTG_IRQ_ENABLE_CLR 0x382
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#define SOTG_IRQ_RISE_SET 0x384
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#define SOTG_IRQ_RISE_CLR 0x386
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#define SOTG_IRQ_OTG_TMR_TIMEOUT (1 << 9)
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#define SOTG_IRQ_B_SE0_SRP (1 << 8)
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#define SOTG_IRQ_B_SESS_END (1 << 7)
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#define SOTG_IRQ_BDIS_ACON (1 << 6)
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#define SOTG_IRQ_OTG_RESUME (1 << 5)
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#define SOTG_IRQ_RMT_CONN (1 << 4)
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#define SOTG_IRQ_ID (1 << 3)
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#define SOTG_IRQ_DP_SRP (1 << 2)
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#define SOTG_IRQ_A_B_SESS_VLD (1 << 1)
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#define SOTG_IRQ_VBUS_VLD (1 << 0)
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#define SOTG_TIMER_LOW_SET 0x388
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#define SOTG_TIMER_LOW_CLR 0x38A
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#define SOTG_TIMER_HIGH_SET 0x38C
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#define SOTG_TIMER_HIGH_CLR 0x38E
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#define SOTG_TIMER_START_TMR (1U << 15)
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/* Peripheral controller specific registers */
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#define SOTG_ADDRESS 0x200
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#define SOTG_ADDRESS_ENABLE (1 << 7)
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#define SOTG_MODE 0x20C
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#define SOTG_MODE_DMACLK_ON (1 << 9)
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#define SOTG_MODE_VBUSSTAT (1 << 8)
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#define SOTG_MODE_CLKAON (1 << 7)
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#define SOTG_MODE_SNDRSU (1 << 6)
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#define SOTG_MODE_GOSUSP (1 << 5)
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#define SOTG_MODE_SFRESET (1 << 4)
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#define SOTG_MODE_GLINTENA (1 << 3)
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#define SOTG_MODE_WKUPCS (1 << 2)
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#define SOTG_INTERRUPT_CFG 0x210
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#define SOTG_INTERRUPT_CFG_CDBGMOD (3 << 6)
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#define SOTG_INTERRUPT_CFG_DDBGMODIN (3 << 4)
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#define SOTG_INTERRUPT_CFG_DDBGMODOUT (3 << 2)
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#define SOTG_INTERRUPT_CFG_INTLVL (1 << 1)
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#define SOTG_INTERRUPT_CFG_INTPOL (1 << 0)
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#define SOTG_DEBUG 0x212
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#define SOTG_DEBUG_SET (1 << 0)
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#define SOTG_DCINTERRUPT_EN 0x214
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#define SOTG_HW_MODE_CTRL 0x300
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#define SOTG_OTG_CTRL 0x374
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#define SOTG_EP_INDEX 0x22c
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#define SOTG_EP_INDEX_EP0SETUP (1 << 5)
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#define SOTG_EP_INDEX_ENDP_INDEX (15 << 1)
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#define SOTG_EP_INDEX_DIR_IN (1 << 0)
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#define SOTG_CTRL_FUNC 0x228
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#define SOTG_CTRL_FUNC_CLBUF (1 << 4)
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#define SOTG_CTRL_FUNC_VENDP (1 << 3)
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#define SOTG_CTRL_FUNC_DSEN (1 << 2)
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#define SOTG_CTRL_FUNC_STATUS (1 << 1)
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#define SOTG_CTRL_FUNC_STALL (1 << 0)
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#define SOTG_DATA_PORT 0x220
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#define SOTG_BUF_LENGTH 0x21C
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#define SOTG_DCBUFFERSTATUS 0x21E
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#define SOTG_EP_MAXPACKET 0x204
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#define SOTG_EP_TYPE 0x208
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#define SOTG_EP_TYPE_NOEMPPKT (1 << 4)
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#define SOTG_EP_TYPE_ENABLE (1 << 3)
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#define SOTG_EP_TYPE_DBLBUF (1 << 2)
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#define SOTG_EP_TYPE_EP_TYPE (3 << 0)
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#define SOTG_DMA_CMD 0x230
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#define SOTG_DMA_XFER_COUNT 0x234
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#define SOTG_DCDMA_CFG 0x238
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#define SOTG_DMA_HW 0x23C
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#define SOTG_DMA_IRQ_REASON 0x250
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#define SOTG_DMA_IRQ_ENABLE 0x254
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#define SOTG_DMA_EP 0x258
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#define SOTG_BURST_COUNTER 0x264
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#define SOTG_DCINTERRUPT 0x218
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#define SOTG_DCINTERRUPT_IEPRX(n) (1 << (10 + (2*(n))))
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#define SOTG_DCINTERRUPT_IEPTX(n) (1 << (11 + (2*(n))))
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#define SOTG_DCINTERRUPT_IEP0SETUP (1 << 8)
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#define SOTG_DCINTERRUPT_IEVBUS (1 << 7)
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#define SOTG_DCINTERRUPT_IEDMA (1 << 6)
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#define SOTG_DCINTERRUPT_IEHS_STA (1 << 5)
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#define SOTG_DCINTERRUPT_IERESM (1 << 4)
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#define SOTG_DCINTERRUPT_IESUSP (1 << 3)
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#define SOTG_DCINTERRUPT_IEPSOF (1 << 2)
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#define SOTG_DCINTERRUPT_IESOF (1 << 1)
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#define SOTG_DCINTERRUPT_IEBRST (1 << 0)
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#define SOTG_DCCHIP_ID 0x270
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#define SOTG_FRAME_NUM 0x274
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#define SOTG_FRAME_NUM_MICROSOFR 0x3800
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#define SOTG_FRAME_NUM_MICROSOFR_SHIFT 11
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#define SOTG_FRAME_NUM_SOFR 0x7FF
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#define SOTG_DCSCRATCH 0x278
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#define SOTG_UNLOCK_DEVICE 0x27C
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#define SOTG_UNLOCK_DEVICE_CODE 0xAA37
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#define SOTG_IRQ_PULSE_WIDTH 0x280
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#define SOTG_TEST_MODE 0x284
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#endif /* _SAF1761_DCI_REG_H_ */
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42
sys/modules/usb/saf1761/Makefile
Normal file
42
sys/modules/usb/saf1761/Makefile
Normal file
@ -0,0 +1,42 @@
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#
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# $FreeBSD$
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#
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# Copyright (c) 2014 Hans Petter Selasky. All rights reserved.
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#
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# This software was developed by SRI International and the University of
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# Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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# ("CTSRD"), as part of the DARPA CRASH research programme.
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#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
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# are met:
|
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# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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S= ${.CURDIR}/../../..
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.PATH: $S/dev/usb/controller
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KMOD= saf1761
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SRCS= bus_if.h device_if.h usb_if.h \
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opt_bus.h opt_usb.h ofw_bus_if.h \
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saf1761_dci.c saf1761_dci_fdt.c \
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pci_if.h
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.include <bsd.kmod.mk>
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