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Disable C1 Enhanced mode on AMD K8 Family Revision F and above to keep

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local APIC timer alive.

Reviewed by:	jhb
PR:		i386/104678
MFC after:	3 days
This commit is contained in:
Ariff Abdullah 2007-04-25 19:58:42 +00:00
parent bca541bab1
commit 1d80d190af
2 changed files with 46 additions and 0 deletions
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23
sys/amd64/amd64/local_apic.c
View File

@ -326,6 +326,29 @@ lapic_setup(int boot)
/* XXX: Error and thermal LVTs */
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family. This feature renders
* the local APIC timer dead, so we disable it by reading
* the Interrupt Pending Message register and clearing both
* C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
*
* Reference:
* "BIOS and Kernel Developer's Guide for AMD NPT
* Family 0Fh Processors"
* #32559 revision 3.00
*/
if ((cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
uint64_t msr;
msr = rdmsr(0xc0010055);
if (msr & 0x18000000)
wrmsr(0xc0010055, msr & ~0x18000000ULL);
}
}
intr_restore(eflags);
}

23
sys/i386/i386/local_apic.c
View File

@ -328,6 +328,29 @@ lapic_setup(int boot)
/* XXX: Error and thermal LVTs */
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family. This feature renders
* the local APIC timer dead, so we disable it by reading
* the Interrupt Pending Message register and clearing both
* C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
*
* Reference:
* "BIOS and Kernel Developer's Guide for AMD NPT
* Family 0Fh Processors"
* #32559 revision 3.00
*/
if ((cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
uint64_t msr;
msr = rdmsr(0xc0010055);
if (msr & 0x18000000)
wrmsr(0xc0010055, msr & ~0x18000000ULL);
}
}
intr_restore(eflags);
}