Only build the cache handling code we need when building the arm ELF
trampoline.
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c935c49309
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@ -39,6 +39,7 @@
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#ifndef ELF_TRAMPOLINE
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/*
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* Functions to set the MMU Translation Table Base register
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*
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@ -192,6 +193,7 @@ ENTRY(armv5_ec_idcache_wbinv_range)
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_idcache_wbinv_range)
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#endif /* !ELF_TRAMPOLINE */
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ENTRY_NP(armv5_ec_idcache_wbinv_all)
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.Larmv5_ec_idcache_wbinv_all:
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@ -204,6 +206,7 @@ ENTRY_NP(armv5_ec_idcache_wbinv_all)
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/* Fall through to purge Dcache. */
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END(armv5_ec_idcache_wbinv_all)
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#ifndef ELF_TRAMPOLINE
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ENTRY(armv5_ec_dcache_wbinv_all)
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.Larmv5_ec_dcache_wbinv_all:
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1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
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@ -211,4 +214,4 @@ ENTRY(armv5_ec_dcache_wbinv_all)
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mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
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RET
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END(armv5_ec_dcache_wbinv_all)
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#endif
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@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/armreg.h>
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#include <machine/param.h>
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#ifndef ELF_TRAMPOLINE
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.Lsheeva_cache_line_size:
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.word _C_LABEL(arm_pdcache_line_size)
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.Lsheeva_asm_page_mask:
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@ -376,6 +377,7 @@ ENTRY(sheeva_l2cache_wb_range)
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ldr lr, [sp], #4
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RET
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END(sheeva_l2cache_wb_range)
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#endif /* !ELF_TRAMPOLINE */
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ENTRY(sheeva_l2cache_wbinv_all)
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/* Disable irqs */
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@ -393,6 +395,7 @@ ENTRY(sheeva_l2cache_wbinv_all)
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RET
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END(sheeva_l2cache_wbinv_all)
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#ifndef ELF_TRAMPOLINE
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/* This function modifies register value as follows:
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*
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* arg1 arg EFFECT (bit value saved into register)
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@ -418,4 +421,4 @@ ENTRY(sheeva_cpu_sleep)
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mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */
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mov pc, lr
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END(sheeva_cpu_sleep)
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#endif /* !ELF_TRAMPOLINE */
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@ -73,8 +73,6 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\
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rm ${FULLKERNEL}.noheader
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FILES_CPU_FUNC = \
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$S/$M/$M/cpufunc_asm_arm9.S \
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$S/$M/$M/cpufunc_asm.S \
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$S/$M/$M/cpufunc_asm_armv5_ec.S \
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$S/$M/$M/cpufunc_asm_sheeva.S
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