sys/dev/e1000: fix uses of 1 << 31
Reviewed by: erj (D13858)
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7ec20ea487
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@ -385,7 +385,7 @@ struct e1000_adv_tx_context_desc {
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#define E1000_ETQF_FILTER_ENABLE (1 << 26)
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#define E1000_ETQF_IMM_INT (1 << 29)
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#define E1000_ETQF_1588 (1 << 30)
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#define E1000_ETQF_QUEUE_ENABLE (1 << 31)
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#define E1000_ETQF_QUEUE_ENABLE (1U << 31)
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/*
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* ETQF filter list: one static filter per filter consumer. This is
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* to avoid filter collisions later. Add new filters
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@ -412,7 +412,7 @@ struct e1000_adv_tx_context_desc {
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#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
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#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
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#define E1000_DTXSWC_LLE_SHIFT 16
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#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
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#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1U << 31) /* global VF LB enable */
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/* Easy defines for setting default pool, would normally be left a zero */
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#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
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@ -5202,7 +5202,7 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
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/* Device Status */
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if (hw->mac.type == e1000_ich8lan) {
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reg = E1000_READ_REG(hw, E1000_STATUS);
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reg &= ~(1 << 31);
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reg &= ~(1U << 31);
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E1000_WRITE_REG(hw, E1000_STATUS, reg);
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}
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@ -215,7 +215,7 @@
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/* QAV Tx mode control register bitfields masks */
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#define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */
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#define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */
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#define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */
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#define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */
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/* Good transmitted packets counter registers */
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#define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n)))
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