Rework link state tracking and TX/RX MAC configuration.
o Do not report link status if driver is not running. o TX/RX MAC configuration should be done with resolved speed, duplex and flow control after establishing a link so it can't be done in driver initialization routine. Move the configuration to miibus_statchg callback which will be called whenever any link state change is detected. At this moment, flow-control is not enabled yet mainly because I was not able to set correct flow control parameters to generate TX pause frames. o Now TX/RX MAC is enabled only when a valid link is detected. Rearragnge hardware initialization routine a bit to leave enabling MAC to miibus_statchg callback. In order to that, TX/RX DMA engine is enabled in et_init_locked(). o Introduce ET_FLAG_LINK flag to track current link state. o Introduce ET_FLAG_FASTETHER flag to mark whether controller is fast ethernet. This flag is checked in miibus_statchg callback to know whether PHY established a valid link. o In et_stop(), TX/RX MAC is explicitly disabled instead of relying on et_reset(). And move et_reset() from et_stop() to controller initialization. Controler reset is not required here and it would also clear critial registers(i.e station address, RX filter configuration, WOL etc) that are required to make WOL work. o Switching to current media is done in et_init_locked() after setting IFF_DRV_RUNNING flag. This should ensure reliable auto-negotiation/manual link establishment. o In et_start_locked(), check whether driver got a valid link before trying to send frames. o Remove checking a link in et_tick() as this is done by miibus_statchg callback.
This commit is contained in:
Pyun YongHyeon
parent
57979d1bd8
commit
1f009e2f39
@ -141,13 +141,11 @@ static int et_start_rxdma(struct et_softc *);
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static int et_start_txdma(struct et_softc *);
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static int et_stop_rxdma(struct et_softc *);
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static int et_stop_txdma(struct et_softc *);
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static int et_enable_txrx(struct et_softc *, int);
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static void et_reset(struct et_softc *);
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static int et_bus_config(struct et_softc *);
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static void et_get_eaddr(device_t, uint8_t[]);
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static void et_setmulti(struct et_softc *);
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static void et_tick(void *);
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static void et_setmedia(struct et_softc *);
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static const struct et_dev {
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uint16_t vid;
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@ -296,6 +294,9 @@ et_attach(device_t dev)
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goto fail;
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}
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if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST)
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sc->sc_flags |= ET_FLAG_FASTETHER;
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error = et_bus_config(sc);
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if (error)
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goto fail;
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@ -487,7 +488,89 @@ et_miibus_writereg(device_t dev, int phy, int reg, int val0)
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static void
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et_miibus_statchg(device_t dev)
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{
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et_setmedia(device_get_softc(dev));
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struct et_softc *sc;
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struct mii_data *mii;
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struct ifnet *ifp;
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uint32_t cfg1, cfg2, ctrl;
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int i;
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sc = device_get_softc(dev);
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mii = device_get_softc(sc->sc_miibus);
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ifp = sc->ifp;
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if (mii == NULL || ifp == NULL ||
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(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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sc->sc_flags &= ~ET_FLAG_LINK;
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if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
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(IFM_ACTIVE | IFM_AVALID)) {
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switch (IFM_SUBTYPE(mii->mii_media_active)) {
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case IFM_10_T:
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case IFM_100_TX:
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sc->sc_flags |= ET_FLAG_LINK;
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break;
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case IFM_1000_T:
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if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0)
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sc->sc_flags |= ET_FLAG_LINK;
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break;
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}
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}
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/* XXX Stop TX/RX MAC? */
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if ((sc->sc_flags & ET_FLAG_LINK) == 0)
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return;
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/* Program MACs with resolved speed/duplex/flow-control. */
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ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
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ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
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cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
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cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
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ET_MAC_CFG1_LOOPBACK);
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cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
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cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
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ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
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cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
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((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
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ET_MAC_CFG2_PREAMBLE_LEN_MASK);
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
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cfg2 |= ET_MAC_CFG2_MODE_GMII;
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else {
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cfg2 |= ET_MAC_CFG2_MODE_MII;
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ctrl |= ET_MAC_CTRL_MODE_MII;
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}
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if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
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cfg2 |= ET_MAC_CFG2_FDX;
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#ifdef notyet
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if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE)
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cfg1 |= ET_MAC_CFG1_TXFLOW;
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if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE)
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cfg1 |= ET_MAC_CFG1_RXFLOW;
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#endif
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} else
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ctrl |= ET_MAC_CTRL_GHDX;
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CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
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CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
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cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
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CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1);
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#define NRETRY 50
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for (i = 0; i < NRETRY; ++i) {
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cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
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if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
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(ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
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break;
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DELAY(100);
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}
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if (i == NRETRY)
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if_printf(ifp, "can't enable RX/TX\n");
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sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
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#undef NRETRY
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}
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static int
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@ -518,10 +601,17 @@ et_ifmedia_upd(struct ifnet *ifp)
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static void
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et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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{
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struct et_softc *sc = ifp->if_softc;
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struct mii_data *mii = device_get_softc(sc->sc_miibus);
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struct et_softc *sc;
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struct mii_data *mii;
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sc = ifp->if_softc;
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ET_LOCK(sc);
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if ((ifp->if_flags & IFF_UP) == 0) {
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ET_UNLOCK(sc);
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return;
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}
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mii = device_get_softc(sc->sc_miibus);
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mii_pollstat(mii);
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ifmr->ifm_active = mii->mii_media_active;
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ifmr->ifm_status = mii->mii_media_status;
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@ -539,14 +629,16 @@ et_stop(struct et_softc *sc)
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/* Disable interrupts. */
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CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
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CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~(
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ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN));
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DELAY(100);
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et_stop_rxdma(sc);
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et_stop_txdma(sc);
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et_free_tx_ring(sc);
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et_free_rx_ring(sc);
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et_reset(sc);
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sc->sc_tx = 0;
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sc->sc_tx_intr = 0;
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sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
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@ -1104,6 +1196,7 @@ et_init_locked(struct et_softc *sc)
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return;
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et_stop(sc);
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et_reset(sc);
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et_init_tx_ring(sc);
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error = et_init_rx_ring(sc);
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@ -1112,22 +1205,33 @@ et_init_locked(struct et_softc *sc)
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error = et_chip_init(sc);
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if (error)
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goto back;
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goto fail;
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error = et_enable_txrx(sc, 1);
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/*
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* Start TX/RX DMA engine
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*/
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error = et_start_rxdma(sc);
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if (error)
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goto back;
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return;
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error = et_start_txdma(sc);
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if (error)
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return;
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/* Enable interrupts. */
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CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS);
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callout_reset(&sc->sc_tick, hz, et_tick, sc);
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CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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back:
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sc->sc_flags &= ~ET_FLAG_LINK;
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et_ifmedia_upd_locked(ifp);
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callout_reset(&sc->sc_tick, hz, et_tick, sc);
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fail:
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if (error)
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et_stop(sc);
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}
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@ -1239,10 +1343,10 @@ et_start_locked(struct ifnet *ifp)
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sc = ifp->if_softc;
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ET_LOCK_ASSERT(sc);
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if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
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return;
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if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
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if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
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IFF_DRV_RUNNING ||
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(sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) !=
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(ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED))
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return;
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/*
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@ -1870,56 +1974,6 @@ et_start_txdma(struct et_softc *sc)
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return (0);
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}
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static int
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et_enable_txrx(struct et_softc *sc, int media_upd)
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{
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struct ifnet *ifp = sc->ifp;
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uint32_t val;
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int i, error;
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val = CSR_READ_4(sc, ET_MAC_CFG1);
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val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
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val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
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ET_MAC_CFG1_LOOPBACK);
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CSR_WRITE_4(sc, ET_MAC_CFG1, val);
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if (media_upd)
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et_ifmedia_upd_locked(ifp);
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else
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et_setmedia(sc);
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#define NRETRY 50
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for (i = 0; i < NRETRY; ++i) {
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val = CSR_READ_4(sc, ET_MAC_CFG1);
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if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
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(ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
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break;
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DELAY(100);
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}
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if (i == NRETRY) {
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if_printf(ifp, "can't enable RX/TX\n");
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return (0);
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}
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sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
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#undef NRETRY
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/*
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* Start TX/RX DMA engine
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*/
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error = et_start_rxdma(sc);
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if (error)
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return (error);
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error = et_start_txdma(sc);
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if (error)
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return (error);
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return (0);
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}
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static void
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et_rxeof(struct et_softc *sc)
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{
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@ -2192,6 +2246,7 @@ et_txeof(struct et_softc *sc)
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if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC)
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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}
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static void
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et_tick(void *xsc)
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{
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@ -2204,13 +2259,6 @@ et_tick(void *xsc)
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mii = device_get_softc(sc->sc_miibus);
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mii_tick(mii);
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if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
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(mii->mii_media_status & IFM_ACTIVE) &&
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IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
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if_printf(ifp, "Link up, enable TX/RX\n");
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if (et_enable_txrx(sc, 0) == 0)
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et_start_locked(ifp);
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}
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if (et_watchdog(sc) == EJUSTRETURN)
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return;
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callout_reset(&sc->sc_tick, hz, et_tick, sc);
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@ -2398,38 +2446,6 @@ et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
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return (error);
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}
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static void
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et_setmedia(struct et_softc *sc)
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{
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struct mii_data *mii = device_get_softc(sc->sc_miibus);
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uint32_t cfg2, ctrl;
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cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
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cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
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ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
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cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
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((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) &
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ET_MAC_CFG2_PREAMBLE_LEN_MASK);
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ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
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ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
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cfg2 |= ET_MAC_CFG2_MODE_GMII;
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} else {
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cfg2 |= ET_MAC_CFG2_MODE_MII;
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ctrl |= ET_MAC_CTRL_MODE_MII;
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}
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
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cfg2 |= ET_MAC_CFG2_FDX;
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else
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ctrl |= ET_MAC_CTRL_GHDX;
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CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
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CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
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}
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static int
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et_suspend(device_t dev)
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{
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@ -289,7 +289,9 @@ struct et_softc {
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#define ET_FLAG_PCIE 0x0001
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#define ET_FLAG_MSI 0x0002
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#define ET_FLAG_FASTETHER 0x0004
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#define ET_FLAG_TXRX_ENABLED 0x0100
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#define ET_FLAG_JUMBO 0x0200
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#define ET_FLAG_LINK 0x8000
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#endif /* !_IF_ETVAR_H */
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Block a user