Add support for Intel High Definition Audio Controller.
This driver make a special guarantee that "playback" works
on majority hardwares with minimal or without specific vendor
quirk.
This driver is a product of collaborative effort made by:
Stephane E. Potvin <sepotvin@videotron.ca>
Andrea Bittau <a.bittau@cs.ucl.ac.uk>
Wesley Morgan <morganw@chemikals.org>
Daniel Eischen <deischen@FreeBSD.org>
Maxime Guillaud <bsd-ports@mguillaud.net>
Ariff Abdullah <ariff@FreeBSD.org>
....and various people from freebsd-multimedia@FreeBSD.org
Refer to snd_hda(4) for features and issues.
Welcome To HDA.
Sponsored by: Defenxis Sdn. Bhd.
This commit is contained in:
Ariff Abdullah
parent
e7e3ba9bbc
commit
1f0387f732
1226
sys/dev/sound/pci/hda/hda_reg.h
Normal file
1226
sys/dev/sound/pci/hda/hda_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
4584
sys/dev/sound/pci/hda/hdac.c
Normal file
4584
sys/dev/sound/pci/hda/hdac.c
Normal file
File diff suppressed because it is too large
Load Diff
69
sys/dev/sound/pci/hda/hdac.h
Normal file
69
sys/dev/sound/pci/hda/hdac.h
Normal file
@ -0,0 +1,69 @@
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/*-
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDAC_H_
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#define _HDAC_H_
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#if 0
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/****************************************************************************
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* Miscellanious defines
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****************************************************************************/
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/****************************************************************************
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* Helper Macros
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****************************************************************************/
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/****************************************************************************
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* Simplified Accessors for HDA devices
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****************************************************************************/
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enum hdac_device_ivars {
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HDAC_IVAR_CODEC_ID,
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HDAC_IVAR_NODE_ID,
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HDAC_IVAR_VENDOR_ID,
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HDAC_IVAR_DEVICE_ID,
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HDAC_IVAR_REVISION_ID,
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HDAC_IVAR_STEPPING_ID,
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HDAC_IVAR_NODE_TYPE,
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};
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#define HDAC_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(hdac, var, HDAC, ivar, type)
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HDAC_ACCESSOR(codec_id, CODEC_ID, uint8_t);
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HDAC_ACCESSOR(node_id, NODE_ID, uint8_t);
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HDAC_ACCESSOR(vendor_id, VENDOR_ID, uint16_t);
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HDAC_ACCESSOR(device_id, DEVICE_ID, uint16_t);
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HDAC_ACCESSOR(revision_id, REVISION_ID, uint8_t);
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HDAC_ACCESSOR(stepping_id, STEPPING_ID, uint8_t);
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HDAC_ACCESSOR(node_type, NODE_TYPE, uint8_t);
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#endif
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#define PCIS_MULTIMEDIA_HDA 0x03
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#endif
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335
sys/dev/sound/pci/hda/hdac_private.h
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335
sys/dev/sound/pci/hda/hdac_private.h
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@ -0,0 +1,335 @@
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/*-
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDAC_PRIVATE_H_
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#define _HDAC_PRIVATE_H_
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/****************************************************************************
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* Miscellanious defines
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****************************************************************************/
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#define HDAC_DMA_ALIGNMENT 128
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#define HDAC_CODEC_MAX 16
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#define HDAC_MTX_NAME "hdac driver mutex"
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/****************************************************************************
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* Helper Macros
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****************************************************************************/
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#define HDAC_READ_1(mem, offset) \
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bus_space_read_1((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_2(mem, offset) \
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bus_space_read_2((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_READ_4(mem, offset) \
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bus_space_read_4((mem)->mem_tag, (mem)->mem_handle, (offset))
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#define HDAC_WRITE_1(mem, offset, value) \
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bus_space_write_1((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_2(mem, offset, value) \
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bus_space_write_2((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_WRITE_4(mem, offset, value) \
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bus_space_write_4((mem)->mem_tag, (mem)->mem_handle, (offset), (value))
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#define HDAC_ISDCTL(sc, n) (_HDAC_ISDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDSTS(sc, n) (_HDAC_ISDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDPICB(sc, n) (_HDAC_ISDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDCBL(sc, n) (_HDAC_ISDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDLVI(sc, n) (_HDAC_ISDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFIFOD(sc, n) (_HDAC_ISDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDFMT(sc, n) (_HDAC_ISDFMT((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPL(sc, n) (_HDAC_ISDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_ISDBDPU(sc, n) (_HDAC_ISDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCTL(sc, n) (_HDAC_OSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDSTS(sc, n) (_HDAC_OSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDPICB(sc, n) (_HDAC_OSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDCBL(sc, n) (_HDAC_OSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDLVI(sc, n) (_HDAC_OSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDFIFOD(sc, n) (_HDAC_OSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPL(sc, n) (_HDAC_OSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_OSDBDPU(sc, n) (_HDAC_OSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCTL(sc, n) (_HDAC_BSDCTL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDSTS(sc, n) (_HDAC_BSDSTS((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDPICB(sc, n) (_HDAC_BSDPICB((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDCBL(sc, n) (_HDAC_BSDCBL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDLVI(sc, n) (_HDAC_BSDLVI((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDFIFOD(sc, n) (_HDAC_BSDFIFOD((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPL(sc, n) (_HDAC_BSDBDPL((n), (sc)->num_iss, (sc)->num_oss))
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#define HDAC_BSDBDPU(sc, n) (_HDAC_BSDBDPU((n), (sc)->num_iss, (sc)->num_oss))
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/****************************************************************************
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* Custom hdac malloc type
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****************************************************************************/
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MALLOC_DECLARE(M_HDAC);
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/****************************************************************************
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* struct hdac_mem
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*
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* Holds the resources necessary to describe the physical memory associated
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* with the device.
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****************************************************************************/
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struct hdac_mem {
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struct resource *mem_res;
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int mem_rid;
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bus_space_tag_t mem_tag;
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bus_space_handle_t mem_handle;
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};
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/****************************************************************************
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* struct hdac_irq
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*
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* Holds the resources necessary to describe the irq associated with the
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* device.
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****************************************************************************/
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struct hdac_irq {
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struct resource *irq_res;
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int irq_rid;
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void *irq_handle;
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};
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/****************************************************************************
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* struct hdac_dma
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*
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* This structure is used to hold all the information to manage the dma
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* states.
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****************************************************************************/
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struct hdac_dma {
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bus_dma_tag_t dma_tag;
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bus_dmamap_t dma_map;
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bus_addr_t dma_paddr;
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caddr_t dma_vaddr;
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};
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/****************************************************************************
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* struct hdac_rirb
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*
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* Hold a response from a verb sent to a codec received via the rirb.
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****************************************************************************/
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struct hdac_rirb {
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uint32_t response;
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uint32_t response_ex;
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};
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK 0x0000000f
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET 0
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#define HDAC_RIRB_RESPONSE_EX_UNSOLICITED 0x00000010
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#define HDAC_RIRB_RESPONSE_EX_SDATA_IN(response_ex) \
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(((response_ex) & HDAC_RIRB_RESPONSE_EX_SDATA_IN_MASK) >> \
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HDAC_RIRB_RESPONSE_EX_SDATA_IN_OFFSET)
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/****************************************************************************
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* struct hdac_command_list
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*
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* This structure holds the list of verbs that are to be sent to the codec
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* via the corb and the responses received via the rirb. It's allocated by
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* the codec driver and is owned by it.
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****************************************************************************/
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struct hdac_command_list {
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int num_commands;
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uint32_t *verbs;
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uint32_t *responses;
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};
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typedef int nid_t;
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struct hdac_softc;
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/****************************************************************************
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* struct hdac_codec
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*
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****************************************************************************/
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struct hdac_codec {
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int verbs_sent;
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int responses_received;
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nid_t cad;
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struct hdac_command_list *commands;
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struct hdac_softc *sc;
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SLIST_ENTRY(hdac_codec) next_codec;
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};
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struct hdac_bdle {
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volatile uint32_t addrl;
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volatile uint32_t addrh;
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volatile uint32_t len;
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volatile uint32_t ioc;
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} __packed;
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#define HDA_MAX_CONNS 32
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#define HDA_MAX_NAMELEN 32
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struct hdac_devinfo;
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struct hdac_widget {
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nid_t nid;
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int type;
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int enable;
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int nconns, selconn;
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uint32_t pflags, ctlflags;
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nid_t conns[HDA_MAX_CONNS];
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char name[HDA_MAX_NAMELEN];
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struct hdac_devinfo *devinfo;
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struct {
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uint32_t widget_cap;
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uint32_t outamp_cap;
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uint32_t inamp_cap;
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uint32_t supp_stream_formats;
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uint32_t supp_pcm_size_rate;
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uint32_t eapdbtl;
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int outpath;
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} param;
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union {
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struct {
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uint32_t config;
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uint32_t cap;
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uint32_t ctrl;
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} pin;
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} wclass;
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};
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struct hdac_audio_ctl {
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struct hdac_widget *widget, *childwidget;
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int enable;
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int index;
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int mute, step, size, offset;
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int left, right;
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uint32_t muted;
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int ossdev;
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uint32_t dir, ossmask, ossval;
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};
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/****************************************************************************
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* struct hdac_devinfo
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*
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* Holds all the parameters of a given codec function group. This is stored
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* in the ivar of each child of the hdac bus
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****************************************************************************/
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struct hdac_devinfo {
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device_t dev;
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uint16_t vendor_id;
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uint16_t device_id;
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uint8_t revision_id;
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uint8_t stepping_id;
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uint8_t node_type;
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nid_t nid;
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nid_t startnode, endnode;
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int nodecnt;
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struct hdac_codec *codec;
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struct hdac_widget *widget;
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union {
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struct {
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uint32_t outamp_cap;
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uint32_t inamp_cap;
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uint32_t supp_stream_formats;
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uint32_t supp_pcm_size_rate;
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int ctlcnt, pcnt, rcnt;
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struct hdac_audio_ctl *ctl;
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uint32_t mvol;
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uint32_t quirks;
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int ossidx;
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int playcnt, reccnt;
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int parsing_strategy;
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} audio;
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/* XXX undefined: modem, hdmi. */
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} function;
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};
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struct hdac_chan {
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struct snd_dbuf *b;
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struct pcm_channel *c;
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struct pcmchan_caps caps;
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struct hdac_devinfo *devinfo;
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struct hdac_dma bdl_dma;
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uint32_t spd, fmt, fmtlist[8], pcmrates[16];
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uint32_t supp_stream_formats, supp_pcm_size_rate;
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int ptr, prevptr, blkcnt, blksz;
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int dir;
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int off;
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int sid;
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int bit16, bit32;
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nid_t io[16];
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};
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/****************************************************************************
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* struct hdac_softc
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*
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* This structure holds the current state of the hdac driver.
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****************************************************************************/
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struct hdac_softc {
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device_t dev;
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device_t hdabus;
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struct mtx *lock;
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struct intr_config_hook intrhook;
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struct hdac_mem mem;
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struct hdac_irq irq;
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uint32_t pci_subvendor;
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int num_iss;
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int num_oss;
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int num_bss;
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int support_64bit;
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int streamcnt;
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int corb_size;
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struct hdac_dma corb_dma;
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int corb_wp;
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int rirb_size;
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struct hdac_dma rirb_dma;
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int rirb_rp;
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struct hdac_chan play, rec;
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bus_dma_tag_t chan_dmat;
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int chan_size;
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int chan_blkcnt;
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#define HDAC_UNSOLQ_MAX 64
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#define HDAC_UNSOLQ_READY 0
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#define HDAC_UNSOLQ_BUSY 1
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int unsolq_rp;
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int unsolq_wp;
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int unsolq_st;
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uint32_t unsolq[HDAC_UNSOLQ_MAX];
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struct hdac_codec *codecs[HDAC_CODEC_MAX];
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SLIST_HEAD(hdac_codec_list_head, hdac_codec) codec_list;
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int registered;
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};
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/****************************************************************************
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* struct hdac_command flags
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****************************************************************************/
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#define HDAC_COMMAND_FLAG_WAITOK 0x0000
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#define HDAC_COMMAND_FLAG_NOWAIT 0x0001
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#endif
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266
sys/dev/sound/pci/hda/hdac_reg.h
Normal file
266
sys/dev/sound/pci/hda/hdac_reg.h
Normal file
@ -0,0 +1,266 @@
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/*-
|
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _HDAC_REG_H_
|
||||
#define _HDAC_REG_H_
|
||||
|
||||
/****************************************************************************
|
||||
* HDA Controller Register Set
|
||||
****************************************************************************/
|
||||
#define HDAC_GCAP 0x00 /* 2 - Global Capabilities*/
|
||||
#define HDAC_VMIN 0x02 /* 1 - Minor Version */
|
||||
#define HDAC_VMAJ 0x03 /* 1 - Major Version */
|
||||
#define HDAC_OUTPAY 0x04 /* 2 - Output Payload Capability */
|
||||
#define HDAC_INPAY 0x06 /* 2 - Input Payload Capability */
|
||||
#define HDAC_GCTL 0x08 /* 4 - Global Control */
|
||||
#define HDAC_WAKEEN 0x0c /* 2 - Wake Enable */
|
||||
#define HDAC_STATESTS 0x0e /* 2 - State Change Status */
|
||||
#define HDAC_GSTS 0x10 /* 2 - Global Status */
|
||||
#define HDAC_OUTSTRMPAY 0x18 /* 2 - Output Stream Payload Capability */
|
||||
#define HDAC_INSTRMPAY 0x1a /* 2 - Input Stream Payload Capability */
|
||||
#define HDAC_INTCTL 0x20 /* 4 - Interrupt Control */
|
||||
#define HDAC_INTSTS 0x24 /* 4 - Interrupt Status */
|
||||
#define HDAC_WALCLK 0x30 /* 4 - Wall Clock Counter */
|
||||
#define HDAC_SSYNC 0x38 /* 4 - Stream Synchronization */
|
||||
#define HDAC_CORBLBASE 0x40 /* 4 - CORB Lower Base Address */
|
||||
#define HDAC_CORBUBASE 0x44 /* 4 - CORB Upper Base Address */
|
||||
#define HDAC_CORBWP 0x48 /* 2 - CORB Write Pointer */
|
||||
#define HDAC_CORBRP 0x4a /* 2 - CORB Read Pointer */
|
||||
#define HDAC_CORBCTL 0x4c /* 1 - CORB Control */
|
||||
#define HDAC_CORBSTS 0x4d /* 1 - CORB Status */
|
||||
#define HDAC_CORBSIZE 0x4e /* 1 - CORB Size */
|
||||
#define HDAC_RIRBLBASE 0x50 /* 4 - RIRB Lower Base Address */
|
||||
#define HDAC_RIRBUBASE 0x54 /* 4 - RIRB Upper Base Address */
|
||||
#define HDAC_RIRBWP 0x58 /* 2 - RIRB Write Pointer */
|
||||
#define HDAC_RINTCNT 0x5a /* 2 - Response Interrupt Count */
|
||||
#define HDAC_RIRBCTL 0x5c /* 1 - RIRB Control */
|
||||
#define HDAC_RIRBSTS 0x5d /* 1 - RIRB Status */
|
||||
#define HDAC_RIRBSIZE 0x5e /* 1 - RIRB Size */
|
||||
#define HDAC_ICOI 0x60 /* 4 - Immediate Command Output Interface */
|
||||
#define HDAC_ICII 0x64 /* 4 - Immediate Command Input Interface */
|
||||
#define HDAC_ICIS 0x68 /* 2 - Immediate Command Status */
|
||||
#define HDAC_DPIBLBASE 0x70 /* 4 - DMA Position Buffer Lower Base */
|
||||
#define HDAC_DPIBUBASE 0x74 /* 4 - DMA Position Buffer Upper Base */
|
||||
#define HDAC_SDCTL0 0x80 /* 3 - Stream Descriptor Control */
|
||||
#define HDAC_SDCTL1 0x81 /* 3 - Stream Descriptor Control */
|
||||
#define HDAC_SDCTL2 0x82 /* 3 - Stream Descriptor Control */
|
||||
#define HDAC_SDSTS 0x83 /* 1 - Stream Descriptor Status */
|
||||
#define HDAC_SDLPIB 0x84 /* 4 - Link Position in Buffer */
|
||||
#define HDAC_SDCBL 0x88 /* 4 - Cyclic Buffer Length */
|
||||
#define HDAC_SDLVI 0x8C /* 2 - Last Valid Index */
|
||||
#define HDAC_SDFIFOS 0x90 /* 2 - FIFOS */
|
||||
#define HDAC_SDFMT 0x92 /* 2 - fmt */
|
||||
#define HDAC_SDBDPL 0x98 /* 4 - Buffer Descriptor Pointer Lower Base */
|
||||
#define HDAC_SDBDPU 0x9C /* 4 - Buffer Descriptor Pointer Upper Base */
|
||||
|
||||
#define _HDAC_ISDOFFSET(n, iss, oss) (0x80 + ((n) * 0x20))
|
||||
#define _HDAC_ISDCTL(n, iss, oss) (0x00 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDSTS(n, iss, oss) (0x03 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDPICB(n, iss, oss) (0x04 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDCBL(n, iss, oss) (0x08 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDLVI(n, iss, oss) (0x0c + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDFIFOD(n, iss, oss) (0x10 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDFMT(n, iss, oss) (0x12 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDBDPL(n, iss, oss) (0x18 + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
#define _HDAC_ISDBDPU(n, iss, oss) (0x1c + _HDAC_ISDOFFSET(n, iss, oss))
|
||||
|
||||
#define _HDAC_OSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((n) * 0x20))
|
||||
#define _HDAC_OSDCTL(n, iss, oss) (0x00 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDSTS(n, iss, oss) (0x03 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDPICB(n, iss, oss) (0x04 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDCBL(n, iss, oss) (0x08 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDLVI(n, iss, oss) (0x0c + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDFIFOD(n, iss, oss) (0x10 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDFMT(n, iss, oss) (0x12 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDBDPL(n, iss, oss) (0x18 + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_OSDBDPU(n, iss, oss) (0x1c + _HDAC_OSDOFFSET(n, iss, oss))
|
||||
|
||||
#define _HDAC_BSDOFFSET(n, iss, oss) (0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))
|
||||
#define _HDAC_BSDCTL(n, iss, oss) (0x00 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDSTS(n, iss, oss) (0x03 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDPICB(n, iss, oss) (0x04 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDCBL(n, iss, oss) (0x08 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDLVI(n, iss, oss) (0x0c + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDFIFOD(n, iss, oss) (0x10 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDFMT(n, iss, oss) (0x12 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDBDPL(n, iss, oss) (0x18 + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
#define _HDAC_BSDBDBU(n, iss, oss) (0x1c + _HDAC_BSDOFFSET(n, iss, oss))
|
||||
|
||||
/****************************************************************************
|
||||
* HDA Controller Register Fields
|
||||
****************************************************************************/
|
||||
|
||||
/* GCAP - Global Capabilities */
|
||||
#define HDAC_GCAP_64OK 0x0001
|
||||
#define HDAC_GCAP_NSDO_MASK 0x0006
|
||||
#define HDAC_GCAP_NSDO_SHIFT 1
|
||||
#define HDAC_GCAP_BSS_MASK 0x00f8
|
||||
#define HDAC_GCAP_BSS_SHIFT 3
|
||||
#define HDAC_GCAP_ISS_MASK 0x0f00
|
||||
#define HDAC_GCAP_ISS_SHIFT 8
|
||||
#define HDAC_GCAP_OSS_MASK 0xf000
|
||||
#define HDAC_GCAP_OSS_SHIFT 12
|
||||
|
||||
#define HDAC_GCAP_NSDO_1SDO 0x00
|
||||
#define HDAC_GCAP_NSDO_2SDO 0x02
|
||||
#define HDAC_GCAP_NSDO_4SDO 0x04
|
||||
|
||||
#define HDAC_GCAP_BSS(gcap) \
|
||||
(((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)
|
||||
#define HDAC_GCAP_ISS(gcap) \
|
||||
(((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)
|
||||
#define HDAC_GCAP_OSS(gcap) \
|
||||
(((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)
|
||||
|
||||
/* GCTL - Global Control */
|
||||
#define HDAC_GCTL_CRST 0x00000001
|
||||
#define HDAC_GCTL_FCNTRL 0x00000002
|
||||
#define HDAC_GCTL_UNSOL 0x00000100
|
||||
|
||||
/* WAKEEN - Wake Enable */
|
||||
#define HDAC_WAKEEN_SDIWEN_MASK 0x7fff
|
||||
#define HDAC_WAKEEN_SDIWEN_SHIFT 0
|
||||
|
||||
/* STATESTS - State Change Status */
|
||||
#define HDAC_STATESTS_SDIWAKE_MASK 0x7fff
|
||||
#define HDAC_STATESTS_SDIWAKE_SHIFT 0
|
||||
|
||||
#define HDAC_STATESTS_SDIWAKE(statests, n) \
|
||||
(((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >> \
|
||||
HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)
|
||||
|
||||
/* GSTS - Global Status */
|
||||
#define HDAC_GSTS_FSTS 0x0002
|
||||
|
||||
/* INTCTL - Interrut Control */
|
||||
#define HDAC_INTCTL_SIE_MASK 0x3fffffff
|
||||
#define HDAC_INTCTL_SIE_SHIFT 0
|
||||
#define HDAC_INTCTL_CIE 0x40000000
|
||||
#define HDAC_INTCTL_GIE 0x80000000
|
||||
|
||||
/* INTSTS - Interrupt Status */
|
||||
#define HDAC_INTSTS_SIS_MASK 0x3fffffff
|
||||
#define HDAC_INTSTS_SIS_SHIFT 0
|
||||
#define HDAC_INTSTS_CIS 0x40000000
|
||||
#define HDAC_INTSTS_GIS 0x80000000
|
||||
|
||||
/* SSYNC - Stream Synchronization */
|
||||
#define HDAC_SSYNC_SSYNC_MASK 0x3fffffff
|
||||
#define HDAC_SSYNC_SSYNC_SHIFT 0
|
||||
|
||||
/* CORBWP - CORB Write Pointer */
|
||||
#define HDAC_CORBWP_CORBWP_MASK 0x00ff
|
||||
#define HDAC_CORBWP_CORBWP_SHIFT 0
|
||||
|
||||
/* CORBRP - CORB Read Pointer */
|
||||
#define HDAC_CORBRP_CORBRP_MASK 0x00ff
|
||||
#define HDAC_CORBRP_CORBRP_SHIFT 0
|
||||
#define HDAC_CORBRP_CORBRPRST 0x8000
|
||||
|
||||
/* CORBCTL - CORB Control */
|
||||
#define HDAC_CORBCTL_CMEIE 0x01
|
||||
#define HDAC_CORBCTL_CORBRUN 0x02
|
||||
|
||||
/* CORBSTS - CORB Status */
|
||||
#define HDAC_CORBSTS_CMEI 0x01
|
||||
|
||||
/* CORBSIZE - CORB Size */
|
||||
#define HDAC_CORBSIZE_CORBSIZE_MASK 0x03
|
||||
#define HDAC_CORBSIZE_CORBSIZE_SHIFT 0
|
||||
#define HDAC_CORBSIZE_CORBSZCAP_MASK 0xf0
|
||||
#define HDAC_CORBSIZE_CORBSZCAP_SHIFT 4
|
||||
|
||||
#define HDAC_CORBSIZE_CORBSIZE_2 0x00
|
||||
#define HDAC_CORBSIZE_CORBSIZE_16 0x01
|
||||
#define HDAC_CORBSIZE_CORBSIZE_256 0x02
|
||||
|
||||
#define HDAC_CORBSIZE_CORBSZCAP_2 0x10
|
||||
#define HDAC_CORBSIZE_CORBSZCAP_16 0x20
|
||||
#define HDAC_CORBSIZE_CORBSZCAP_256 0x40
|
||||
|
||||
#define HDAC_CORBSIZE_CORBSIZE(corbsize) \
|
||||
(((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)
|
||||
|
||||
/* RIRBWP - RIRB Write Pointer */
|
||||
#define HDAC_RIRBWP_RIRBWP_MASK 0x00ff
|
||||
#define HDAC_RIRBWP_RIRBWP_SHIFT 0
|
||||
#define HDAC_RIRBWP_RIRBWPRST 0x8000
|
||||
|
||||
/* RINTCTN - Response Interrupt Count */
|
||||
#define HDAC_RINTCNT_MASK 0x00ff
|
||||
#define HDAC_RINTCNT_SHIFT 0
|
||||
|
||||
/* RIRBCTL - RIRB Control */
|
||||
#define HDAC_RIRBCTL_RINTCTL 0x01
|
||||
#define HDAC_RIRBCTL_RIRBDMAEN 0x02
|
||||
#define HDAC_RIRBCTL_RIRBOIC 0x04
|
||||
|
||||
/* RIRBSTS - RIRB Status */
|
||||
#define HDAC_RIRBSTS_RINTFL 0x01
|
||||
#define HDAC_RIRBSTS_RIRBOIS 0x04
|
||||
|
||||
/* RIRBSIZE - RIRB Size */
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE_MASK 0x03
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT 0
|
||||
#define HDAC_RIRBSIZE_RIRBSZCAP_MASK 0xf0
|
||||
#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT 4
|
||||
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE_2 0x00
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE_16 0x01
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE_256 0x02
|
||||
|
||||
#define HDAC_RIRBSIZE_RIRBSZCAP_2 0x10
|
||||
#define HDAC_RIRBSIZE_RIRBSZCAP_16 0x20
|
||||
#define HDAC_RIRBSIZE_RIRBSZCAP_256 0x40
|
||||
|
||||
#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize) \
|
||||
(((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)
|
||||
|
||||
/* DPLBASE - DMA Position Lower Base Address */
|
||||
#define HDAC_DPLBASE_DPLBASE_MASK 0xffffff80
|
||||
#define HDAC_DPLBASE_DPLBASE_SHIFT 7
|
||||
#define HDAC_DPLBASE_DPLBASE_DMAPBE 0x00000001
|
||||
|
||||
/* SDCTL - Stream Descriptor Control */
|
||||
#define HDAC_SDCTL_SRST 0x000001
|
||||
#define HDAC_SDCTL_RUN 0x000002
|
||||
#define HDAC_SDCTL_IOCE 0x000004
|
||||
#define HDAC_SDCTL_FEIE 0x000008
|
||||
#define HDAC_SDCTL_DEIE 0x000010
|
||||
#define HDAC_SDCTL_STRIPE_MASK 0x030000
|
||||
#define HDAC_SDCTL_STRIPE_SHIFT 16
|
||||
#define HDAC_SDCTL_TP 0x040000
|
||||
#define HDAC_SDCTL_DIR 0x080000
|
||||
#define HDAC_SDCTL2_STRM_MASK 0xf0
|
||||
#define HDAC_SDCTL2_STRM_SHIFT 4
|
||||
|
||||
#define HDAC_SDSTS_DESE (1 << 4)
|
||||
#define HDAC_SDSTS_FIFOE (1 << 3)
|
||||
#define HDAC_SDSTS_BCIS (1 << 2)
|
||||
|
||||
#endif
|
||||
9
sys/modules/sound/driver/hda/Makefile
Normal file
9
sys/modules/sound/driver/hda/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../../../dev/sound/pci/hda
|
||||
|
||||
KMOD= snd_hda
|
||||
SRCS= device_if.h bus_if.h pci_if.h channel_if.h mixer_if.h
|
||||
SRCS+= hdac.c hdac_private.h hdac_reg.h hda_reg.h hdac.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
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Reference in New Issue
Block a user