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The GIC (v2 at least) has a bit in the TYPER register to indicate whether the GIC

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supports the Security Extensions or not. This bit is not the same as the CPU one.
Currently we are not checking for either before trying to write to the special
registers.  This can lead to problems on hardware or simulators that do not
provide the security extensions.  Add the missing checks. Their interactions with
the CPU flag is not entirely clear to me but using a macro will make it easier
to quickly adjust the condition once the CPU bits are sorted as well.

Reviewed by:	br
Sponsored by:	DARPA/AFRL
Differential Revision:	https://reviews.freebsd.org/D6397
This commit is contained in:
Bjoern A. Zeeb 2016-05-17 13:12:26 +00:00
parent cef367e6a1
commit 1f420ed469
3 changed files with 21 additions and 9 deletions
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16
sys/arm/arm/gic.c
View File

@ -108,6 +108,11 @@ __FBSDID("$FreeBSD$");
#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
/* TYPER Registers */
#define GICD_TYPER_SECURITYEXT 0x400
#define GIC_SUPPORT_SECEXT(_sc) \
((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
/* First bit is a polarity bit (0 - low, 1 - high) */
#define GICD_ICFGR_POL_LOW (0 << 0)
#define GICD_ICFGR_POL_HIGH (1 << 0)
@ -172,6 +177,7 @@ struct arm_gic_softc {
uint8_t ver;
struct mtx mutex;
uint32_t nirqs;
uint32_t typer;
#ifdef GIC_DEBUG_SPURIOUS
uint32_t last_irq[MAXCPU];
#endif
@ -299,7 +305,7 @@ arm_gic_init_secondary(device_t dev)
gic_d_write_4(sc, GICD_IPRIORITYR(irq >> 2), 0);
/* Set all the interrupts to be in Group 0 (secure) */
for (irq = 0; irq < sc->nirqs; irq += 32) {
for (irq = 0; GIC_SUPPORT_SECEXT(sc) && irq < sc->nirqs; irq += 32) {
gic_d_write_4(sc, GICD_IGROUPR(irq >> 5), 0);
}
@ -336,7 +342,7 @@ arm_gic_init_secondary(device_t dev)
gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < sc->nirqs; i += 32) {
for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}
@ -639,8 +645,8 @@ arm_gic_attach(device_t dev)
gic_d_write_4(sc, GICD_CTLR, 0x00);
/* Get the number of interrupts */
nirqs = gic_d_read_4(sc, GICD_TYPER);
nirqs = 32 * ((nirqs & 0x1f) + 1);
sc->typer = gic_d_read_4(sc, GICD_TYPER);
nirqs = 32 * ((sc->typer & 0x1f) + 1);
#ifdef INTRNG
if (arm_gic_register_isrcs(sc, nirqs)) {
@ -686,7 +692,7 @@ arm_gic_attach(device_t dev)
}
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < sc->nirqs; i += 32) {
for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}

13
sys/arm64/arm64/gic.c
View File

@ -94,6 +94,11 @@ __FBSDID("$FreeBSD$");
#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
/* TYPER Registers */
#define GICD_TYPER_SECURITYEXT 0x400
#define GIC_SUPPORT_SECEXT(_sc) \
((_sc->typer & GICD_TYPER_SECURITYEXT) == GICD_TYPER_SECURITYEXT)
/* First bit is a polarity bit (0 - low, 1 - high) */
#define GICD_ICFGR_POL_LOW (0 << 0)
#define GICD_ICFGR_POL_HIGH (1 << 0)
@ -164,7 +169,7 @@ gic_init_secondary(device_t dev)
gic_d_write_4(sc, GICD_IPRIORITYR(i >> 2), 0);
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < sc->nirqs; i += 32) {
for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}
@ -221,8 +226,8 @@ arm_gic_attach(device_t dev)
gic_d_write_4(sc, GICD_CTLR, 0x00);
/* Get the number of interrupts */
sc->nirqs = gic_d_read_4(sc, GICD_TYPER);
sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
sc->typer = gic_d_read_4(sc, GICD_TYPER);
sc->nirqs = 32 * ((sc->typer & 0x1f) + 1);
arm_register_root_pic(dev, sc->nirqs);
@ -257,7 +262,7 @@ arm_gic_attach(device_t dev)
}
/* Set all the interrupts to be in Group 0 (secure) */
for (i = 0; i < sc->nirqs; i += 32) {
for (i = 0; GIC_SUPPORT_SECEXT(sc) && i < sc->nirqs; i += 32) {
gic_d_write_4(sc, GICD_IGROUPR(i >> 5), 0);
}

1
sys/arm64/arm64/gic.h
View File

@ -49,6 +49,7 @@ struct arm_gic_softc {
uint8_t ver;
struct mtx mutex;
uint32_t nirqs;
uint32_t typer;
};
DECLARE_CLASS(arm_gicv2m_driver);