MFC r271906:
Make the ARM MPCore Timer driver work with published standard FDT bindings.
This commit is contained in:
ian
parent
839e78bb76
commit
2008cd3c3f
@ -97,36 +97,25 @@ __FBSDID("$FreeBSD$");
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#define GBL_TIMER_INTR_EVENT (1UL << 0)
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struct arm_tmr_softc {
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struct resource * tmr_res[4];
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bus_space_tag_t prv_bst;
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bus_space_tag_t gbl_bst;
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bus_space_handle_t prv_bsh;
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bus_space_handle_t gbl_bsh;
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device_t dev;
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int irqrid;
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int memrid;
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struct resource * gbl_mem;
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struct resource * prv_mem;
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struct resource * prv_irq;
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uint64_t clkfreq;
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struct eventtimer et;
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};
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static struct resource_spec arm_tmr_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Global registers */
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{ SYS_RES_IRQ, 0, RF_ACTIVE }, /* Global timer interrupt (unused) */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Private (per-CPU) registers */
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{ SYS_RES_IRQ, 1, RF_ACTIVE }, /* Private timer interrupt */
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{ -1, 0 }
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};
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static struct arm_tmr_softc *arm_tmr_sc = NULL;
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static uint64_t platform_arm_tmr_freq = 0;
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#define tmr_prv_read_4(reg) \
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bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg)
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#define tmr_prv_write_4(reg, val) \
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bus_space_write_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg, val)
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#define tmr_gbl_read_4(reg) \
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bus_space_read_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg)
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#define tmr_gbl_write_4(reg, val) \
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bus_space_write_4(arm_tmr_sc->gbl_bst, arm_tmr_sc->gbl_bsh, reg, val)
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static struct eventtimer *arm_tmr_et;
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static struct timecounter *arm_tmr_tc;
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static uint64_t arm_tmr_freq;
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static boolean_t arm_tmr_freq_varies;
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#define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
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#define tmr_prv_write_4(sc, reg, val) bus_write_4((sc)->prv_mem, reg, val)
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#define tmr_gbl_read_4(sc, reg) bus_read_4((sc)->gbl_mem, reg)
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#define tmr_gbl_write_4(sc, reg, val) bus_write_4((sc)->gbl_mem, reg, val)
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static timecounter_get_t arm_tmr_get_timecount;
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@ -139,6 +128,21 @@ static struct timecounter arm_tmr_timecount = {
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.tc_quality = 800,
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};
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#define TMR_GBL 0x01
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#define TMR_PRV 0x02
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#define TMR_BOTH (TMR_GBL | TMR_PRV)
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#define TMR_NONE 0
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static struct ofw_compat_data compat_data[] = {
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{"arm,mpcore-timers", TMR_BOTH}, /* Non-standard, FreeBSD. */
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{"arm,cortex-a9-global-timer", TMR_GBL},
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{"arm,cortex-a5-global-timer", TMR_GBL},
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{"arm,cortex-a9-twd-timer", TMR_PRV},
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{"arm,cortex-a5-twd-timer", TMR_PRV},
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{"arm,arm11mp-twd-timer", TMR_PRV},
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{NULL, TMR_NONE}
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};
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/**
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* arm_tmr_get_timecount - reads the timecount (global) timer
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* @tc: pointer to arm_tmr_timecount struct
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@ -152,7 +156,10 @@ static struct timecounter arm_tmr_timecount = {
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static unsigned
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arm_tmr_get_timecount(struct timecounter *tc)
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{
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return (tmr_gbl_read_4(GBL_TIMER_COUNT_LOW));
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struct arm_tmr_softc *sc;
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sc = tc->tc_priv;
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return (tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW));
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}
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/**
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@ -172,11 +179,13 @@ arm_tmr_get_timecount(struct timecounter *tc)
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static int
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arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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{
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struct arm_tmr_softc *sc;
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uint32_t load, count;
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uint32_t ctrl;
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tmr_prv_write_4(PRV_TIMER_CTRL, 0);
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tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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sc = et->et_priv;
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tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
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tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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ctrl = PRV_TIMER_CTRL_IRQ_ENABLE | PRV_TIMER_CTRL_TIMER_ENABLE;
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@ -191,9 +200,9 @@ arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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else
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count = load;
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tmr_prv_write_4(PRV_TIMER_LOAD, load);
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tmr_prv_write_4(PRV_TIMER_COUNT, count);
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tmr_prv_write_4(PRV_TIMER_CTRL, ctrl);
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tmr_prv_write_4(sc, PRV_TIMER_LOAD, load);
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tmr_prv_write_4(sc, PRV_TIMER_COUNT, count);
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tmr_prv_write_4(sc, PRV_TIMER_CTRL, ctrl);
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return (0);
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}
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@ -210,8 +219,11 @@ arm_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
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static int
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arm_tmr_stop(struct eventtimer *et)
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{
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tmr_prv_write_4(PRV_TIMER_CTRL, 0);
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tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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struct arm_tmr_softc *sc;
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sc = et->et_priv;
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tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0);
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tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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return (0);
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}
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@ -227,13 +239,12 @@ arm_tmr_stop(struct eventtimer *et)
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static int
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arm_tmr_intr(void *arg)
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{
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struct arm_tmr_softc *sc = (struct arm_tmr_softc *)arg;
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tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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struct arm_tmr_softc *sc;
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sc = arg;
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tmr_prv_write_4(sc, PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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return (FILTER_HANDLED);
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}
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@ -257,94 +268,74 @@ arm_tmr_probe(device_t dev)
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "arm,mpcore-timers"))
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == TMR_NONE)
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return (ENXIO);
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device_set_desc(dev, "ARM MPCore Timers");
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return (BUS_PROBE_DEFAULT);
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}
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/**
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* arm_tmr_attach - attaches the timer to the simplebus
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* @dev: new device
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*
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* Reserves memory and interrupt resources, stores the softc structure
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* globally and registers both the timecount and eventtimer objects.
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*
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* RETURNS
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* Zero on sucess or ENXIO if an error occuried.
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*/
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static int
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arm_tmr_attach(device_t dev)
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attach_tc(struct arm_tmr_softc *sc)
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{
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int rid;
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if (arm_tmr_tc != NULL)
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return (EBUSY);
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rid = sc->memrid;
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sc->gbl_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->gbl_mem == NULL) {
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device_printf(sc->dev, "could not allocate gbl mem resources\n");
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return (ENXIO);
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}
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tmr_gbl_write_4(sc, GBL_TIMER_CTRL, 0x00000000);
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arm_tmr_timecount.tc_frequency = sc->clkfreq;
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arm_tmr_timecount.tc_priv = sc;
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tc_init(&arm_tmr_timecount);
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arm_tmr_tc = &arm_tmr_timecount;
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tmr_gbl_write_4(sc, GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
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return (0);
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}
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static int
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attach_et(struct arm_tmr_softc *sc)
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{
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struct arm_tmr_softc *sc = device_get_softc(dev);
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phandle_t node;
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pcell_t clock;
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void *ihl;
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boolean_t fixed_freq;
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int irid, mrid;
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if (arm_tmr_sc)
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if (arm_tmr_et != NULL)
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return (EBUSY);
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mrid = sc->memrid;
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sc->prv_mem = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &mrid,
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RF_ACTIVE);
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if (sc->prv_mem == NULL) {
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device_printf(sc->dev, "could not allocate prv mem resources\n");
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return (ENXIO);
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if (platform_arm_tmr_freq == ARM_TMR_FREQUENCY_VARIES) {
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fixed_freq = false;
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} else {
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fixed_freq = true;
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if (platform_arm_tmr_freq != 0) {
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sc->clkfreq = platform_arm_tmr_freq;
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} else {
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/* Get the base clock frequency */
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node = ofw_bus_get_node(dev);
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if ((OF_getencprop(node, "clock-frequency", &clock,
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sizeof(clock))) <= 0) {
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device_printf(dev, "missing clock-frequency "
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"attribute in FDT\n");
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return (ENXIO);
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}
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sc->clkfreq = clock;
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}
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}
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tmr_prv_write_4(sc, PRV_TIMER_CTRL, 0x00000000);
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if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
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device_printf(dev, "could not allocate resources\n");
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irid = sc->irqrid;
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sc->prv_irq = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irid, RF_ACTIVE);
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if (sc->prv_irq == NULL) {
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bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
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device_printf(sc->dev, "could not allocate prv irq resources\n");
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return (ENXIO);
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}
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/* Global timer interface */
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sc->gbl_bst = rman_get_bustag(sc->tmr_res[0]);
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sc->gbl_bsh = rman_get_bushandle(sc->tmr_res[0]);
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/* Private per-CPU timer interface */
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sc->prv_bst = rman_get_bustag(sc->tmr_res[2]);
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sc->prv_bsh = rman_get_bushandle(sc->tmr_res[2]);
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arm_tmr_sc = sc;
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/* Disable both timers to start off */
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tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000);
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tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000);
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if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr,
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if (bus_setup_intr(sc->dev, sc->prv_irq, INTR_TYPE_CLK, arm_tmr_intr,
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NULL, sc, &ihl) != 0) {
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bus_release_resources(dev, arm_tmr_spec, sc->tmr_res);
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device_printf(dev, "Unable to setup the clock irq handler.\n");
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bus_release_resource(sc->dev, SYS_RES_MEMORY, mrid, sc->prv_mem);
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bus_release_resource(sc->dev, SYS_RES_IRQ, irid, sc->prv_irq);
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device_printf(sc->dev, "unable to setup the et irq handler.\n");
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return (ENXIO);
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}
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/*
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* If the clock is fixed-frequency, setup and enable the global timer to
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* use as the timecounter. If it's variable frequency it won't work as
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* a timecounter. We also can't use it for DELAY(), so hopefully the
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* platform provides its own implementation. If it doesn't, ours will
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* get used, but since the frequency isn't set, it will only use the
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* bogus loop counter.
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*/
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if (fixed_freq) {
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tmr_gbl_write_4(GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
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arm_tmr_timecount.tc_frequency = sc->clkfreq;
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tc_init(&arm_tmr_timecount);
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}
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/*
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* Setup and register the eventtimer. Most event timers set their min
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* and max period values to some value calculated from the clock
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@ -364,10 +355,87 @@ arm_tmr_attach(device_t dev)
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sc->et.et_stop = arm_tmr_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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arm_tmr_et = &sc->et;
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return (0);
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}
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/**
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* arm_tmr_attach - attaches the timer to the simplebus
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* @dev: new device
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*
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* Reserves memory and interrupt resources, stores the softc structure
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* globally and registers both the timecount and eventtimer objects.
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*
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* RETURNS
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* Zero on sucess or ENXIO if an error occuried.
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*/
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static int
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arm_tmr_attach(device_t dev)
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{
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struct arm_tmr_softc *sc;
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phandle_t node;
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pcell_t clock;
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int et_err, tc_err, tmrtype;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (arm_tmr_freq_varies) {
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sc->clkfreq = arm_tmr_freq;
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} else {
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if (arm_tmr_freq != 0) {
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sc->clkfreq = arm_tmr_freq;
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} else {
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/* Get the base clock frequency */
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node = ofw_bus_get_node(dev);
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if ((OF_getencprop(node, "clock-frequency", &clock,
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sizeof(clock))) <= 0) {
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device_printf(dev, "missing clock-frequency "
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"attribute in FDT\n");
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return (ENXIO);
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}
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sc->clkfreq = clock;
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}
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}
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tmrtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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tc_err = ENXIO;
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et_err = ENXIO;
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/*
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* If we're handling the global timer and it is fixed-frequency, set it
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* up to use as a timecounter. If it's variable frequency it won't work
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* as a timecounter. We also can't use it for DELAY(), so hopefully the
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* platform provides its own implementation. If it doesn't, ours will
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* get used, but since the frequency isn't set, it will only use the
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* bogus loop counter.
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*/
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if (tmrtype & TMR_GBL) {
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if (!arm_tmr_freq_varies)
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tc_err = attach_tc(sc);
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else if (bootverbose)
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device_printf(sc->dev,
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"not using variable-frequency device as timecounter");
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sc->memrid++;
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sc->irqrid++;
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}
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/* If we are handling the private timer, set it up as an eventtimer. */
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if (tmrtype & TMR_PRV) {
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et_err = attach_et(sc);
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}
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/*
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* If we didn't successfully set up a timecounter or eventtimer then we
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* didn't actually attach at all, return error.
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*/
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if (tc_err != 0 && et_err != 0) {
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return (ENXIO);
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}
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return (0);
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}
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static device_method_t arm_tmr_methods[] = {
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DEVMETHOD(device_probe, arm_tmr_probe),
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DEVMETHOD(device_attach, arm_tmr_attach),
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@ -384,6 +452,8 @@ static devclass_t arm_tmr_devclass;
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EARLY_DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
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BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
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EARLY_DRIVER_MODULE(mp_tmr, ofwbus, arm_tmr_driver, arm_tmr_devclass, 0, 0,
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BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
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/*
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* Handle a change in clock frequency. The mpcore timer runs at half the CPU
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@ -404,10 +474,14 @@ void
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arm_tmr_change_frequency(uint64_t newfreq)
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{
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if (arm_tmr_sc == NULL)
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platform_arm_tmr_freq = newfreq;
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else
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et_change_frequency(&arm_tmr_sc->et, newfreq);
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if (newfreq == ARM_TMR_FREQUENCY_VARIES) {
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arm_tmr_freq_varies = true;
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return;
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}
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arm_tmr_freq = newfreq;
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if (arm_tmr_et != NULL)
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et_change_frequency(arm_tmr_et, newfreq);
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}
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/**
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@ -424,12 +498,13 @@ arm_tmr_change_frequency(uint64_t newfreq)
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static void __used /* Must emit function code for the weak ref below. */
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arm_tmr_DELAY(int usec)
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{
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struct arm_tmr_softc *sc;
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int32_t counts_per_usec;
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int32_t counts;
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uint32_t first, last;
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/* Check the timers are setup, if not just use a for loop for the meantime */
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if (arm_tmr_sc == NULL || arm_tmr_timecount.tc_frequency == 0) {
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if (arm_tmr_tc == NULL || arm_tmr_timecount.tc_frequency == 0) {
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for (; usec > 0; usec--)
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for (counts = 200; counts > 0; counts--)
|
||||
cpufunc_nullop(); /* Prevent gcc from optimizing
|
||||
@ -438,6 +513,8 @@ arm_tmr_DELAY(int usec)
|
||||
return;
|
||||
}
|
||||
|
||||
sc = arm_tmr_tc->tc_priv;
|
||||
|
||||
/* Get the number of times to count */
|
||||
counts_per_usec = ((arm_tmr_timecount.tc_frequency / 1000000) + 1);
|
||||
|
||||
@ -452,10 +529,10 @@ arm_tmr_DELAY(int usec)
|
||||
else
|
||||
counts = usec * counts_per_usec;
|
||||
|
||||
first = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
|
||||
first = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
|
||||
|
||||
while (counts > 0) {
|
||||
last = tmr_gbl_read_4(GBL_TIMER_COUNT_LOW);
|
||||
last = tmr_gbl_read_4(sc, GBL_TIMER_COUNT_LOW);
|
||||
counts -= (int32_t)(last - first);
|
||||
first = last;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user