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Sponsored by:	The FreeBSD Foundation
This commit is contained in:
gjb 2016-01-20 17:08:01 +00:00
commit 206c677651
50 changed files with 3466 additions and 759 deletions
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2
share/misc/committers-src.dot
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@ -316,6 +316,7 @@ weongyo [label="Weongyo Jeong\nweongyo@FreeBSD.org\n2007/12/21"]
wes [label="Wes Peters\nwes@FreeBSD.org\n1998/11/25"]
whu [label="Wei Hu\nwhu@FreeBSD.org\n2015/02/11"]
wkoszek [label="Wojciech A. Koszek\nwkoszek@FreeBSD.org\n2006/02/21"]
wma [label="Wojciech Macek\nwma@FreeBSD.org\n2016/01/18"]
wollman [label="Garrett Wollman\nwollman@FreeBSD.org\n????/??/??"]
wsalamon [label="Wayne Salamon\nwsalamon@FreeBSD.org\n2005/06/25"]
yongari [label="Pyun YongHyeon\nyongari@FreeBSD.org\n2004/08/01"]
@ -391,6 +392,7 @@ cognet -> jceel
cognet -> kevlo
cognet -> ian
cognet -> wkoszek
cognet -> wma
cognet -> zbb
cperciva -> eadler

2
share/misc/organization.dot
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@ -30,7 +30,7 @@ coresecretary [label="Core Team Secretary\ncore-secretary@FreeBSD.org\nmatthew"]
doccommitters [label="Doc/www Committers\ndoc-committers@FreeBSD.org"]
doceng [label="Documentation Engineering Team\ndoceng@FreeBSD.org\ngjb, blackend,\ngabor, hrs"]
portscommitters [label="Ports Committers\nports-committers@FreeBSD.org"]
portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bapt, bdrewery,\nerwin, mat, swills"]
portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bapt, bdrewery,\nerwin, mat, swills,\nmiwi"]
portmgrsecretary [label="Port Management Team Secretary\nportmgr-secretary@FreeBSD.org\nculot"]
re [label="Primary Release Engineering Team\nre@FreeBSD.org\nkib, blackend, jpaetzel, hrs, kensmith"]
secteam [label="Security Team\nsecteam@FreeBSD.org\nsimon, qingli, delphij,\nremko, philip, stas, cperciva,\ncsjp, rwatson, miwi, bz"]

6
sys/arm/arm/gic.c
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@ -336,9 +336,11 @@ gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
* 2 = high-to-low edge triggered
* 4 = active high level-sensitive
* 8 = active low level-sensitive
* The hardware only supports active-high-level or rising-edge.
* The hardware only supports active-high-level or rising-edge
* for SPIs
*/
if (fdt32_to_cpu(intr[2]) & 0x0a) {
if (*interrupt >= GIC_FIRST_SPI &&
fdt32_to_cpu(intr[2]) & 0x0a) {
printf("unsupported trigger/polarity configuration "
"0x%02x\n", fdt32_to_cpu(intr[2]) & 0x0f);
}

84
sys/arm/conf/ARMADA38X Normal file
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@ -0,0 +1,84 @@
#
# Kernel configuration for Marvell Armada38x
#
# $FreeBSD$
#
include "../mv/armada38x/std.armada38x"
include "std.armv6"
ident ARMADA38X
options SOC_MV_ARMADA38X
makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
makeoptions WERROR="-Werror"
options MD_ROOT
#makeoptions MFS_IMAGE=/path/to/miniroot
#options ROOTDEVNAME=\"ufs:md0\"
options ROOTDEVNAME=\"/dev/da0s1a\"
options SCHED_ULE # ULE scheduler
#options SCHED_4BSD # 4BSD scheduler
options SMP
# Debugging
#options DEBUG
#options VERBOSE_SYSINIT
options ALT_BREAK_TO_DEBUGGER
options DDB
#options GDB
#options DIAGNOSTIC
options INVARIANTS # Enable calls of extra sanity checking
options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS
options KDB
options KDB_TRACE
#options WITNESS # Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
#options WITNESS_KDB
#options BOOTVERBOSE
# Pseudo devices
device random
device pty
device loop
device md
# Serial ports
device uart
device uart_ns8250
# Network
device ether
device vlan
device mii
device bpf
device re
# PCI
device pci
# Interrupt controllers
device gic
# Timers
device mpcore_timer
# USB
device usb
device ehci
device umass
device scbus
device pass
device da
# I2C
device iic
device iicbus
#FDT
options FDT
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=armada-388-gp.dts

3
sys/arm/conf/DB-78XXX
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@ -90,6 +90,9 @@ device mvs
# NAND
device nand
# GPIO
device gpio
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC

3
sys/arm/conf/DB-88F5XXX
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@ -88,6 +88,9 @@ device da
# SATA
device mvs
# GPIO
device gpio
# Flattened Device Tree
options FDT
makeoptions FDT_DTS_FILE=db88f5281.dts

3
sys/arm/conf/DB-88F6XXX
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@ -94,6 +94,9 @@ device mvs
# NAND
device nand
# GPIO
device gpio
# Flattened Device Tree
options FDT # Configure using FDT/DTB data
options FDT_DTB_STATIC

3
sys/arm/conf/DOCKSTAR
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@ -148,6 +148,9 @@ device pf
device pflog
device pfsync
# GPIO
device gpio
# ALTQ, required for PF
options ALTQ # Basic ALTQ support
options ALTQ_CBQ # Class Based Queueing

3
sys/arm/conf/DREAMPLUG-1001
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@ -122,6 +122,9 @@ device u3g # USB-based 3G modems (Option, Huawei, Sierra)
device iic
device iicbus
# GPIO
device gpio
# SATA
device mvs
device ahci

3
sys/arm/conf/SHEEVAPLUG
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@ -82,6 +82,9 @@ device da
# NAND
device nand
# GPIO
device gpio
# Flattened Device Tree
options FDT # Configure using FDT/DTB data
options FDT_DTB_STATIC

3
sys/arm/conf/TS7800
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@ -76,6 +76,9 @@ device da
# SATA
device ata
# GPIO
device gpio
# Flattened Device Tree
options FDT
options FDT_DTB_STATIC

137
sys/arm/mv/armada38x/armada38x.c Normal file
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@ -0,0 +1,137 @@
/*-
* Copyright (c) 2015 Semihalf.
* Copyright (c) 2015 Stormshield.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/fdt.h>
#include <arm/mv/mvwin.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
int armada38x_open_bootrom_win(void);
int armada38x_scu_enable(void);
int armada38x_win_set_iosync_barrier(void);
uint32_t
get_tclk(void)
{
uint32_t sar;
/*
* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
* Current setting is read from Sample At Reset register.
*/
sar = (uint32_t)get_sar_value();
sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
if (sar == 0)
return (TCLK_250MHZ);
else
return (TCLK_200MHZ);
}
int
armada38x_win_set_iosync_barrier(void)
{
bus_space_handle_t vaddr_iowind;
int rv;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
if (rv != 0)
return (rv);
/* Set Sync Barrier flags for all Mbus internal units */
bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,
MV_SYNC_BARRIER_CTRL_ALL);
bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,
MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);
bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
return (rv);
}
int
armada38x_open_bootrom_win(void)
{
bus_space_handle_t vaddr_iowind;
uint32_t val;
int rv;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
if (rv != 0)
return (rv);
val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT;
val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT;
val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT;
/* Enable window and Sync Barrier */
val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT;
val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT;
/* Configure IO Window Control Register */
bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET,
val);
/* Configure IO Window Base Register */
bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET,
MV_BOOTROM_MEM_ADDR);
bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN,
BUS_SPACE_BARRIER_WRITE);
bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
return (rv);
}
int
armada38x_scu_enable(void)
{
bus_space_handle_t vaddr_scu;
int rv;
uint32_t val;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
MV_SCU_REGS_LEN, 0, &vaddr_scu);
if (rv != 0)
return (rv);
/* Enable SCU */
val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
if (!(val & MV_SCU_ENABLE))
bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
val | MV_SCU_ENABLE);
bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
return (0);
}

166
sys/arm/mv/armada38x/armada38x_mp.c Normal file
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@ -0,0 +1,166 @@
/*-
* Copyright (c) 2015 Semihalf.
* Copyright (c) 2015 Stormshield.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/smp.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <arm/mv/mvreg.h>
#include "pmsu.h"
int cpu_reset_deassert(void);
int
cpu_reset_deassert(void)
{
bus_space_handle_t vaddr;
uint32_t reg;
int rv;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
MV_CPU_RESET_REGS_LEN, 0, &vaddr);
if (rv != 0)
return (rv);
/* CPU1 is held at reset by default - clear assert bit to release it */
reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
reg &= ~CPU_RESET_ASSERT;
bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
return (0);
}
static int
platform_cnt_cpus(void)
{
bus_space_handle_t vaddr_scu;
phandle_t cpus_node, child;
char device_type[16];
int fdt_cpu_count = 0;
int reg_cpu_count = 0;
uint32_t val;
int rv;
cpus_node = OF_finddevice("/cpus");
if (cpus_node == -1) {
/* Default is one core */
mp_ncpus = 1;
return (0);
}
/* Get number of 'cpu' nodes from FDT */
for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
/* Check if child is a CPU */
memset(device_type, 0, sizeof(device_type));
rv = OF_getprop(child, "device_type", device_type,
sizeof(device_type) - 1);
if (rv < 0)
continue;
if (strcmp(device_type, "cpu") != 0)
continue;
fdt_cpu_count++;
}
/* Get number of CPU cores from SCU register to cross-check with FDT */
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
MV_SCU_REGS_LEN, 0, &vaddr_scu);
if (rv != 0) {
/* Default is one core */
mp_ncpus = 1;
return (0);
}
val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
/* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
/* mp_ncpus must be at least 1 */
mp_ncpus = max(1, mp_ncpus);
return (mp_ncpus);
}
void
platform_mp_setmaxid(void)
{
/* Armada38x family supports maximum 2 cores */
mp_ncpus = platform_cnt_cpus();
mp_maxid = 1;
}
int
platform_mp_probe(void)
{
return (mp_ncpus > 1);
}
void
platform_mp_init_secondary(void)
{
intr_pic_init_secondary();
}
void
platform_mp_start_ap(void)
{
int rv;
/* Write secondary entry address to PMSU register */
rv = pmsu_boot_secondary_cpu();
if (rv != 0)
return;
/* Release CPU1 from reset */
cpu_reset_deassert();
}
void
platform_ipi_send(cpuset_t cpus, u_int ipi)
{
pic_ipi_send(cpus, ipi);
}

6
sys/arm/mv/armada38x/files.armada38x Normal file
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@ -0,0 +1,6 @@
# $FreeBSD$
arm/mv/armada38x/armada38x.c standard
arm/mv/armada38x/armada38x_mp.c optional smp
arm/mv/armada38x/pmsu.c standard
arm/mv/armada38x/rtc.c standard

154
sys/arm/mv/armada38x/pmsu.c Normal file
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@ -0,0 +1,154 @@
/*-
* Copyright (c) 2015 Semihalf.
* Copyright (c) 2015 Stormshield.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/rman.h>
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/resource.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/fdt.h>
#include <machine/smp.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <arm/mv/mvreg.h>
#include "pmsu.h"
static struct resource_spec pmsu_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
};
struct pmsu_softc {
device_t dev;
struct resource *res;
};
static int pmsu_probe(device_t dev);
static int pmsu_attach(device_t dev);
static int pmsu_detach(device_t dev);
static device_method_t pmsu_methods[] = {
DEVMETHOD(device_probe, pmsu_probe),
DEVMETHOD(device_attach, pmsu_attach),
DEVMETHOD(device_detach, pmsu_detach),
{ 0, 0 }
};
static driver_t pmsu_driver = {
"pmsu",
pmsu_methods,
sizeof(struct pmsu_softc)
};
static devclass_t pmsu_devclass;
DRIVER_MODULE(pmsu, simplebus, pmsu_driver, pmsu_devclass, 0, 0);
DRIVER_MODULE(pmsu, ofwbus, pmsu_driver, pmsu_devclass, 0, 0);
static int
pmsu_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "marvell,armada-380-pmsu"))
return (ENXIO);
device_set_desc(dev, "Power Management Service Unit");
return (BUS_PROBE_DEFAULT);
}
static int
pmsu_attach(device_t dev)
{
struct pmsu_softc *sc;
int err;
sc = device_get_softc(dev);
sc->dev = dev;
err = bus_alloc_resources(dev, pmsu_spec, &sc->res);
if (err != 0) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
return (0);
}
static int
pmsu_detach(device_t dev)
{
struct pmsu_softc *sc;
sc = device_get_softc(dev);
bus_release_resources(dev, pmsu_spec, &sc->res);
return (0);
}
#ifdef SMP
int
pmsu_boot_secondary_cpu(void)
{
bus_space_handle_t vaddr;
int rv;
rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_PMSU_BASE, MV_PMSU_REGS_LEN,
0, &vaddr);
if (rv != 0)
return (rv);
/* Boot cpu1 */
bus_space_write_4(fdtbus_bs_tag, vaddr, PMSU_BOOT_ADDR_REDIRECT_OFFSET(1),
pmap_kextract((vm_offset_t)mpentry));
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);
return (0);
}
#endif

35
sys/arm/mv/armada38x/pmsu.h Normal file
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@ -0,0 +1,35 @@
/*-
* Copyright (c) 2015 Semihalf.
* Copyright (c) 2015 Stormshield.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include "opt_global.h"
#ifdef SMP
/* Boot secondary core using PMSU */
int pmsu_boot_secondary_cpu(void);
#endif

235
sys/arm/mv/armada38x/rtc.c Normal file
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@ -0,0 +1,235 @@
/*-
* Copyright (c) 2015 Semihalf.
* Copyright (c) 2015 Stormshield.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/lock.h>
#include <sys/time.h>
#include <sys/proc.h>
#include <sys/conf.h>
#include <sys/rman.h>
#include <sys/clock.h>
#include <sys/systm.h>
#include <sys/mutex.h>
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/resource.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include "clock_if.h"
#define RTC_RES_US 1000000
#define HALF_OF_SEC_NS 500000000
#define RTC_STATUS 0x0
#define RTC_TIME 0xC
#define MV_RTC_LOCK(sc) mtx_lock(&(sc)->mutex)
#define MV_RTC_UNLOCK(sc) mtx_unlock(&(sc)->mutex)
static struct resource_spec res_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0 }
};
struct mv_rtc_softc {
device_t dev;
struct resource *res;
struct mtx mutex;
};
static int mv_rtc_probe(device_t dev);
static int mv_rtc_attach(device_t dev);
static int mv_rtc_detach(device_t dev);
static int mv_rtc_gettime(device_t dev, struct timespec *ts);
static int mv_rtc_settime(device_t dev, struct timespec *ts);
static uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off);
static int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off,
uint32_t val);
static device_method_t mv_rtc_methods[] = {
DEVMETHOD(device_probe, mv_rtc_probe),
DEVMETHOD(device_attach, mv_rtc_attach),
DEVMETHOD(device_detach, mv_rtc_detach),
DEVMETHOD(clock_gettime, mv_rtc_gettime),
DEVMETHOD(clock_settime, mv_rtc_settime),
{ 0, 0 },
};
static driver_t mv_rtc_driver = {
"rtc",
mv_rtc_methods,
sizeof(struct mv_rtc_softc),
};
static devclass_t mv_rtc_devclass;
DRIVER_MODULE(mv_rtc, simplebus, mv_rtc_driver, mv_rtc_devclass, 0, 0);
static int
mv_rtc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "marvell,armada-380-rtc"))
return (ENXIO);
device_set_desc(dev, "Marvell Integrated RTC");
return (BUS_PROBE_DEFAULT);
}
static int
mv_rtc_attach(device_t dev)
{
struct mv_rtc_softc *sc;
int unit, ret;
unit = device_get_unit(dev);
sc = device_get_softc(dev);
sc->dev = dev;
clock_register(dev, RTC_RES_US);
mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_DEF);
ret = bus_alloc_resources(dev, res_spec, &sc->res);
if (ret != 0) {
device_printf(dev, "could not allocate resources\n");
mtx_destroy(&sc->mutex);
return (ENXIO);
}
return (0);
}
static int
mv_rtc_detach(device_t dev)
{
struct mv_rtc_softc *sc;
sc = device_get_softc(dev);
mtx_destroy(&sc->mutex);
bus_release_resources(dev, res_spec, &sc->res);
return (0);
}
static int
mv_rtc_gettime(device_t dev, struct timespec *ts)
{
struct mv_rtc_softc *sc;
uint32_t val, val_check;
sc = device_get_softc(dev);
MV_RTC_LOCK(sc);
/*
* According to HW Errata if more than one second between
* two time reads is detected, then read once again
*/
val = mv_rtc_reg_read(sc, RTC_TIME);
val_check = mv_rtc_reg_read(sc, RTC_TIME);
if (val_check - val > 1)
val_check = mv_rtc_reg_read(sc, RTC_TIME);
MV_RTC_UNLOCK(sc);
ts->tv_sec = val_check;
/* RTC resolution is 1 sec */
ts->tv_nsec = 0;
return (0);
}
static int
mv_rtc_settime(device_t dev, struct timespec *ts)
{
struct mv_rtc_softc *sc;
sc = device_get_softc(dev);
/* RTC resolution is 1 sec */
if (ts->tv_nsec >= HALF_OF_SEC_NS)
ts->tv_sec++;
ts->tv_nsec = 0;
MV_RTC_LOCK(sc);
/*
* According to errata FE-3124064, Write to RTC TIME register
* may fail. As a workaround, before writing to RTC TIME register,
* issue a dummy write of 0x0 twice to RTC Status register.
*/
mv_rtc_reg_write(sc, RTC_STATUS, 0x0);
mv_rtc_reg_write(sc, RTC_STATUS, 0x0);
mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec);
MV_RTC_UNLOCK(sc);
return (0);
}
static uint32_t
mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off)
{
return (bus_read_4(sc->res, off));
}
/*
* According to the datasheet, the OS should wait 5us after every
* register write to the RTC hard macro so that the required update
* can occur without holding off the system bus
*/
static int
mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val)
{
bus_write_4(sc->res, off, val);
DELAY(5);
return (0);
}

12
sys/arm/mv/armada38x/std.armada38x Normal file
View File

@ -0,0 +1,12 @@
# $FreeBSD$
files "../mv/armada38x/files.armada38x"
files "../mv/files.mv"
cpu CPU_CORTEXA
machine arm armv6
makeoptions CONF_CFLAGS="-march=armv7a"
makeoptions KERNVIRTADDR=0xc0000000
options KERNVIRTADDR=0xc0000000
options IPI_IRQ_START=0
options IPI_IRQ_END=15

7
sys/arm/mv/armadaxp/armadaxp.c
View File

@ -86,13 +86,6 @@ int platform_get_ncpus(void);
#define COHER_FABRIC_CFU 0x28
#define COHER_FABRIC_CIB_CTRL 0x80
/* XXX Make gpio driver optional and remove it */
struct resource_spec mv_gpio_res[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
{ -1, 0 }
};
struct vco_freq_ratio {
uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */
uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */

2
sys/arm/mv/files.mv
View File

@ -12,7 +12,7 @@
# - JTAG/ICE
# - Vector Floating Point (VFP) unit
#
arm/mv/gpio.c standard
arm/mv/gpio.c optional gpio
arm/mv/mv_common.c standard
arm/mv/mv_localbus.c standard
arm/mv/mv_machdep.c standard

30
sys/arm/mv/mv_common.c
View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <machine/fdt.h>
#include <machine/vmparam.h>
#include <machine/intr.h>
#include <arm/mv/mvreg.h>
#include <arm/mv/mvvar.h>
@ -104,6 +105,10 @@ static void decode_win_idma_dump(u_long base);
static void decode_win_xor_dump(u_long base);
static int fdt_get_ranges(const char *, void *, int, int *, int *);
#ifdef SOC_MV_ARMADA38X
int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
int *trig, int *pol);
#endif
static int win_cpu_from_dt(void);
static int fdt_win_setup(void);
@ -260,7 +265,7 @@ write_cpu_ctrl(uint32_t reg, uint32_t val)
bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
}
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
uint32_t
read_cpu_mp_clocks(uint32_t reg)
{
@ -294,7 +299,7 @@ void
cpu_reset(void)
{
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
#else
@ -442,6 +447,15 @@ soc_identify(void)
else if (r == 1)
rev = "A1";
break;
case MV_DEV_88F6828:
dev = "Marvell 88F6828";
break;
case MV_DEV_88F6820:
dev = "Marvell 88F6820";
break;
case MV_DEV_88F6810:
dev = "Marvell 88F6810";
break;
case MV_DEV_MV78100_Z0:
dev = "Marvell MV78100 Z0";
break;
@ -719,6 +733,9 @@ win_cpu_can_remap(int i)
(dev == MV_DEV_88F5281 && i < 4) ||
(dev == MV_DEV_88F6281 && i < 4) ||
(dev == MV_DEV_88F6282 && i < 4) ||
(dev == MV_DEV_88F6828 && i < 20) ||
(dev == MV_DEV_88F6820 && i < 20) ||
(dev == MV_DEV_88F6810 && i < 20) ||
(dev == MV_DEV_88RC8180 && i < 2) ||
(dev == MV_DEV_88F6781 && i < 4) ||
(dev == MV_DEV_MV78100_Z0 && i < 8) ||
@ -2055,7 +2072,7 @@ fdt_win_setup(void)
*/
child = OF_peer(child);
if ((child == 0) && (node == OF_finddevice("/"))) {
node = fdt_find_compatible(node, "simple-bus", 1);
node = fdt_find_compatible(node, "simple-bus", 0);
if (node == 0)
return (ENXIO);
child = OF_child(node);
@ -2181,6 +2198,9 @@ fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
}
fdt_pic_decode_t fdt_pic_table[] = {
#ifdef SOC_MV_ARMADA38X
&gic_decode_fdt,
#endif
&fdt_pic_decode_ic,
NULL
};
@ -2195,6 +2215,10 @@ get_sar_value(void)
SAMPLE_AT_RESET_HI);
sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
SAMPLE_AT_RESET_LO);
#elif defined(SOC_MV_ARMADA38X)
sar_high = 0;
sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
SAMPLE_AT_RESET);
#else
/*
* TODO: Add getting proper values for other SoC configurations

18
sys/arm/mv/mv_machdep.c
View File

@ -66,6 +66,11 @@ static int platform_mpp_init(void);
void armadaxp_init_coher_fabric(void);
void armadaxp_l2_init(void);
#endif
#if defined(SOC_MV_ARMADA38X)
int armada38x_win_set_iosync_barrier(void);
int armada38x_scu_enable(void);
int armada38x_open_bootrom_win(void);
#endif
#define MPP_PIN_MAX 68
#define MPP_PIN_CELLS 2
@ -249,6 +254,19 @@ platform_late_init(void)
#endif
armadaxp_l2_init();
#endif
#if defined(SOC_MV_ARMADA38X)
/* Set IO Sync Barrier bit for all Mbus devices */
if (armada38x_win_set_iosync_barrier() != 0)
printf("WARNING: could not map CPU Subsystem registers\n");
if (armada38x_scu_enable() != 0)
printf("WARNING: could not enable SCU\n");
#ifdef SMP
/* Open window to bootROM memory - needed for SMP */
if (armada38x_open_bootrom_win() != 0)
printf("WARNING: could not open window to bootROM\n");
#endif
#endif
}
#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)

25
sys/arm/mv/mv_pci.c
View File

@ -1,7 +1,7 @@
/*-
* Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
* Copyright (c) 2010 The FreeBSD Foundation
* Copyright (c) 2010-2012 Semihalf
* Copyright (c) 2010-2015 Semihalf
* All rights reserved.
*
* Developed by Semihalf.
@ -1016,6 +1016,25 @@ mv_pcib_maxslots(device_t dev)
return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
}
static int
mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
{
#if defined(SOC_MV_ARMADA38X)
struct mv_pcib_softc *sc = device_get_softc(dev);
uint32_t vendor, device;
vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
PCIR_VENDOR_LENGTH);
device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
#else
/* On platforms other than Armada38x, root link is always at slot 0 */
return (slot == 0);
#endif
}
static uint32_t
mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, int bytes)
@ -1024,7 +1043,7 @@ mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
/* Return ~0 if link is inactive or trying to read from Root */
if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
PCIE_STATUS_LINK_DOWN) || (slot == 0))
PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
return (~0U);
return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
@ -1038,7 +1057,7 @@ mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
/* Return if link is inactive or trying to write to Root */
if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
PCIE_STATUS_LINK_DOWN) || (slot == 0))
PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
return;
mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);

52
sys/arm/mv/mvreg.h
View File

@ -34,6 +34,8 @@
#ifndef _MVREG_H_
#define _MVREG_H_
#include <arm/mv/mvwin.h>
#if defined(SOC_MV_DISCOVERY)
#define IRQ_CAUSE_ERROR 0x0
#define IRQ_CAUSE 0x4
@ -123,8 +125,9 @@
/*
* System reset
*/
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define RSTOUTn_MASK 0x60
#define RSTOUTn_MASK_WD 0x400
#define SYSTEM_SOFT_RESET 0x64
#define WD_RSTOUTn_MASK 0x4
#define WD_GLOBAL_MASK 0x00000100
@ -217,8 +220,10 @@
#define CPU_TIMER0_AUTO 0x00000002
#define CPU_TIMER1_EN 0x00000004
#define CPU_TIMER1_AUTO 0x00000008
#define CPU_TIMER_WD_EN 0x00000010
#define CPU_TIMER_WD_AUTO 0x00000020
#define CPU_TIMER2_EN 0x00000010
#define CPU_TIMER2_AUTO 0x00000020
#define CPU_TIMER_WD_EN 0x00000100
#define CPU_TIMER_WD_AUTO 0x00000200
/* 25MHz mode is Armada XP - specific */
#define CPU_TIMER_WD_25MHZ_EN 0x00000400
#define CPU_TIMER0_25MHZ_EN 0x00000800
@ -346,6 +351,8 @@
#define SAMPLE_AT_RESET 0x30
#elif defined(SOC_MV_FREY)
#define SAMPLE_AT_RESET 0x100
#elif defined(SOC_MV_ARMADA38X)
#define SAMPLE_AT_RESET 0x400
#endif
#if defined(SOC_MV_DISCOVERY)
#define SAMPLE_AT_RESET_LO 0x30
@ -370,6 +377,9 @@
#elif defined(SOC_MV_LOKIPLUS)
#define TCLK_MASK 0x0000F000
#define TCLK_SHIFT 0x0C
#elif defined(SOC_MV_ARMADA38X)
#define TCLK_MASK 0x00008000
#define TCLK_SHIFT 15
#endif
#define TCLK_100MHZ 100000000
@ -415,6 +425,9 @@
#define MV_DEV_88F6281 0x6281
#define MV_DEV_88F6282 0x6282
#define MV_DEV_88F6781 0x6781
#define MV_DEV_88F6828 0x6828
#define MV_DEV_88F6820 0x6820
#define MV_DEV_88F6810 0x6810
#define MV_DEV_MV78100_Z0 0x6381
#define MV_DEV_MV78100 0x7810
#define MV_DEV_MV78130 0x7813
@ -428,6 +441,7 @@
#define MV_DEV_FAMILY_MASK 0xff00
#define MV_DEV_DISCOVERY 0x7800
#define MV_DEV_ARMADA38X 0x6800
/*
* Doorbell register control
@ -444,4 +458,36 @@
#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4)
#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
#endif
/*
* SCU
*/
#if defined(SOC_MV_ARMADA38X)
#define MV_SCU_BASE (MV_BASE + 0xc000)
#define MV_SCU_REGS_LEN 0x100
#define MV_SCU_REG_CTRL 0x00
#define MV_SCU_REG_CONFIG 0x04
#define MV_SCU_ENABLE 1
#define SCU_CFG_REG_NCPU_MASK 0x3
#endif
/*
* PMSU
*/
#if defined(SOC_MV_ARMADA38X)
#define MV_PMSU_BASE (MV_BASE + 0x22000)
#define MV_PMSU_REGS_LEN 0x1000
#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124)
#endif
/*
* CPU RESET
*/
#if defined(SOC_MV_ARMADA38X)
#define MV_CPU_RESET_BASE (MV_BASE + 0x20800)
#define MV_CPU_RESET_REGS_LEN 0x8
#define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8)
#define CPU_RESET_ASSERT 0x1
#endif
#endif /* _MVREG_H_ */

2
sys/arm/mv/mvvar.h
View File

@ -109,7 +109,7 @@ uint32_t get_l2clk(void);
uint32_t read_cpu_ctrl(uint32_t);
void write_cpu_ctrl(uint32_t, uint32_t);
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
uint32_t read_cpu_mp_clocks(uint32_t reg);
void write_cpu_mp_clocks(uint32_t reg, uint32_t val);
uint32_t read_cpu_misc(uint32_t reg);

45
sys/arm/mv/mvwin.h
View File

@ -73,6 +73,8 @@
#define MV_PCI_PORTS 2 /* 2x PCIE */
#elif defined(SOC_MV_ARMADAXP)
#define MV_PCI_PORTS 3 /* 3x PCIE */
#elif defined(SOC_MV_ARMADA38X)
#define MV_PCI_PORTS 4 /* 4x PCIE */
#else
#error "MV_PCI_PORTS not configured !"
#endif
@ -122,14 +124,14 @@
#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100)
#elif defined(SOC_MV_LOKIPLUS)
#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500)
#elif defined(SOC_MV_ARMADAXP)
#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_DDR_CADR_BASE (MV_BASE + 0x20180)
#else
#define MV_DDR_CADR_BASE (MV_BASE + 0x1500)
#endif
#define MV_MPP_BASE (MV_BASE + 0x10000)
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_MISC_BASE (MV_BASE + 0x18200)
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
@ -148,6 +150,8 @@
#if defined(SOC_MV_FREY)
#define MV_PCIE_BASE (MV_BASE + 0x8000)
#elif defined(SOC_MV_ARMADA38X)
#define MV_PCIE_BASE (MV_BASE + 0x80000)
#else
#define MV_PCIE_BASE (MV_BASE + 0x40000)
#endif
@ -168,7 +172,7 @@
/*
* Decode windows definitions and macros
*/
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8)))
#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4)
#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008)
@ -182,7 +186,7 @@
#if defined(SOC_MV_DISCOVERY)
#define MV_WIN_CPU_MAX 14
#elif defined(SOC_MV_ARMADAXP)
#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_WIN_CPU_MAX 20
#else
#define MV_WIN_CPU_MAX 8
@ -267,6 +271,10 @@
#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2)))
#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2)))
#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2)))
#elif defined(SOC_MV_ARMADA38X)
#define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4)
#define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
#define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
#elif defined(SOC_MV_ORION)
#define MV_WIN_PCIE_TARGET(n) 4
#define MV_WIN_PCIE_MEM_ATTR(n) 0x59
@ -303,6 +311,35 @@
#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34)
#define MV_WIN_SATA_MAX 4
#if defined(SOC_MV_ARMADA38X)
#define MV_BOOTROM_MEM_ADDR 0xFFF00000
#define MV_BOOTROM_WIN_SIZE 0xF
#define MV_CPU_SUBSYS_REGS_LEN 0x100
/* IO Window Control Register fields */
#define IO_WIN_SIZE_SHIFT 16
#define IO_WIN_SIZE_MASK 0xFFFF
#define IO_WIN_ATTR_SHIFT 8
#define IO_WIN_ATTR_MASK 0xFF
#define IO_WIN_TGT_SHIFT 4
#define IO_WIN_TGT_MASK 0xF
#define IO_WIN_SYNC_SHIFT 1
#define IO_WIN_SYNC_MASK 0x1
#define IO_WIN_ENA_SHIFT 0
#define IO_WIN_ENA_MASK 0x1
#define IO_WIN_9_CTRL_OFFSET 0x98
#define IO_WIN_9_BASE_OFFSET 0x9C
/* Mbus decoding unit IDs and attributes */
#define MBUS_BOOTROM_TGT_ID 0x1
#define MBUS_BOOTROM_ATTR 0x1D
/* Internal Units Sync Barrier Control Register */
#define MV_SYNC_BARRIER_CTRL 0x84
#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF
#endif
#define WIN_REG_IDX_RD(pre,reg,off,base) \
static __inline uint32_t \
pre ## _ ## reg ## _read(int i) \

83
sys/arm/mv/timer.c
View File

@ -54,26 +54,44 @@ __FBSDID("$FreeBSD$");
#define INITIAL_TIMECOUNTER (0xffffffff)
#define MAX_WATCHDOG_TICKS (0xffffffff)
#if defined(SOC_MV_ARMADAXP)
#define MV_TMR 0x1
#define MV_WDT 0x2
#define MV_NONE 0x0
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
#else
#define MV_CLOCK_SRC get_tclk()
#endif
#if defined(SOC_MV_ARMADA38X)
#define WATCHDOG_TIMER 4
#else
#define WATCHDOG_TIMER 2
#endif
struct mv_timer_softc {
struct resource * timer_res[2];
bus_space_tag_t timer_bst;
bus_space_handle_t timer_bsh;
struct mtx timer_mtx;
struct eventtimer et;
boolean_t has_wdt;
};
static struct resource_spec mv_timer_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE },
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL },
{ -1, 0 }
};
/* Interrupt is not required by MV_WDT devices */
static struct ofw_compat_data mv_timer_compat[] = {
{"mrvl,timer", MV_TMR | MV_WDT },
{"marvell,armada-380-wdt", MV_WDT },
{NULL, MV_NONE }
};
static struct mv_timer_softc *timer_softc = NULL;
static int timers_initialized = 0;
@ -111,7 +129,7 @@ mv_timer_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "mrvl,timer"))
if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)
return (ENXIO);
device_set_desc(dev, "Marvell CPU Timer");
@ -124,7 +142,7 @@ mv_timer_attach(device_t dev)
int error;
void *ihl;
struct mv_timer_softc *sc;
#if !defined(SOC_MV_ARMADAXP)
#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_cause, irq_mask;
#endif
@ -143,9 +161,26 @@ mv_timer_attach(device_t dev)
sc->timer_bst = rman_get_bustag(sc->timer_res[0]);
sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);
sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") ||
ofw_bus_is_compatible(dev, "marvell,armada-380-wdt");
mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);
mv_watchdog_disable();
EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
if (sc->has_wdt) {
mv_watchdog_disable();
EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
}
if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data
== MV_WDT) {
/* Don't set timers for wdt-only entry. */
device_printf(dev, "only watchdog attached\n");
return (0);
} else if (sc->timer_res[1] == NULL) {
device_printf(dev, "no interrupt resource\n");
bus_release_resources(dev, mv_timer_spec, sc->timer_res);
return (ENXIO);
}
if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,
mv_hardclock, NULL, sc, &ihl) != 0) {
@ -155,7 +190,7 @@ mv_timer_attach(device_t dev)
}
mv_setup_timers();
#if !defined(SOC_MV_ARMADAXP)
#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER0_CLR;
@ -294,7 +329,7 @@ static void
mv_watchdog_enable(void)
{
uint32_t val, irq_cause;
#if !defined(SOC_MV_ARMADAXP)
#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask;
#endif
@ -302,10 +337,14 @@ mv_watchdog_enable(void)
irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val &= ~RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, val);
#else
irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
irq_mask |= IRQ_TIMER_WD_MASK;
@ -317,9 +356,12 @@ mv_watchdog_enable(void)
#endif
val = mv_get_timer_control();
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
#if defined(SOC_MV_ARMADAXP)
val |= CPU_TIMER_WD_25MHZ_EN;
#if defined(SOC_MV_ARMADA38X)
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
#elif defined(SOC_MV_ARMADAXP)
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
#else
val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
#endif
mv_set_timer_control(val);
}
@ -328,18 +370,26 @@ static void
mv_watchdog_disable(void)
{
uint32_t val, irq_cause;
#if !defined(SOC_MV_ARMADAXP)
#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask;
#endif
val = mv_get_timer_control();
#if defined(SOC_MV_ARMADA38X)
val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
#else
val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
#endif
mv_set_timer_control(val);
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
val = read_cpu_misc(RSTOUTn_MASK);
val |= RSTOUTn_MASK_WD;
write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD);
#else
val = read_cpu_ctrl(RSTOUTn_MASK);
val &= ~WD_RST_OUT_EN;
@ -378,8 +428,7 @@ mv_watchdog_event(void *arg, unsigned int cmd, int *error)
if (ticks > MAX_WATCHDOG_TICKS)
mv_watchdog_disable();
else {
/* Timer 2 is the watchdog */
mv_set_timer(2, ticks);
mv_set_timer(WATCHDOG_TIMER, ticks);
mv_watchdog_enable();
*error = 0;
}
@ -438,7 +487,7 @@ mv_setup_timers(void)
val = mv_get_timer_control();
val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
#if defined(SOC_MV_ARMADAXP)
#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
/* Enable 25MHz mode */
val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
#endif

8
sys/arm/mv/twsi.c
View File

@ -141,6 +141,12 @@ static struct resource_spec res_spec[] = {
{ -1, 0 }
};
static struct ofw_compat_data compat_data[] = {
{ "mrvl,twsi", true },
{ "marvell,mv64xxx-i2c", true },
{ NULL, false }
};
static device_method_t mv_twsi_methods[] = {
/* device interface */
DEVMETHOD(device_probe, mv_twsi_probe),
@ -308,7 +314,7 @@ mv_twsi_probe(device_t dev)
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (!ofw_bus_is_compatible(dev, "mrvl,twsi"))
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
return (ENXIO);
device_set_desc(dev, "Marvell Integrated I2C Bus Controller");

1
sys/arm64/conf/GENERIC
View File

@ -66,7 +66,6 @@ options MAC # TrustedBSD MAC Framework
options KDTRACE_FRAME # Ensure frames are compiled in
options KDTRACE_HOOKS # Kernel DTrace hooks
options VFP # Floating-point support
options VFS_AIO # Real implementations of the aio_* system calls
options RACCT # Resource accounting framework
options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default
options RCTL # Resource limits

154
sys/boot/fdt/dts/arm/armada-380.dtsi Normal file
View File

@ -0,0 +1,154 @@
/*
* Device Tree Include file for Marvell Armada 380 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* $FreeBSD$
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 380 family SoC";
compatible = "marvell,armada380";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-380-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
};
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6810-pinctrl";
};
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
/* x1 port */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
};
/* x1 port */
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
/* x1 port */
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
};
};
};
};

81
sys/boot/fdt/dts/arm/armada-385.dtsi Normal file
View File

@ -0,0 +1,81 @@
/*
* Device Tree Include file for Marvell Armada 385 SoC.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* $FreeBSD$
*/
#include "armada-38x.dtsi"
/ {
model = "Marvell Armada 385 family SoC";
compatible = "marvell,armada385", "marvell,armada380";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,armada-380-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6820-pinctrl";
};
};
};
};

393
sys/boot/fdt/dts/arm/armada-388-gp.dts Normal file
View File

@ -0,0 +1,393 @@
/*
* Device Tree file for Marvell Armada 385 development board
* (RD-88F6820-GP)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* $FreeBSD$
*/
/dts-v1/;
#include "armada-388.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 GP";
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
};
soc {
ranges = <0 0 0xf1000000 0x100000>;
internal-regs {
spi@10600 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
/*
* The EEPROM located at adresse 54 is needed
* for the boot - DO NOT ERASE IT -
*/
expander0: pca9555@20 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
pinctrl-0 = <&pca0_pins>;
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20>;
};
expander1: pca9555@21 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
interrupt-parent = <&gpio0>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x21>;
};
};
serial@12000 {
/*
* Exported on the micro USB connector CON16
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
/* GE1 CON15 */
ethernet@30000 {
pinctrl-names = "default";
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON4 */
usb@58000 {
vcc-supply = <&reg_usb2_0_vbus>;
status = "okay";
};
/* GE0 CON1 */
ethernet@70000 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
mdio@72004 {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
sata@a8000 {
pinctrl-names = "default";
pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
target-supply = <&reg_5v_sata0>;
};
sata1: sata-port@1 {
reg = <1>;
target-supply = <&reg_5v_sata1>;
};
};
sata@e0000 {
pinctrl-names = "default";
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
sata2: sata-port@0 {
reg = <0>;
target-supply = <&reg_5v_sata2>;
};
sata3: sata-port@1 {
reg = <1>;
target-supply = <&reg_5v_sata3>;
};
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
no-1-8-v;
wp-inverted;
bus-width = <8>;
status = "okay";
};
/* CON5 */
usb3@f0000 {
vcc-supply = <&reg_usb2_1_vbus>;
status = "okay";
};
/* CON7 */
usb3@f8000 {
vcc-supply = <&reg_usb3_vbus>;
status = "okay";
};
};
gpio-fan {
compatible = "gpio-fan";
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = < 0 0
3000 1>;
};
};
pci0: pcie@f1080000 {
status = "okay";
};
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
};
reg_usb2_0_vbus: v5-vbus0 {
compatible = "regulator-fixed";
regulator-name = "v5.0-vbus0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
};
reg_usb2_1_vbus: v5-vbus1 {
compatible = "regulator-fixed";
regulator-name = "v5.0-vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
reg_usb2_1_vbus: v5-vbus1 {
compatible = "regulator-fixed";
regulator-name = "v5.0-vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
reg_sata0: pwr-sata0 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0";
enable-active-high;
regulator-always-on;
};
reg_5v_sata0: v5-sata0 {
compatible = "regulator-fixed";
regulator-name = "v5.0-sata0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata0>;
};
reg_12v_sata0: v12-sata0 {
compatible = "regulator-fixed";
regulator-name = "v12.0-sata0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
vin-supply = <&reg_sata0>;
};
reg_sata1: pwr-sata1 {
regulator-name = "pwr_en_sata1";
compatible = "regulator-fixed";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata1: v5-sata1 {
compatible = "regulator-fixed";
regulator-name = "v5.0-sata1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata1>;
};
reg_12v_sata1: v12-sata1 {
compatible = "regulator-fixed";
regulator-name = "v12.0-sata1";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
vin-supply = <&reg_sata1>;
};
reg_sata2: pwr-sata2 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata2";
enable-active-high;
regulator-always-on;
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata2: v5-sata2 {
compatible = "regulator-fixed";
regulator-name = "v5.0-sata2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata2>;
};
reg_12v_sata2: v12-sata2 {
compatible = "regulator-fixed";
regulator-name = "v12.0-sata2";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
vin-supply = <&reg_sata2>;
};
reg_sata3: pwr-sata3 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata3";
enable-active-high;
regulator-always-on;
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata3: v5-sata3 {
compatible = "regulator-fixed";
regulator-name = "v5.0-sata3";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata3>;
};
reg_12v_sata3: v12-sata3 {
compatible = "regulator-fixed";
regulator-name = "v12.0-sata3";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
vin-supply = <&reg_sata3>;
};
};
&pinctrl {
pca0_pins: pca0_pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
};

72
sys/boot/fdt/dts/arm/armada-388.dtsi Normal file
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@ -0,0 +1,72 @@
/*
* Device Tree Include file for Marvell Armada 388 SoC.
*
* Copyright (C) 2015 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
* The main difference with the Armada 385 is that the 388 can handle two more
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
* property and the name of the SoC, and add the second SATA host which control
* the 2 other ports.
*
* $FreeBSD$
*/
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6828-pinctrl";
};
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>;
status = "disabled";
};
};
};
};

630
sys/boot/fdt/dts/arm/armada-38x.dtsi Normal file
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@ -0,0 +1,630 @@
/*
* Device Tree Include file for Marvell Armada 38x family of SoCs.
*
* Copyright (C) 2014 Marvell
*
* Lior Amsalem <alior@marvell.com>
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* $FreeBSD$
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 38x family SoC";
compatible = "marvell,armada380";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
serial0 = &uart0;
serial1 = &uart1;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
compatible = "marvell,armada380-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
interrupt-parent = <&gic>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
};
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
L2: cache-controller@8000 {
compatible = "arm,pl310-cache";
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
};
scu@c000 {
compatible = "arm,cortex-a9-scu";
reg = <0xc000 0x58>;
};
timer@c200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0xc200 0x20>;
interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clock-frequency = <800000000>;
clocks = <&coreclk 2>;
};
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x20>;
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
clock-frequency = <800000000>;
clocks = <&coreclk 2>;
};
gic: interrupt-controller@d000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
interrupt-controller;
reg = <0xd000 0x1000>,
<0xc100 0x100>;
};
spi0: spi@10600 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart0: serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
pinctrl: pinctrl@18000 {
reg = <0x18000 0x20>;
ge0_rgmii_pins: ge-rgmii-pins-0 {
marvell,pins = "mpp6", "mpp7", "mpp8",
"mpp9", "mpp10", "mpp11",
"mpp12", "mpp13", "mpp14",
"mpp15", "mpp16", "mpp17";
marvell,function = "ge0";
};
ge1_rgmii_pins: ge-rgmii-pins-1 {
marvell,pins = "mpp21", "mpp27", "mpp28",
"mpp29", "mpp30", "mpp31",
"mpp32", "mpp37", "mpp38",
"mpp39", "mpp40", "mpp41";
marvell,function = "ge1";
};
i2c0_pins: i2c-pins-0 {
marvell,pins = "mpp2", "mpp3";
marvell,function = "i2c0";
};
mdio_pins: mdio-pins {
marvell,pins = "mpp4", "mpp5";
marvell,function = "ge";
};
ref_clk0_pins: ref-clk-pins-0 {
marvell,pins = "mpp45";
marvell,function = "ref";
};
ref_clk1_pins: ref-clk-pins-1 {
marvell,pins = "mpp46";
marvell,function = "ref";
};
spi0_pins: spi-pins-0 {
marvell,pins = "mpp22", "mpp23", "mpp24",
"mpp25";
marvell,function = "spi0";
};
spi1_pins: spi-pins-1 {
marvell,pins = "mpp56", "mpp57", "mpp58",
"mpp59";
marvell,function = "spi1";
};
uart0_pins: uart-pins-0 {
marvell,pins = "mpp0", "mpp1";
marvell,function = "ua0";
};
uart1_pins: uart-pins-1 {
marvell,pins = "mpp19", "mpp20";
marvell,function = "ua1";
};
sdhci_pins: sdhci-pins {
marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp52", "mpp53", "mpp54",
"mpp55", "mpp57", "mpp58",
"mpp59";
marvell,function = "sd0";
};
sata0_pins: sata-pins-0 {
marvell,pins = "mpp20";
marvell,function = "sata0";
};
sata1_pins: sata-pins-1 {
marvell,pins = "mpp19";
marvell,function = "sata1";
};
sata2_pins: sata-pins-2 {
marvell,pins = "mpp47";
marvell,function = "sata2";
};
sata3_pins: sata-pins-3 {
marvell,pins = "mpp44";
marvell,function = "sata3";
};
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <28>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
system-controller@18200 {
compatible = "marvell,armada-380-system-controller",
"marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-380-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
coreclk: mvebu-sar@18600 {
compatible = "marvell,armada-380-core-clock";
reg = <0x18600 0x04>;
#clock-cells = <1>;
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
msi-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
timer@20300 {
compatible = "marvell,armada-380-timer",
"marvell,armada-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<&mpic 5>,
<&mpic 6>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
compatible = "marvell,armada-380-wdt";
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
};
mpcore-soc-ctrl@20d20 {
compatible = "marvell,armada-380-mpcore-soc-ctrl";
reg = <0x20d20 0x6c>;
};
coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;
};
pmsu@22000 {
compatible = "marvell,armada-380-pmsu";
reg = <0x22000 0x1000>;
};
eth1: ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0x30000 0x4000>;
interrupts-extended = <&mpic 10>;
clocks = <&gateclk 3>;
status = "disabled";
};
eth2: ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0x34000 0x4000>;
interrupts-extended = <&mpic 12>;
clocks = <&gateclk 2>;
status = "disabled";
};
usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 18>;
status = "disabled";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor10 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
status = "disabled";
};
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
clocks = <&gateclk 4>;
};
rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 15>;
status = "disabled";
};
sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>;
status = "disabled";
};
coredivclk: clock@e4250 {
compatible = "marvell,armada-380-corediv-clock";
reg = <0xe4250 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>;
status = "okay";
};
flash@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&coredivclk 0>;
status = "disabled";
};
sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
<0xdc000 0x100>,
<0x18454 0x4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 17>;
mrvl,clk-delay-cycles = <0x1F>;
status = "disabled";
};
usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 9>;
status = "disabled";
};
usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 10>;
status = "disabled";
};
};
};
pci0: pcie@f1080000 {
compatible = "mrvl,pcie";
status = "disabled";
device_type = "pci";
#interrupt-cells = <3>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xf1080000 0x2000>;
bus-range = <0 255>;
ranges = <0x42000000 0x0 0xf1200000 0xf1200000 0x0 0x00100000
0x41000000 0x0 0x00000000 0xf1300000 0x0 0x00100000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 91 0>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x0000 0x0 0x0 0x1 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
>;
};
clocks {
/* 2 GHz fixed main PLL */
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
};
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};

12
sys/boot/fdt/dts/arm/db78460.dts
View File

@ -111,45 +111,41 @@
};
serial0: serial@12000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x20>;
reg-shift = <2>;
current-speed = <115200>;
clock-frequency = <0>;
busy-detect = <1>;
interrupts = <41>;
interrupt-parent = <&MPIC>;
};
serial1: serial@12100 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x20>;
reg-shift = <2>;
current-speed = <115200>;
clock-frequency = <0>;
busy-detect = <1>;
interrupts = <42>;
interrupt-parent = <&MPIC>;
};
serial2: serial@12200 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x12200 0x20>;
reg-shift = <2>;
current-speed = <115200>;
clock-frequency = <0>;
busy-detect = <1>;
interrupts = <43>;
interrupt-parent = <&MPIC>;
};
serial3: serial@12300 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x12300 0x20>;
reg-shift = <2>;
current-speed = <115200>;
clock-frequency = <0>;
busy-detect = <1>;
interrupts = <44>;
interrupt-parent = <&MPIC>;
};

12
sys/boot/fdt/dts/arm/rk3188.dtsi
View File

@ -179,53 +179,49 @@
};
uart0: serial@10124000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>;
reg-shift = <2>;
interrupts = <66>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
status = "disabled";
};
uart1: serial@10126000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x10126000 0x400>;
reg-shift = <2>;
interrupts = <67>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
status = "disabled";
};
uart2: serial@20064000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
reg-shift = <2>;
interrupts = <68>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
status = "disabled";
};
uart3: serial@20068000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x20068000 0x400>;
reg-shift = <2>;
interrupts = <69>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
status = "disabled";
};

3
sys/boot/fdt/dts/arm/sun4i-a10.dtsi
View File

@ -120,14 +120,13 @@
};
UART0: serial@01c28000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
reg-shift = <2>;
interrupts = <1>;
interrupt-parent = <&AINTC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
};
emac@01c0b000 {

3
sys/boot/fdt/dts/arm/sun7i-a20.dtsi
View File

@ -126,14 +126,13 @@
};
UART0: serial@01c28000 {
compatible = "ns16550";
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
reg-shift = <2>;
interrupts = <1>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
};
emac@01c0b000 {

1
sys/conf/options.arm
View File

@ -47,6 +47,7 @@ SOC_IMX51 opt_global.h
SOC_IMX53 opt_global.h
SOC_IMX6 opt_global.h
SOC_MV_ARMADAXP opt_global.h
SOC_MV_ARMADA38X opt_global.h
SOC_MV_DISCOVERY opt_global.h
SOC_MV_DOVE opt_global.h
SOC_MV_FREY opt_global.h

4
sys/dev/fdt/fdt_common.c
View File

@ -212,7 +212,7 @@ fdt_immr_addr(vm_offset_t immr_va)
* Try to access the SOC node directly i.e. through /aliases/.
*/
if ((node = OF_finddevice("soc")) != 0)
if (fdt_is_compatible_strict(node, "simple-bus"))
if (fdt_is_compatible(node, "simple-bus"))
goto moveon;
/*
* Find the node the long way.
@ -220,7 +220,7 @@ fdt_immr_addr(vm_offset_t immr_va)
if ((node = OF_finddevice("/")) == 0)
return (ENXIO);
if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0)
if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
return (ENXIO);
moveon:

14
sys/dev/ofw/ofw_bus_subr.c
View File

@ -716,9 +716,10 @@ ofw_bus_find_string_index(phandle_t node, const char *list_name,
*/
int
ofw_bus_string_list_to_array(phandle_t node, const char *list_name,
const char ***array)
const char ***out_array)
{
char *elems, *tptr;
const char **array;
int i, cnt, nelems, len;
elems = NULL;
@ -731,11 +732,11 @@ ofw_bus_string_list_to_array(phandle_t node, const char *list_name,
i += strlen(elems + i) + 1;
/* Allocate space for arrays and all strings. */
*array = malloc((cnt + 1) * sizeof(char *) + nelems, M_OFWPROP,
array = malloc((cnt + 1) * sizeof(char *) + nelems, M_OFWPROP,
M_WAITOK);
/* Get address of first string. */
tptr = (char *)(*array + cnt);
tptr = (char *)(array + cnt + 1);
/* Copy strings. */
memcpy(tptr, elems, nelems);
@ -743,12 +744,13 @@ ofw_bus_string_list_to_array(phandle_t node, const char *list_name,
/* Fill string pointers. */
for (i = 0, cnt = 0; i < nelems; cnt++) {
len = strlen(tptr + i) + 1;
*array[cnt] = tptr;
len = strlen(tptr) + 1;
array[cnt] = tptr;
i += len;
tptr += len;
}
*array[cnt] = 0;
array[cnt] = 0;
*out_array = array;
return (cnt);
}

3
sys/dev/pci/pcireg.h
View File

@ -690,6 +690,9 @@
#define PCIR_VENDOR_LENGTH 0x2
#define PCIR_VENDOR_DATA 0x3
/* PCI Device capability definitions */
#define PCIR_DEVICE_LENGTH 0x2
/* PCI EHCI Debug Port definitions */
#define PCIR_DEBUG_PORT 0x2
#define PCIM_DEBUG_PORT_OFFSET 0x1FFF

8
sys/dev/uart/uart_dev_ns8250.c
View File

@ -397,6 +397,7 @@ struct uart_class uart_ns8250_class = {
#ifdef FDT
static struct ofw_compat_data compat_data[] = {
{"ns16550", (uintptr_t)&uart_ns8250_class},
{"snps,dw-apb-uart", (uintptr_t)&uart_ns8250_class},
{NULL, (uintptr_t)NULL},
};
UART_FDT_CLASS_AND_DEVICE(compat_data);
@ -456,9 +457,12 @@ ns8250_bus_attach(struct uart_softc *sc)
* Check whether uart requires to read USR reg when IIR_BUSY and
* has broken txfifo.
*/
ns8250->busy_detect = ofw_bus_is_compatible(sc->sc_dev, "snps,dw-apb-uart");
node = ofw_bus_get_node(sc->sc_dev);
if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
ns8250->busy_detect = cell ? 1 : 0;
/* XXX: This is kept for a short time for compatibility with older device trees */
if ((OF_getencprop(node, "busy-detect", &cell, sizeof(cell))) > 0
&& cell != 0)
ns8250->busy_detect = 1;
if ((OF_getencprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
broken_txfifo = cell ? 1 : 0;
#endif

38
sys/dev/usb/controller/ehci_mv.c
View File

@ -99,6 +99,12 @@ static void *ih_err;
#define MV_USB_HOST_OVERFLOW (1 << 2)
#define MV_USB_DEVICE_UNDERFLOW (1 << 3)
static struct ofw_compat_data compat_data[] = {
{"mrvl,usb-ehci", true},
{"marvell,orion-ehci", true},
{NULL, false}
};
static int
mv_ehci_probe(device_t self)
{
@ -106,7 +112,7 @@ mv_ehci_probe(device_t self)
if (!ofw_bus_status_okay(self))
return (ENXIO);
if (!ofw_bus_is_compatible(self, "mrvl,usb-ehci"))
if (!ofw_bus_search_compatible(self, compat_data)->ocd_data)
return (ENXIO);
device_set_desc(self, EHCI_HC_DEVSTR);
@ -156,12 +162,15 @@ mv_ehci_attach(device_t self)
device_get_name(self));
rid = 0;
irq_err = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (irq_err == NULL) {
device_printf(self, "Could not allocate error irq\n");
mv_ehci_detach(self);
return (ENXIO);
if (!ofw_bus_is_compatible(self, "marvell,orion-ehci")) {
irq_err = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (irq_err == NULL) {
device_printf(self, "Could not allocate error irq\n");
mv_ehci_detach(self);
return (ENXIO);
}
rid = 1;
}
/*
@ -169,7 +178,6 @@ mv_ehci_attach(device_t self)
* sure to use the correct rid for the main one (controller interrupt)
* -- refer to DTS for the right resource number to use here.
*/
rid = 1;
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
@ -187,12 +195,14 @@ mv_ehci_attach(device_t self)
sprintf(sc->sc_vendor, "Marvell");
err = bus_setup_intr(self, irq_err, INTR_TYPE_BIO,
err_intr, NULL, sc, &ih_err);
if (err) {
device_printf(self, "Could not setup error irq, %d\n", err);
ih_err = NULL;
goto error;
if (!ofw_bus_is_compatible(self, "marvell,orion-ehci")) {
err = bus_setup_intr(self, irq_err, INTR_TYPE_BIO,
err_intr, NULL, sc, &ih_err);
if (err) {
device_printf(self, "Could not setup error irq, %d\n", err);
ih_err = NULL;
goto error;
}
}
EWRITE4(sc, USB_BRIDGE_INTR_MASK, MV_USB_ADDR_DECODE_ERR |

1648
sys/dev/xen/netfront/netfront.c
View File

File diff suppressed because it is too large Load Diff

2
sys/modules/ix/Makefile
View File

@ -3,7 +3,7 @@
.PATH: ${.CURDIR}/../../dev/ixgbe
KMOD = if_ix
SRCS = device_if.h bus_if.h pci_if.h
SRCS = device_if.h bus_if.h pci_if.h pci_iov_if.h
SRCS += opt_inet.h opt_inet6.h opt_rss.h
SRCS += if_ix.c ix_txrx.c ixgbe_osdep.c
# Shared source

2
sys/modules/ixlv/Makefile
View File

@ -3,7 +3,7 @@
.PATH: ${.CURDIR}/../../dev/ixl
KMOD = if_ixlv
SRCS = device_if.h bus_if.h pci_if.h opt_bdg.h
SRCS = device_if.h bus_if.h pci_if.h pci_iov_if.h opt_bdg.h
SRCS += opt_inet.h opt_inet6.h opt_rss.h
SRCS += if_ixlv.c ixlvc.c ixl_txrx.c i40e_osdep.c

2
sys/modules/ixv/Makefile
View File

@ -3,7 +3,7 @@
.PATH: ${.CURDIR}/../../dev/ixgbe
KMOD = if_ixv
SRCS = device_if.h bus_if.h pci_if.h
SRCS = device_if.h bus_if.h pci_if.h pci_iov_if.h
SRCS += opt_inet.h opt_inet6.h opt_rss.h
SRCS += if_ixv.c ix_txrx.c ixgbe_osdep.c
# Shared source

7
sys/netinet6/ip6_forward.c
View File

@ -341,6 +341,7 @@ again:
dst->sin6_addr = ip6->ip6_dst;
again2:
rin6.ro_rt = in6_rtalloc1((struct sockaddr *)dst, 0, 0, M_GETFIB(m));
rt = rin6.ro_rt;
if (rin6.ro_rt != NULL)
RT_UNLOCK(rin6.ro_rt);
else {
@ -352,7 +353,6 @@ again2:
}
goto bad;
}
rt = rin6.ro_rt;
/*
* Source scope check: if a packet can't be delivered to its
@ -505,8 +505,10 @@ again2:
/* If destination is now ourself drop to ip6_input(). */
if (in6_localip(&ip6->ip6_dst))
m->m_flags |= M_FASTFWD_OURS;
else
else {
RTFREE(rt);
goto again; /* Redo the routing table lookup. */
}
}
/* See if local, if yes, send it to netisr. */
@ -533,6 +535,7 @@ again2:
m->m_flags |= M_SKIP_FIREWALL;
m->m_flags &= ~M_IP6_NEXTHOP;
m_tag_delete(m, fwd_tag);
RTFREE(rt);
goto again2;
}

3
sys/sys/ttydevsw.h
View File

@ -188,7 +188,8 @@ static __inline bool
ttydevsw_busy(struct tty *tp)
{
MPASS(tty_gone(tp));
tty_lock_assert(tp, MA_OWNED);
MPASS(!tty_gone(tp));
return (tp->t_devsw->tsw_busy(tp));
}