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Merge commit 2e24219d3 from llvm git (by Hans Wennborg):

Browse Source 
[MC][ARM] Resolve some pcrel fixups at assembly time (PR44929)

  MC currently does not emit these relocation types, and lld does not
  handle them. Add FKF_Constant as a work-around of some ARM code after
  D72197. Eventually we probably should implement these relocation
  types.

  By Fangrui Song!

  Differential revision: https://reviews.llvm.org/D72892

This re-enables using the arm 'adr' pseudo instruction on global symbols
again.  It was broken as a side-effect of upstream commit 2bfee35cb,
which lead to "error: unsupported relocation on symbol" when assembling
such constructs, which are used in e.g. sys/arm/arm/locore-v[46].S.

PR:		244251
This commit is contained in:
Dimitry Andric 2020-02-27 18:49:49 +00:00
parent c0ac260c74
commit 21054a9b07
3 changed files with 20 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
contrib/llvm-project/llvm/include/llvm/MC/MCFixupKindInfo.h
View File

@ -22,7 +22,12 @@ struct MCFixupKindInfo {
FKF_IsAlignedDownTo32Bits = (1 << 1),
/// Should this fixup be evaluated in a target dependent manner?
FKF_IsTarget = (1 << 2)
FKF_IsTarget = (1 << 2),
/// This fixup kind should be resolved if defined.
/// FIXME This is a workaround because we don't support certain ARM
/// relocation types. This flag should eventually be removed.
FKF_Constant = 1 << 3,
};
/// A target specific name for the fixup kind. The names will be unique for

6
contrib/llvm-project/llvm/lib/MC/MCAssembler.cpp
View File

@ -224,6 +224,7 @@ bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout,
return getBackend().evaluateTargetFixup(*this, Layout, Fixup, DF, Target,
Value, WasForced);
unsigned FixupFlags = getBackendPtr()->getFixupKindInfo(Fixup.getKind()).Flags;
bool IsPCRel = getBackendPtr()->getFixupKindInfo(Fixup.getKind()).Flags &
MCFixupKindInfo::FKF_IsPCRel;
@ -239,8 +240,9 @@ bool MCAssembler::evaluateFixup(const MCAsmLayout &Layout,
if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined()) {
IsResolved = false;
} else if (auto *Writer = getWriterPtr()) {
IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
*this, SA, *DF, false, true);
IsResolved = (FixupFlags & MCFixupKindInfo::FKF_Constant) ||
Writer->isSymbolRefDifferenceFullyResolvedImpl(
*this, SA, *DF, false, true);
}
}
} else {

22
contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -55,31 +55,29 @@ Optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
}
const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
unsigned IsPCRelConstant =
MCFixupKindInfo::FKF_IsPCRel | MCFixupKindInfo::FKF_Constant;
const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
// This table *must* be in the order that the fixup_* kinds are defined in
// ARMFixupKinds.h.
//
// Name Offset (bits) Size (bits) Flags
{"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
{"fixup_t2_ldst_pcrel_12", 0, 32,
MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
{"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
{"fixup_t2_pcrel_10", 0, 32,
MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_t2_pcrel_9", 0, 32,
MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_thumb_adr_pcrel_10", 0, 8,
MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
{"fixup_t2_adr_pcrel_12", 0, 32,
MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
{"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},