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Reformat indentation to match other imx5/6 register definition headers, and

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tweak some comments.  No functional changes.
This commit is contained in:
Ian Lepore 2018-01-24 17:52:06 +00:00
parent e0a40f3045
commit 2128fefb75
1 changed files with 19 additions and 19 deletions
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38
sys/arm/freescale/imx/imx_wdogreg.h
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@ -34,31 +34,31 @@
#define WDOG_CLK_FREQ 32768
#define WDOG_CR_REG 0x00 /* Control Register */
#define WDOG_CR_WT_MASK 0xff00 /* Count of 0.5 sec */
#define WDOG_CR_WT_SHIFT 8
#define WDOG_CR_WDW (1 << 7) /* Suspend WDog */
#define WDOG_CR_WDA (1 << 5) /* Don't touch ipp_wdog */
#define WDOG_CR_SRS (1 << 4) /* Don't touch sys_reset */
#define WDOG_CR_WDT (1 << 3) /* Assert ipp_wdog on tout */
#define WDOG_CR_WDE (1 << 2) /* WDog Enable */
#define WDOG_CR_WDBG (1 << 1) /* Suspend when DBG mode */
#define WDOG_CR_WDZST (1 << 0) /* Suspend when LP mode */
#define WDOG_CR_WT_MASK 0xff00 /* Count; 0.5 sec units */
#define WDOG_CR_WT_SHIFT 8
#define WDOG_CR_WDW (1u << 7) /* Suspend when in WAIT mode */
#define WDOG_CR_WDA (1u << 5) /* Don't assert ext reset */
#define WDOG_CR_SRS (1u << 4) /* Don't assert soft reset */
#define WDOG_CR_WDT (1u << 3) /* Assert ext reset on timeout */
#define WDOG_CR_WDE (1u << 2) /* Watchdog Enable */
#define WDOG_CR_WDBG (1u << 1) /* Suspend when DBG mode */
#define WDOG_CR_WDZST (1u << 0) /* Suspend when LP mode */
#define WDOG_SR_REG 0x02 /* Service Register */
#define WDOG_SR_STEP1 0x5555
#define WDOG_SR_STEP2 0xaaaa
#define WDOG_SR_STEP1 0x5555
#define WDOG_SR_STEP2 0xaaaa
#define WDOG_RSR_REG 0x04 /* Reset Status Register */
#define WDOG_RSR_POR (1 << 4) /* Due to Power-On Reset */
#define WDOG_RSR_TOUT (1 << 1) /* Due WDog timeout reset */
#define WDOG_RSR_SFTW (1 << 0) /* Due Soft reset */
#define WDOG_RSR_POR (1u << 4) /* Due to Power-On Reset */
#define WDOG_RSR_TOUT (1u << 1) /* Due WDog timeout reset */
#define WDOG_RSR_SFTW (1u << 0) /* Due Soft reset */
#define WDOG_ICR_REG 0x06 /* Interrupt Control Register */
#define WDOG_ICR_WIE (1 << 15) /* Enable Interrupt */
#define WDOG_ICR_WTIS (1 << 14) /* Interrupt has occurred */
#define WDOG_ICR_WTCT_MASK 0x00ff
#define WDOG_ICR_WTCT_SHIFT 0 /* Interrupt hold time */
#define WDOG_ICR_WIE (1u << 15) /* Enable Interrupt */
#define WDOG_ICR_WTIS (1u << 14) /* Interrupt has occurred */
#define WDOG_ICR_WTCT_MASK 0x00ff /* Interrupt lead time in 0.5s */
#define WDOG_ICR_WTCT_SHIFT 0 /* units before reset occurs */
#define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */
#define WDOG_MCR_PDE (1 << 0)
#define WDOG_MCR_PDE (1u << 0) /* Power-down enable */