Fix tx pause quanta and timer calculations.
MFC after: 3 days
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3dd6d7570f
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21d68a68bf
@ -462,7 +462,7 @@ static int rx_fifo_hwm(int mtu)
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*/
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int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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{
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int hwm, lwm, divisor;
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int hwm, lwm;
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int ipg;
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unsigned int thres, v, reg;
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adapter_t *adap = mac->adapter;
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@ -541,16 +541,6 @@ int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu)
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t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
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V_TXFIFOTHRESH(M_TXFIFOTHRESH) | V_TXIPG(M_TXIPG),
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V_TXFIFOTHRESH(thres) | V_TXIPG(ipg));
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/* Assuming a minimum drain rate of 2.5Gbps...
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*/
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if (adap->params.rev > 0) {
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divisor = (adap->params.rev == T3_REV_C) ? 64 : 8;
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t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
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(hwm - lwm) * 4 / divisor);
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}
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t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
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MAC_RXFIFO_SIZE * 4 * 8 / 512);
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return 0;
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}
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@ -570,9 +560,17 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
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u32 val;
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adapter_t *adap = mac->adapter;
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unsigned int oft = mac->offset;
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unsigned int pause_bits;
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if (duplex >= 0 && duplex != DUPLEX_FULL)
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return -EINVAL;
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pause_bits = MAC_RXFIFO_SIZE * 4 * 8;
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t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
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pause_bits / 512);
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t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
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(pause_bits >> (adap->params.rev == T3_REV_C ? 10 : 7)));
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if (mac->multiport) {
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u32 rx_max_pkt_size =
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G_RXMAXPKTSIZE(t3_read_reg(adap,
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@ -581,9 +579,9 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
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val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
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val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(rx_max_pkt_size) / 8);
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t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
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t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
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F_TXPAUSEEN);
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return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
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}
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if (speed >= 0) {
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