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Increase the PIO timeout to approximately the value it used to have

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before rev 1.229 (~ 100 ms).  According to bde, some (old) broken
hardware could require it.  In order to make timing more accurate than
what could be achieved with a loop around DELAY(1), increase loop
timing after the initial ~ 1 ms.

Also, move the declaration of FDSTS_TIMEOUT out from fdreg.h into fd.c
where it actually belongs to.

MFC after:	2 days
This commit is contained in:
joerg 2002-05-12 15:24:21 +00:00
parent c57dc2b4a8
commit 21ef250e0a
4 changed files with 76 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
sys/dev/fdc/fdc.c
View File

@ -212,6 +212,17 @@ FDC_ACCESSOR(fdunit, FDUNIT, int)
*/
#define FDC_DMAOV_MAX 25
/*
* Timeout value for the PIO loops to wait until the FDC main status
* register matches our expectations (request for master, direction
* bit). This is supposed to be a number of microseconds, although
* timing might actually not be very accurate.
*
* Timeouts of 100 msec are believed to be required for some broken
* (old) hardware.
*/
#define FDSTS_TIMEOUT 100000
/*
* Number of subdevices that can be used for different density types.
* By now, the lower 6 bit of the minor number are reserved for this,
@ -1480,7 +1491,15 @@ fd_in(struct fdc_data *fdc, int *ptr)
!= (NE7_DIO|NE7_RQM) && j-- > 0) {
if (i == NE7_RQM)
return fdc_err(fdc, "ready for output in input\n");
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - j > 1000) {
DELAY(1000);
j -= 999;
} else
DELAY(1);
}
if (j <= 0)
return fdc_err(fdc, bootverbose? "input ready timeout\n": 0);
@ -1505,13 +1524,29 @@ out_fdc(struct fdc_data *fdc, int x)
/* Check that the direction bit is set */
i = FDSTS_TIMEOUT;
while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0)
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - i > 1000) {
DELAY(1000);
i -= 999;
} else
DELAY(1);
if (i <= 0) return fdc_err(fdc, "direction bit not set\n");
/* Check that the floppy controller is ready for a command */
i = FDSTS_TIMEOUT;
while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0)
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - i > 1000) {
DELAY(1000);
i -= 999;
} else
DELAY(1);
if (i <= 0)
return fdc_err(fdc, bootverbose? "output ready timeout\n": 0);

12
sys/dev/fdc/fdcreg.h
View File

@ -69,15 +69,3 @@
#define FDI_DCHG 0x80 /* diskette has been changed */
/* requires drive and motor being selected */
/* is cleared by any step pulse to drive */
/*
* Timeout value for the PIO loops to wait until the FDC main status
* register matches our expextations (request for master, direction
* bit). This is the number of cycles to loop while waiting, with a
* 1-microsecond (in theory) DELAY() in each cycle. In particular on
* slower hardware, it could take a fair amount more to execute. Of
* course, as soon as the FDC main status register indicates the correct
* bits are set, the loop will terminate, so this is merely a safety
* measure to avoid looping forever in case of broken hardware.
*/
#define FDSTS_TIMEOUT 200

41
sys/isa/fd.c
View File

@ -212,6 +212,17 @@ FDC_ACCESSOR(fdunit, FDUNIT, int)
*/
#define FDC_DMAOV_MAX 25
/*
* Timeout value for the PIO loops to wait until the FDC main status
* register matches our expectations (request for master, direction
* bit). This is supposed to be a number of microseconds, although
* timing might actually not be very accurate.
*
* Timeouts of 100 msec are believed to be required for some broken
* (old) hardware.
*/
#define FDSTS_TIMEOUT 100000
/*
* Number of subdevices that can be used for different density types.
* By now, the lower 6 bit of the minor number are reserved for this,
@ -1480,7 +1491,15 @@ fd_in(struct fdc_data *fdc, int *ptr)
!= (NE7_DIO|NE7_RQM) && j-- > 0) {
if (i == NE7_RQM)
return fdc_err(fdc, "ready for output in input\n");
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - j > 1000) {
DELAY(1000);
j -= 999;
} else
DELAY(1);
}
if (j <= 0)
return fdc_err(fdc, bootverbose? "input ready timeout\n": 0);
@ -1505,13 +1524,29 @@ out_fdc(struct fdc_data *fdc, int x)
/* Check that the direction bit is set */
i = FDSTS_TIMEOUT;
while ((fdsts_rd(fdc) & NE7_DIO) && i-- > 0)
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - i > 1000) {
DELAY(1000);
i -= 999;
} else
DELAY(1);
if (i <= 0) return fdc_err(fdc, "direction bit not set\n");
/* Check that the floppy controller is ready for a command */
i = FDSTS_TIMEOUT;
while ((fdsts_rd(fdc) & NE7_RQM) == 0 && i-- > 0)
DELAY(1);
/*
* After (maybe) 1 msec of waiting, back off to larger
* stepping to get the timing more accurate.
*/
if (FDSTS_TIMEOUT - i > 1000) {
DELAY(1000);
i -= 999;
} else
DELAY(1);
if (i <= 0)
return fdc_err(fdc, bootverbose? "output ready timeout\n": 0);

12
sys/isa/fdreg.h
View File

@ -69,15 +69,3 @@
#define FDI_DCHG 0x80 /* diskette has been changed */
/* requires drive and motor being selected */
/* is cleared by any step pulse to drive */
/*
* Timeout value for the PIO loops to wait until the FDC main status
* register matches our expextations (request for master, direction
* bit). This is the number of cycles to loop while waiting, with a
* 1-microsecond (in theory) DELAY() in each cycle. In particular on
* slower hardware, it could take a fair amount more to execute. Of
* course, as soon as the FDC main status register indicates the correct
* bits are set, the loop will terminate, so this is merely a safety
* measure to avoid looping forever in case of broken hardware.
*/
#define FDSTS_TIMEOUT 200