Add driver for the Xilinx AXI Direct Memory Access (AXI DMA) controller
found in the U.S. Government Furnished Equipment (GFE) 64-bit RISC-V cores. Sponsored by: DARPA, AFRL
This commit is contained in:
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parent
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648
sys/dev/xilinx/axidma.c
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648
sys/dev/xilinx/axidma.c
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory (Department of Computer Science and
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* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
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* DARPA SSITH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Xilinx AXI DMA controller driver. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_page.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/xdma/xdma.h>
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#include <dev/xilinx/axidma.h>
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#include "xdma_if.h"
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#define AXIDMA_DEBUG
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#undef AXIDMA_DEBUG
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#ifdef AXIDMA_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define AXIDMA_NCHANNELS 2
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#define AXIDMA_DESCS_NUM 512
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#define AXIDMA_TX_CHAN 0
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#define AXIDMA_RX_CHAN 1
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extern struct bus_space memmap_bus;
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struct axidma_fdt_data {
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int id;
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};
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struct axidma_channel {
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struct axidma_softc *sc;
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xdma_channel_t *xchan;
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bool used;
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int idx_head;
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int idx_tail;
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struct axidma_desc **descs;
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vm_paddr_t *descs_phys;
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uint32_t descs_num;
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vm_size_t mem_size;
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vm_offset_t mem_paddr;
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vm_offset_t mem_vaddr;
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uint32_t descs_used_count;
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};
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struct axidma_softc {
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device_t dev;
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struct resource *res[3];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih[2];
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struct axidma_desc desc;
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struct axidma_channel channels[AXIDMA_NCHANNELS];
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};
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static struct resource_spec axidma_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 1, RF_ACTIVE },
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{ -1, 0 }
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};
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#define HWTYPE_NONE 0
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#define HWTYPE_STD 1
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static struct ofw_compat_data compat_data[] = {
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{ "xlnx,eth-dma", HWTYPE_STD },
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{ NULL, HWTYPE_NONE },
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};
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static int axidma_probe(device_t dev);
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static int axidma_attach(device_t dev);
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static int axidma_detach(device_t dev);
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static inline uint32_t
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axidma_next_desc(struct axidma_channel *chan, uint32_t curidx)
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{
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return ((curidx + 1) % chan->descs_num);
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}
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static void
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axidma_intr(struct axidma_softc *sc,
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struct axidma_channel *chan)
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{
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xdma_transfer_status_t status;
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xdma_transfer_status_t st;
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struct axidma_fdt_data *data;
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xdma_controller_t *xdma;
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struct axidma_desc *desc;
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struct xdma_channel *xchan;
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uint32_t tot_copied;
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int pending;
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int errors;
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xchan = chan->xchan;
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xdma = xchan->xdma;
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data = xdma->data;
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pending = READ4(sc, AXI_DMASR(data->id));
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WRITE4(sc, AXI_DMASR(data->id), pending);
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errors = (pending & (DMASR_DMAINTERR | DMASR_DMASLVERR
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| DMASR_DMADECOREERR | DMASR_SGINTERR
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| DMASR_SGSLVERR | DMASR_SGDECERR));
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dprintf("%s: AXI_DMASR %x\n", __func__,
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READ4(sc, AXI_DMASR(data->id)));
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dprintf("%s: AXI_CURDESC %x\n", __func__,
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READ4(sc, AXI_CURDESC(data->id)));
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dprintf("%s: AXI_TAILDESC %x\n", __func__,
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READ4(sc, AXI_TAILDESC(data->id)));
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tot_copied = 0;
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while (chan->idx_tail != chan->idx_head) {
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desc = chan->descs[chan->idx_tail];
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if ((desc->status & BD_STATUS_CMPLT) == 0)
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break;
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st.error = errors;
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st.transferred = desc->status & BD_CONTROL_LEN_M;
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tot_copied += st.transferred;
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xchan_seg_done(xchan, &st);
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chan->idx_tail = axidma_next_desc(chan, chan->idx_tail);
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atomic_subtract_int(&chan->descs_used_count, 1);
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}
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/* Finish operation */
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status.error = errors;
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status.transferred = tot_copied;
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xdma_callback(chan->xchan, &status);
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}
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static void
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axidma_intr_rx(void *arg)
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{
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struct axidma_softc *sc;
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struct axidma_channel *chan;
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dprintf("%s\n", __func__);
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sc = arg;
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chan = &sc->channels[AXIDMA_RX_CHAN];
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axidma_intr(sc, chan);
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}
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static void
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axidma_intr_tx(void *arg)
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{
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struct axidma_softc *sc;
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struct axidma_channel *chan;
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dprintf("%s\n", __func__);
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sc = arg;
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chan = &sc->channels[AXIDMA_TX_CHAN];
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axidma_intr(sc, chan);
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}
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static int
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axidma_reset(struct axidma_softc *sc, int chan_id)
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{
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int timeout;
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WRITE4(sc, AXI_DMACR(chan_id), DMACR_RESET);
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timeout = 100;
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do {
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if ((READ4(sc, AXI_DMACR(chan_id)) & DMACR_RESET) == 0)
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break;
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} while (timeout--);
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dprintf("timeout %d\n", timeout);
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if (timeout == 0)
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return (-1);
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dprintf("%s: read control after reset: %x\n",
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__func__, READ4(sc, AXI_DMACR(chan_id)));
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return (0);
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}
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static int
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axidma_probe(device_t dev)
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{
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int hwtype;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (hwtype == HWTYPE_NONE)
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return (ENXIO);
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device_set_desc(dev, "Xilinx AXI DMA");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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axidma_attach(device_t dev)
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{
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struct axidma_softc *sc;
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phandle_t xref, node;
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int err;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, axidma_spec, sc->res)) {
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device_printf(dev, "could not allocate resources.\n");
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return (ENXIO);
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}
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/* CSR memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, axidma_intr_tx, sc, &sc->ih[0]);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, axidma_intr_rx, sc, &sc->ih[1]);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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node = ofw_bus_get_node(dev);
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xref = OF_xref_from_node(node);
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OF_device_register_xref(xref, dev);
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return (0);
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}
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static int
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axidma_detach(device_t dev)
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{
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struct axidma_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->res[1], sc->ih[0]);
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bus_teardown_intr(dev, sc->res[2], sc->ih[1]);
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bus_release_resources(dev, axidma_spec, sc->res);
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return (0);
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}
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static int
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axidma_desc_free(struct axidma_softc *sc, struct axidma_channel *chan)
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{
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struct xdma_channel *xchan;
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int nsegments;
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nsegments = chan->descs_num;
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xchan = chan->xchan;
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free(chan->descs, M_DEVBUF);
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free(chan->descs_phys, M_DEVBUF);
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pmap_kremove_device(chan->mem_vaddr, chan->mem_size);
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kva_free(chan->mem_vaddr, chan->mem_size);
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vmem_free(xchan->vmem, chan->mem_paddr, chan->mem_size);
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return (0);
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}
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static int
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axidma_desc_alloc(struct axidma_softc *sc, struct xdma_channel *xchan,
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uint32_t desc_size)
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{
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struct axidma_channel *chan;
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int nsegments;
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int i;
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chan = (struct axidma_channel *)xchan->chan;
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nsegments = chan->descs_num;
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chan->descs = malloc(nsegments * sizeof(struct axidma_desc *),
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M_DEVBUF, M_NOWAIT | M_ZERO);
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if (chan->descs == NULL) {
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device_printf(sc->dev,
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"%s: Can't allocate memory.\n", __func__);
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return (-1);
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}
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chan->descs_phys = malloc(nsegments * sizeof(bus_dma_segment_t),
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M_DEVBUF, M_NOWAIT | M_ZERO);
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chan->mem_size = desc_size * nsegments;
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if (vmem_alloc(xchan->vmem, chan->mem_size, M_FIRSTFIT | M_NOWAIT,
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&chan->mem_paddr)) {
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device_printf(sc->dev, "Failed to allocate memory.\n");
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return (-1);
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}
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chan->mem_vaddr = kva_alloc(chan->mem_size);
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pmap_kenter_device(chan->mem_vaddr, chan->mem_size, chan->mem_paddr);
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device_printf(sc->dev, "Allocated chunk %lx %d\n",
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chan->mem_paddr, chan->mem_size);
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for (i = 0; i < nsegments; i++) {
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chan->descs[i] = (struct axidma_desc *)
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((uint64_t)chan->mem_vaddr + desc_size * i);
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chan->descs_phys[i] = chan->mem_paddr + desc_size * i;
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}
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return (0);
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}
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static int
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axidma_channel_alloc(device_t dev, struct xdma_channel *xchan)
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{
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xdma_controller_t *xdma;
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struct axidma_fdt_data *data;
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struct axidma_channel *chan;
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struct axidma_softc *sc;
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sc = device_get_softc(dev);
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if (xchan->caps & XCHAN_CAP_BUSDMA) {
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device_printf(sc->dev,
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"Error: busdma operation is not implemented.");
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return (-1);
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}
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xdma = xchan->xdma;
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data = xdma->data;
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chan = &sc->channels[data->id];
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if (chan->used == false) {
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if (axidma_reset(sc, data->id) != 0)
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return (-1);
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chan->xchan = xchan;
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xchan->chan = (void *)chan;
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chan->sc = sc;
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chan->used = true;
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chan->idx_head = 0;
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chan->idx_tail = 0;
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chan->descs_used_count = 0;
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chan->descs_num = AXIDMA_DESCS_NUM;
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return (0);
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}
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return (-1);
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}
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static int
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axidma_channel_free(device_t dev, struct xdma_channel *xchan)
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{
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struct axidma_channel *chan;
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struct axidma_softc *sc;
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sc = device_get_softc(dev);
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chan = (struct axidma_channel *)xchan->chan;
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axidma_desc_free(sc, chan);
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chan->used = false;
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return (0);
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}
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static int
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axidma_channel_capacity(device_t dev, xdma_channel_t *xchan,
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uint32_t *capacity)
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{
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struct axidma_channel *chan;
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uint32_t c;
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chan = (struct axidma_channel *)xchan->chan;
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/* At least one descriptor must be left empty. */
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c = (chan->descs_num - chan->descs_used_count - 1);
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*capacity = c;
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return (0);
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}
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static int
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axidma_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
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struct xdma_sglist *sg, uint32_t sg_n)
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{
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xdma_controller_t *xdma;
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struct axidma_fdt_data *data;
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struct axidma_channel *chan;
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struct axidma_desc *desc;
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struct axidma_softc *sc;
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uint32_t src_addr;
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uint32_t dst_addr;
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uint32_t addr;
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uint32_t len;
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uint32_t tmp;
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int i;
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int tail;
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dprintf("%s: sg_n %d\n", __func__, sg_n);
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sc = device_get_softc(dev);
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chan = (struct axidma_channel *)xchan->chan;
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xdma = xchan->xdma;
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data = xdma->data;
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if (sg_n == 0)
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return (0);
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tail = chan->idx_head;
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tmp = 0;
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for (i = 0; i < sg_n; i++) {
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src_addr = (uint32_t)sg[i].src_addr;
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dst_addr = (uint32_t)sg[i].dst_addr;
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len = (uint32_t)sg[i].len;
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dprintf("%s(%d): src %x dst %x len %d\n", __func__,
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data->id, src_addr, dst_addr, len);
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desc = chan->descs[chan->idx_head];
|
||||
if (sg[i].direction == XDMA_MEM_TO_DEV)
|
||||
desc->phys = src_addr;
|
||||
else
|
||||
desc->phys = dst_addr;
|
||||
desc->status = 0;
|
||||
desc->control = len;
|
||||
if (sg[i].first == 1)
|
||||
desc->control |= BD_CONTROL_TXSOF;
|
||||
if (sg[i].last == 1)
|
||||
desc->control |= BD_CONTROL_TXEOF;
|
||||
|
||||
tmp = chan->idx_head;
|
||||
|
||||
atomic_add_int(&chan->descs_used_count, 1);
|
||||
chan->idx_head = axidma_next_desc(chan, chan->idx_head);
|
||||
}
|
||||
|
||||
dprintf("%s(%d): _curdesc %x\n", __func__, data->id,
|
||||
READ8(sc, AXI_CURDESC(data->id)));
|
||||
dprintf("%s(%d): _curdesc %x\n", __func__, data->id,
|
||||
READ8(sc, AXI_CURDESC(data->id)));
|
||||
dprintf("%s(%d): status %x\n", __func__, data->id,
|
||||
READ4(sc, AXI_DMASR(data->id)));
|
||||
|
||||
addr = chan->descs_phys[tmp];
|
||||
WRITE8(sc, AXI_TAILDESC(data->id), addr);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
axidma_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
|
||||
{
|
||||
xdma_controller_t *xdma;
|
||||
struct axidma_fdt_data *data;
|
||||
struct axidma_channel *chan;
|
||||
struct axidma_desc *desc;
|
||||
struct axidma_softc *sc;
|
||||
uint32_t addr;
|
||||
uint32_t reg;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct axidma_channel *)xchan->chan;
|
||||
xdma = xchan->xdma;
|
||||
data = xdma->data;
|
||||
|
||||
dprintf("%s(%d)\n", __func__, data->id);
|
||||
|
||||
ret = axidma_desc_alloc(sc, xchan, sizeof(struct axidma_desc));
|
||||
if (ret != 0) {
|
||||
device_printf(sc->dev,
|
||||
"%s: Can't allocate descriptors.\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
for (i = 0; i < chan->descs_num; i++) {
|
||||
desc = chan->descs[i];
|
||||
bzero(desc, sizeof(struct axidma_desc));
|
||||
|
||||
if (i == (chan->descs_num - 1))
|
||||
desc->next = chan->descs_phys[0];
|
||||
else
|
||||
desc->next = chan->descs_phys[i + 1];
|
||||
desc->status = 0;
|
||||
desc->control = 0;
|
||||
|
||||
dprintf("%s(%d): desc %d vaddr %lx next paddr %x\n", __func__,
|
||||
data->id, i, (uint64_t)desc, le32toh(desc->next));
|
||||
}
|
||||
|
||||
addr = chan->descs_phys[0];
|
||||
WRITE8(sc, AXI_CURDESC(data->id), addr);
|
||||
|
||||
reg = READ4(sc, AXI_DMACR(data->id));
|
||||
reg |= DMACR_IOC_IRQEN | DMACR_DLY_IRQEN | DMACR_ERR_IRQEN;
|
||||
WRITE4(sc, AXI_DMACR(data->id), reg);
|
||||
reg |= DMACR_RS;
|
||||
WRITE4(sc, AXI_DMACR(data->id), reg);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
axidma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
|
||||
{
|
||||
struct axidma_channel *chan;
|
||||
struct axidma_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct axidma_channel *)xchan->chan;
|
||||
|
||||
switch (cmd) {
|
||||
case XDMA_CMD_BEGIN:
|
||||
case XDMA_CMD_TERMINATE:
|
||||
case XDMA_CMD_PAUSE:
|
||||
/* TODO: implement me */
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef FDT
|
||||
static int
|
||||
axidma_ofw_md_data(device_t dev, pcell_t *cells, int ncells, void **ptr)
|
||||
{
|
||||
struct axidma_fdt_data *data;
|
||||
|
||||
if (ncells != 1)
|
||||
return (-1);
|
||||
|
||||
data = malloc(sizeof(struct axidma_fdt_data),
|
||||
M_DEVBUF, (M_WAITOK | M_ZERO));
|
||||
data->id = cells[0];
|
||||
|
||||
*ptr = data;
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static device_method_t axidma_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, axidma_probe),
|
||||
DEVMETHOD(device_attach, axidma_attach),
|
||||
DEVMETHOD(device_detach, axidma_detach),
|
||||
|
||||
/* xDMA Interface */
|
||||
DEVMETHOD(xdma_channel_alloc, axidma_channel_alloc),
|
||||
DEVMETHOD(xdma_channel_free, axidma_channel_free),
|
||||
DEVMETHOD(xdma_channel_control, axidma_channel_control),
|
||||
|
||||
/* xDMA SG Interface */
|
||||
DEVMETHOD(xdma_channel_capacity, axidma_channel_capacity),
|
||||
DEVMETHOD(xdma_channel_prep_sg, axidma_channel_prep_sg),
|
||||
DEVMETHOD(xdma_channel_submit_sg, axidma_channel_submit_sg),
|
||||
|
||||
#ifdef FDT
|
||||
DEVMETHOD(xdma_ofw_md_data, axidma_ofw_md_data),
|
||||
#endif
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t axidma_driver = {
|
||||
"axidma",
|
||||
axidma_methods,
|
||||
sizeof(struct axidma_softc),
|
||||
};
|
||||
|
||||
static devclass_t axidma_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(axidma, simplebus, axidma_driver, axidma_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
||||
96
sys/dev/xilinx/axidma.h
Normal file
96
sys/dev/xilinx/axidma.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com>
|
||||
*
|
||||
* This software was developed by SRI International and the University of
|
||||
* Cambridge Computer Laboratory (Department of Computer Science and
|
||||
* Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
|
||||
* DARPA SSITH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_XILINX_AXIDMA_H_
|
||||
#define _DEV_XILINX_AXIDMA_H_
|
||||
|
||||
#define AXI_DMACR(n) (0x00 + 0x30 * (n)) /* DMA Control register */
|
||||
#define DMACR_RS (1 << 0) /* Run / Stop. */
|
||||
#define DMACR_RESET (1 << 2) /* Soft reset the AXI DMA core. */
|
||||
#define DMACR_IOC_IRQEN (1 << 12) /* Interrupt on Complete (IOC) Interrupt Enable. */
|
||||
#define DMACR_DLY_IRQEN (1 << 13) /* Interrupt on Delay Timer Interrupt Enable. */
|
||||
#define DMACR_ERR_IRQEN (1 << 14) /* Interrupt on Error Interrupt Enable. */
|
||||
#define AXI_DMASR(n) (0x04 + 0x30 * (n)) /* DMA Status register */
|
||||
#define DMASR_HALTED (1 << 0)
|
||||
#define DMASR_IDLE (1 << 1)
|
||||
#define DMASR_SGINCLD (1 << 3) /* Scatter Gather Enabled */
|
||||
#define DMASR_DMAINTERR (1 << 4) /* DMA Internal Error. */
|
||||
#define DMASR_DMASLVERR (1 << 5) /* DMA Slave Error. */
|
||||
#define DMASR_DMADECOREERR (1 << 6) /* Decode Error. */
|
||||
#define DMASR_SGINTERR (1 << 8) /* Scatter Gather Internal Error. */
|
||||
#define DMASR_SGSLVERR (1 << 9) /* Scatter Gather Slave Error. */
|
||||
#define DMASR_SGDECERR (1 << 10) /* Scatter Gather Decode Error. */
|
||||
#define DMASR_IOC_IRQ (1 << 12) /* Interrupt on Complete. */
|
||||
#define DMASR_DLY_IRQ (1 << 13) /* Interrupt on Delay. */
|
||||
#define DMASR_ERR_IRQ (1 << 14) /* Interrupt on Error. */
|
||||
#define AXI_CURDESC(n) (0x08 + 0x30 * (n)) /* Current Descriptor Pointer. Lower 32 bits of the address. */
|
||||
#define AXI_CURDESC_MSB(n) (0x0C + 0x30 * (n)) /* Current Descriptor Pointer. Upper 32 bits of address. */
|
||||
#define AXI_TAILDESC(n) (0x10 + 0x30 * (n)) /* Tail Descriptor Pointer. Lower 32 bits. */
|
||||
#define AXI_TAILDESC_MSB(n) (0x14 + 0x30 * (n)) /* Tail Descriptor Pointer. Upper 32 bits of address. */
|
||||
#define AXI_SG_CTL 0x2C /* Scatter/Gather User and Cache */
|
||||
|
||||
#define READ4(_sc, _reg) \
|
||||
bus_space_read_4(_sc->bst, _sc->bsh, _reg)
|
||||
#define WRITE4(_sc, _reg, _val) \
|
||||
bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
|
||||
#define READ8(_sc, _reg) \
|
||||
bus_space_read_8(_sc->bst, _sc->bsh, _reg)
|
||||
#define WRITE8(_sc, _reg, _val) \
|
||||
bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val)
|
||||
|
||||
struct axidma_desc {
|
||||
uint32_t next;
|
||||
uint32_t reserved1;
|
||||
uint32_t phys;
|
||||
uint32_t reserved2;
|
||||
uint32_t reserved3;
|
||||
uint32_t reserved4;
|
||||
uint32_t control;
|
||||
#define BD_CONTROL_TXSOF (1 << 27) /* Start of Frame. */
|
||||
#define BD_CONTROL_TXEOF (1 << 26) /* End of Frame. */
|
||||
#define BD_CONTROL_LEN_S 0 /* Buffer Length. */
|
||||
#define BD_CONTROL_LEN_M (0x3ffffff << BD_CONTROL_LEN_S)
|
||||
uint32_t status;
|
||||
#define BD_STATUS_CMPLT (1 << 31)
|
||||
#define BD_STATUS_TRANSFERRED_S 0
|
||||
#define BD_STATUS_TRANSFERRED_M (0x7fffff << BD_STATUS_TRANSFERRED_S)
|
||||
uint32_t app0;
|
||||
uint32_t app1;
|
||||
uint32_t app2;
|
||||
uint32_t app3;
|
||||
uint32_t app4;
|
||||
uint32_t reserved[3];
|
||||
};
|
||||
|
||||
#endif /* !_DEV_XILINX_AXIDMA_H_ */
|
||||
Loading…
Reference in New Issue
Block a user