ixl(4): Fix errors in queue interrupt setup in MSIX mode.
- I40E_PFINT_DYN_CTLN needs to be cleared, and not have a queue index written to it. - The interrupt linked list for each queue is changed to only include the queue's Rx and Tx queues. Differential Revision: https://reviews.freebsd.org/D5206 Reviewed by: sbruno Tested by: jeffrey.e.pieper@intel.com Sponsored by: Intel Corporation
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@ -2246,7 +2246,8 @@ ixl_configure_msix(struct ixl_pf *pf)
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/* Next configure the queues */
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/* Next configure the queues */
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for (int i = 0; i < vsi->num_queues; i++, vector++) {
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for (int i = 0; i < vsi->num_queues; i++, vector++) {
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wr32(hw, I40E_PFINT_DYN_CTLN(i), i);
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wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
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/* First queue type is RX / type 0 */
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wr32(hw, I40E_PFINT_LNKLSTN(i), i);
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wr32(hw, I40E_PFINT_LNKLSTN(i), i);
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reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
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reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
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@ -2259,11 +2260,8 @@ ixl_configure_msix(struct ixl_pf *pf)
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reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
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reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
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(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
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(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
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(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
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(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
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((i+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
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(IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
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(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
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(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
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if (i == (vsi->num_queues - 1))
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reg |= (IXL_QUEUE_EOL
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<< I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
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wr32(hw, I40E_QINT_TQCTL(i), reg);
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wr32(hw, I40E_QINT_TQCTL(i), reg);
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}
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}
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}
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}
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