From 22aeed02bfd8460da1b66e2d78d9b018c0beb959 Mon Sep 17 00:00:00 2001
From: Adrian Chadd <adrian@FreeBSD.org>
Date: Sat, 14 Mar 2015 07:59:54 +0000
Subject: [PATCH] Add board support for the TP-Link TL-WR1043nd v2.

This is a QCA9558 based design with on-chip 2GHz 3x3 11n wifi,
AR8327N switch, 64MB RAM and 8MB flash.

Of course, it runs FreeBSD.
---
 sys/mips/conf/TL-WR1043NDv2       |  51 ++++++++++
 sys/mips/conf/TL-WR1043NDv2.hints | 149 ++++++++++++++++++++++++++++++
 2 files changed, 200 insertions(+)
 create mode 100644 sys/mips/conf/TL-WR1043NDv2
 create mode 100644 sys/mips/conf/TL-WR1043NDv2.hints

diff --git a/sys/mips/conf/TL-WR1043NDv2 b/sys/mips/conf/TL-WR1043NDv2
new file mode 100644
index 000000000000..48fddf0bb735
--- /dev/null
+++ b/sys/mips/conf/TL-WR1043NDv2
@@ -0,0 +1,51 @@
+#
+# TP-Link TL-WR1043nd v2 - based on the AP135 reference design.
+#
+# This contains a QCA9558 MIPS74k SoC with on-board 3x3 2GHz wifi,
+# 64MiB RAM and an AR8327 5-port gigabit ethernet switch.
+#
+# $FreeBSD$
+#
+
+# Include the default QCA955x parameters
+include         "QCA955X_BASE"
+
+ident           TL-WR1043NDv2
+
+# Override hints with board values
+hints           "TL-WR1043NDv2.hints"
+
+options         AR71XX_REALMEM=(64*1024*1024)
+
+# Options required for miiproxy and mdiobus
+options 	ARGE_MDIO	# Export an MDIO bus separate from arge
+device		miiproxy	# MDIO bus <-> MII PHY rendezvous
+
+device		etherswitch
+device		arswitch
+
+# read MSDOS formatted disks - USB
+options 	MSDOSFS
+
+# Enable the uboot environment stuff rather then the
+# redboot stuff.
+options 	AR71XX_ENV_UBOOT
+
+# uzip - to boot natively from flash
+device		geom_uncompress
+options 	GEOM_UNCOMPRESS
+
+# Used for the static uboot partition map
+device          geom_map
+
+# yes, this board has a PCI connected atheros device
+#device		ath_pci
+#options 	AR71XX_ATH_EEPROM
+#device		firmware		# Used by the above
+#options 	ATH_EEPROM_FIRMWARE
+
+# Boot off of the rootfs, as defined in the geom_map setup.
+options 	ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
+
+# Default to accept
+options		IPFIREWALL_DEFAULT_TO_ACCEPT
diff --git a/sys/mips/conf/TL-WR1043NDv2.hints b/sys/mips/conf/TL-WR1043NDv2.hints
new file mode 100644
index 000000000000..b7e283118f32
--- /dev/null
+++ b/sys/mips/conf/TL-WR1043NDv2.hints
@@ -0,0 +1,149 @@
+# The TP-Link 1043NDv2 is based on the AP135 with a couple of minor
+# differences - well, besides having no 11ac.
+
+# $FreeBSD$
+
+# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
+hint.qca955x_gmac.0.gmac_cfg=0x1
+
+# mdiobus0 on arge0
+hint.argemdio.0.at="nexus0"
+hint.argemdio.0.maddr=0x19000000
+hint.argemdio.0.msize=0x1000
+hint.argemdio.0.order=0
+
+# mdiobus1 on arge1 - required to bring up arge1?
+hint.argemdio.1.at="nexus0"
+hint.argemdio.1.maddr=0x1a000000
+hint.argemdio.1.msize=0x1000
+hint.argemdio.1.order=0
+
+# AR8327 - connected via mdiobus0 on arge0
+hint.arswitch.0.at="mdio0"
+hint.arswitch.0.is_7240=0	# definitely not the internal switch!
+hint.arswitch.0.is_9340=0	# not the internal switch!
+hint.arswitch.0.numphys=5	# all ports are PHYs
+hint.arswitch.0.phy4cpu=0
+hint.arswitch.0.is_rgmii=0	# not needed
+hint.arswitch.0.is_gmii=0	# not needed
+
+# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
+# The current code only supports one CPU port.  So hm, what should
+# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
+
+# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
+# That's currently supposed to be hooked up to CPU port 0.
+
+# Other AR8327 configuration parameters
+
+# AP136-020 parameters
+
+# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
+
+# AR8327_PAD_MAC_SGMII
+hint.arswitch.0.pad.0.mode=3
+#hint.arswitch.0.pad.0.rxclk_delay_sel=0
+hint.arswitch.0.pad.0.sgmii_delay_en=1
+
+# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
+
+# AR8327_PAD_MAC_RGMII
+hint.arswitch.0.pad.6.mode=6
+hint.arswitch.0.pad.6.txclk_delay_en=1
+hint.arswitch.0.pad.6.rxclk_delay_en=1
+# AR8327_CLK_DELAY_SEL1
+hint.arswitch.0.pad.6.txclk_delay_sel=1
+# AR8327_CLK_DELAY_SEL2
+hint.arswitch.0.pad.6.rxclk_delay_sel=2
+
+hint.arswitch.0.led.ctrl0=0xcc35cc35
+hint.arswitch.0.led.ctrl1=0xca35ca35
+hint.arswitch.0.led.ctrl2=0xc935c935
+hint.arswitch.0.led.ctrl3=0x03ffff00
+int.arswitch.0.led.open_drain=1
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.0.force_link=1
+hint.arswitch.0.port.0.speed=1000
+hint.arswitch.0.port.0.duplex=1
+hint.arswitch.0.port.0.txpause=1
+hint.arswitch.0.port.0.rxpause=1
+
+# force_link=1 is required for the rest of the parameters
+# to be configured.
+hint.arswitch.0.port.6.force_link=1
+hint.arswitch.0.port.6.speed=1000
+hint.arswitch.0.port.6.duplex=1
+hint.arswitch.0.port.6.txpause=1
+hint.arswitch.0.port.6.rxpause=1
+
+# arge0 - hooked up to AR8327 GMAC6, RGMII
+# set at 1000/full to the switch.
+# so, lock both sides of this connect up to 1000/full;
+# if_arge thus wont change the PLL configuration
+# upon a link status change.
+hint.arge.0.phymask=0x0
+hint.arge.0.miimode=3           # RGMII
+hint.arge.0.media=1000
+hint.arge.0.fduplex=1
+hint.arge.0.pll_1000=0x56000000
+
+hint.arge.0.eeprommac=0x1f01fc00
+
+# arge1 - lock up to 1000/full
+hint.arge.1.phymask=0x0
+hint.arge.1.media=1000
+hint.arge.1.fduplex=1
+hint.arge.1.miimode=5		# SGMII
+hint.arge.1.pll_1000=0x03000101
+
+# hint.arge.1.eeprommac=0x1f01fc06
+
+# ath0: Where the ART is - last 64k in the flash
+hint.ath.0.eepromaddr=0x1fff0000
+hint.ath.0.eepromsize=16384
+
+# 128 KiB u-boot
+hint.map.0.at="flash/spi0"
+hint.map.0.start=0x00000000
+hint.map.0.end=0x00020000	# 128k u-boot
+hint.map.0.name="u-boot"
+hint.map.0.readonly=1
+
+# The TP-Link firmware will put the kernel first (variable size);
+# then the rootfs will be placed hopefully at a 64KiB alignment
+# by whatever calls mktplinkfw.
+
+hint.map.1.at="flash/spi0"
+hint.map.1.start=0x00020000
+hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
+hint.map.1.name="kernel"
+hint.map.1.readonly=1
+
+hint.map.2.at="flash/spi0"
+hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
+hint.map.2.end=0x007d0000
+hint.map.2.name="rootfs"
+hint.map.2.readonly=1
+
+# 64KiB cfg
+hint.map.3.at="flash/spi0"
+hint.map.3.start=0x007d0000
+hint.map.3.end=0x007e0000
+hint.map.3.name="cfg"
+hint.map.3.readonly=0
+
+# 64KiB mib0
+hint.map.4.at="flash/spi0"
+hint.map.4.start=0x007e0000
+hint.map.4.end=0x007f0000
+hint.map.4.name="mib0"
+hint.map.4.readonly=1
+
+# 64KiB ART
+hint.map.5.at="flash/spi0"
+hint.map.5.start=0x007f0000
+hint.map.5.end=0x00800000	# 64k ART
+hint.map.5.name="ART"
+hint.map.5.readonly=1