Import xscale core 3 cache management functions.
Approved by: re (blanket)
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cognet
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397
sys/arm/arm/cpufunc_asm_xscale_c3.S
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397
sys/arm/arm/cpufunc_asm_xscale_c3.S
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/* $NetBSD: cpufunc_asm_xscale.S,v 1.16 2002/08/17 16:36:32 thorpej Exp $ */
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/*-
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* Copyright (c) 2007 Olivier Houchard
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Allen Briggs and Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*-
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* Copyright (c) 2001 Matt Thomas.
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* XScale core 3 assembly functions for CPU / MMU / TLB specific operations
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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/*
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* Size of the XScale core D-cache.
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*/
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#define DCACHE_SIZE 0x00008000
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.Lblock_userspace_access:
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.word _C_LABEL(block_userspace_access)
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/*
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* CPWAIT -- Canonical method to wait for CP15 update.
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* From: Intel 80200 manual, section 2.3.3.
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*
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* NOTE: Clobbers the specified temp reg.
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*/
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#define CPWAIT_BRANCH \
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sub pc, pc, #4
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#define CPWAIT(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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mov tmp, tmp /* wait for it to complete */ ;\
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CPWAIT_BRANCH /* branch to next insn */
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#define CPWAIT_AND_RETURN_SHIFTER lsr #32
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#define CPWAIT_AND_RETURN(tmp) \
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mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
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/* Wait for it to complete and branch to the return address */ \
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sub pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER
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#define ARM_USE_L2_CACHE
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#define L2_CACHE_SIZE 0x80000
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#define L2_CACHE_WAYS 8
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#define L2_CACHE_LINE_SIZE 32
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#define L2_CACHE_SETS (L2_CACHE_SIZE / \
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(L2_CACHE_WAYS * L2_CACHE_LINE_SIZE))
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#define L1_DCACHE_SIZE 32 * 1024
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#define L1_DCACHE_WAYS 4
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#define L1_DCACHE_LINE_SIZE 32
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#define L1_DCACHE_SETS (L1_DCACHE_SIZE / \
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(L1_DCACHE_WAYS * L1_DCACHE_LINE_SIZE))
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#ifdef CACHE_CLEAN_BLOCK_INTR
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#define XSCALE_CACHE_CLEAN_BLOCK \
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stmfd sp!, {r4} ; \
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mrs r4, cpsr_all ; \
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orr r0, r4, #(I32_bit | F32_bit) ; \
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msr cpsr_all, r0
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#define XSCALE_CACHE_CLEAN_UNBLOCK \
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msr cpsr_all, r4 ; \
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ldmfd sp!, {r4}
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#else
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#define XSCALE_CACHE_CLEAN_BLOCK \
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stmfd sp!, {r4} ; \
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ldr r4, .Lblock_userspace_access ; \
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ldr ip, [r4] ; \
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orr r0, ip, #1 ; \
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str r0, [r4]
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#define XSCALE_CACHE_CLEAN_UNBLOCK \
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str ip, [r3] ; \
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ldmfd sp!, {r4}
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#endif /* CACHE_CLEAN_BLOCK_INTR */
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ENTRY_NP(xscalec3_cache_syncI)
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ENTRY_NP(xscalec3_cache_purgeID)
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mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
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ENTRY_NP(xscalec3_cache_cleanID)
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ENTRY_NP(xscalec3_cache_purgeD)
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ENTRY(xscalec3_cache_cleanD)
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XSCALE_CACHE_CLEAN_BLOCK
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mov r0, #0
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1:
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mov r1, r0, asl #30
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mov r2, #0
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2:
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orr r3, r1, r2, asl #5
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mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */
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add r2, r2, #1
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cmp r2, #L1_DCACHE_SETS
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bne 2b
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add r0, r0, #1
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cmp r0, #4
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bne 1b
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CPWAIT(r0)
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XSCALE_CACHE_CLEAN_UNBLOCK
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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RET
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ENTRY(xscalec3_cache_purgeID_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscalec3_cache_cleanID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */
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nop
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mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_cache_syncI_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscalec3_cache_syncI)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
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mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_cache_purgeD_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscalec3_cache_cleanID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c14, 1 /* Clean and invalidate D cache entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_cache_cleanID_rng)
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ENTRY(xscalec3_cache_cleanD_rng)
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cmp r1, #0x4000
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bcs _C_LABEL(xscalec3_cache_cleanID)
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 0, r0, c7, c10, 1 /* clean L1 D cache entry */
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nop
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_l2cache_purge)
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/* Clean-up the L2 cache */
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mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
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mov r0, #0
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1:
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mov r1, r0, asl #29
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mov r2, #0
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2:
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orr r3, r1, r2, asl #5
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mcr p15, 1, r3, c7, c15, 2
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add r2, r2, #1
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cmp r2, #L2_CACHE_SETS
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bne 2b
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add r0, r0, #1
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cmp r0, #8
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bne 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
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RET
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ENTRY(xscalec3_l2cache_clean_rng)
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mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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CPWAIT(r0)
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c10, 5
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_l2cache_purge_rng)
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mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 1, r0, c7, c11, 1 /* Clean L2 D cache entry */
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mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 D cache entry */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c10, 5
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CPWAIT_AND_RETURN(r0)
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ENTRY(xscalec3_l2cache_flush_rng)
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mcr p15, 0, r0, c7, c10, 5 /* Data memory barrier */
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and r2, r0, #0x1f
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add r1, r1, r2
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bic r0, r0, #0x1f
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1: mcr p15, 1, r0, c7, c7, 1 /* Invalidate L2 cache line */
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add r0, r0, #32
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subs r1, r1, #32
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c10, 5
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CPWAIT_AND_RETURN(r0)
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/*
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* Functions to set the MMU Translation Table Base register
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*
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* We need to clean and flush the cache as it uses virtual
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* addresses that are about to change.
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*/
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ENTRY(xscalec3_setttb)
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#ifdef CACHE_CLEAN_BLOCK_INTR
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit | F32_bit)
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msr cpsr_all, r1
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#else
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ldr r3, .Lblock_userspace_access
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ldr r2, [r3]
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orr r1, r2, #1
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str r1, [r3]
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#endif
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stmfd sp!, {r0-r3, lr}
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bl _C_LABEL(xscalec3_cache_cleanID)
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
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mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
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CPWAIT(r0)
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ldmfd sp!, {r0-r3, lr}
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#ifdef ARM_USE_L2_CACHE
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orr r0, r0, #0x18 /* cache the page table in L2 */
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#endif
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
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CPWAIT(r0)
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#ifdef CACHE_CLEAN_BLOCK_INTR
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msr cpsr_all, r3
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#else
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str r2, [r3]
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#endif
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RET
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/*
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* Context switch.
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*
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* These is the CPU-specific parts of the context switcher cpu_switch()
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* These functions actually perform the TTB reload.
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*
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* NOTE: Special calling convention
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* r1, r4-r13 must be preserved
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*/
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ENTRY(xscalec3_context_switch)
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/*
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* CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
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* Thus the data cache will contain only kernel data and the
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* instruction cache will contain only kernel code, and all
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* kernel mappings are shared by all processes.
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*/
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#ifdef ARM_USE_L2_CACHE
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orr r0, r0, #0x18 /* Cache the page table in L2 */
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#endif
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/* Write the TTB */
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mcr p15, 0, r0, c2, c0, 0
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/* If we have updated the TTB we must flush the TLB */
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mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
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CPWAIT_AND_RETURN(r0)
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