Add support for the 'xsave', 'xrstor', 'xsaveopt', 'xgetbv', and 'xsetbv'
instructions. I reimplemented this from scratch based on the Intel manuals and the existing support for handling the fxsave and fxrstor instructions. This will let us use these instructions natively with GCC rather than hardcoding the opcodes in hex. Reviewed by: kib MFC after: 1 month
This commit is contained in:
John Baldwin
parent
1ebccfd0a2
commit
22f9e86238
@ -517,7 +517,9 @@ static const arch_entry cpu_arch[] =
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{".sse4a", PROCESSOR_UNKNOWN,
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CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
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{".abm", PROCESSOR_UNKNOWN,
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CpuABM}
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CpuABM},
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{".xsave", PROCESSOR_UNKNOWN,
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CpuXSAVE}
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};
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const pseudo_typeS md_pseudo_table[] =
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@ -93,6 +93,7 @@ static void OP_3DNowSuffix (int, int);
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static void OP_SIMD_Suffix (int, int);
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static void SIMD_Fixup (int, int);
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static void PNI_Fixup (int, int);
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static void XCR_Fixup (int, int);
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static void SVME_Fixup (int, int);
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static void INVLPG_Fixup (int, int);
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static void BadOp (void);
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@ -1693,7 +1694,7 @@ static const struct dis386 grps[][8] = {
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{
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{ "sgdt{Q|IQ||}", { { VMX_Fixup, 0 } } },
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{ "sidt{Q|IQ||}", { { PNI_Fixup, 0 } } },
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{ "lgdt{Q|Q||}", { M } },
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{ "lgdt{Q|Q||}", { { XCR_Fixup, 0 } } },
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{ "lidt{Q|Q||}", { { SVME_Fixup, 0 } } },
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{ "smswD", { Sv } },
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{ "(bad)", { XX } },
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@ -1783,9 +1784,9 @@ static const struct dis386 grps[][8] = {
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{ "fxrstor", { Ev } },
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{ "ldmxcsr", { Ev } },
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{ "stmxcsr", { Ev } },
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{ "(bad)", { XX } },
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{ "lfence", { { OP_0fae, 0 } } },
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{ "mfence", { { OP_0fae, 0 } } },
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{ "xsave", { Ev } },
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{ "xrstor", { { OP_0fae, v_mode } } },
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{ "xsaveopt", { { OP_0fae, v_mode } } },
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{ "clflush", { { OP_0fae, 0 } } },
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},
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/* GRP16 */
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@ -5905,17 +5906,17 @@ OP_0fae (int bytemode, int sizeflag)
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{
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if (modrm.reg == 7)
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strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence");
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else if (modrm.reg == 6)
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strcpy (obuf + strlen (obuf) - sizeof ("xsaveopt") + 1, "mfence");
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else if (modrm.reg == 5)
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strcpy (obuf + strlen (obuf) - sizeof ("xrstor") + 1, "lfence");
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if (modrm.reg < 5 || modrm.rm != 0)
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{
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BadOp (); /* bad sfence, mfence, or lfence */
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return;
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}
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}
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else if (modrm.reg != 7)
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{
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BadOp (); /* bad clflush */
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return;
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bytemode = 0;
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}
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OP_E (bytemode, sizeflag);
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@ -6169,6 +6170,43 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
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OP_M (0, sizeflag);
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}
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static void
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XCR_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
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{
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if (modrm.mod == 3 && modrm.reg == 2 && modrm.rm <= 1)
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{
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/* Override "lgdt". */
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size_t olen = strlen (obuf);
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char *p = obuf + olen - 4;
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/* We might have a suffix when disassembling with -Msuffix. */
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if (*p == 'i')
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--p;
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/* Remove "addr16/addr32" if we aren't in Intel mode. */
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if (!intel_syntax
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&& (prefixes & PREFIX_ADDR)
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&& olen >= (4 + 7)
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&& *(p - 1) == ' '
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&& CONST_STRNEQ (p - 7, "addr")
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&& (CONST_STRNEQ (p - 3, "16")
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|| CONST_STRNEQ (p - 3, "32")))
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p -= 7;
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if (modrm.rm)
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{
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strcpy (p, "xsetbv");
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}
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else
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{
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strcpy (p, "xgetbv");
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}
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codep++;
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}
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else
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OP_M (0, sizeflag);
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}
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static void
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SVME_Fixup (int bytemode, int sizeflag)
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{
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@ -71,6 +71,7 @@ typedef struct template
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#define CpuABM 0x200000 /* ABM New Instructions required */
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#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */
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#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */
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#define CpuXSAVE 0x1000000 /* XSAVE Instructions required */
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/* SSE4.1/4.2 Instructions required */
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#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
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@ -83,7 +84,7 @@ typedef struct template
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#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
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|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
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|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
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|CpuSSE4_2|CpuABM|CpuSSE4a)
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|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE)
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -1487,3 +1487,10 @@ xcryptcfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf
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xcryptofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 }
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// Alias for xstore-rng.
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xstore, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 }
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// XSAVE/XRSTOR related instructions
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xgetbv, 0, 0xf01, 0xd0, CpuXSAVE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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xsetbv, 0, 0xf01, 0xd1, CpuXSAVE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 }
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xsave, 1, 0xfae, 0x4, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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xsaveopt, 1, 0xfae, 0x6, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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@ -4288,6 +4288,21 @@ const template i386_optab[] =
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{ "xstore", 0, 0xfa7, 0xc0, Cpu686|CpuPadLock,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt,
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{ 0 } },
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{ "xgetbv", 0, 0xf01, 0xd0, CpuXSAVE,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
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{ 0 } },
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{ "xsetbv", 0, 0xf01, 0xd1, CpuXSAVE,
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No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
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{ 0 } },
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{ "xsave", 1, 0xfae, 0x4, CpuXSAVE,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "xsaveopt", 1, 0xfae, 0x6, CpuXSAVE,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ "xrstor", 1, 0xfae, 0x5, CpuXSAVE,
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Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
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{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
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{ NULL, 0, 0, 0, 0, 0, { 0 } }
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};
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