MFpc98: fundamental differences. The magic numbers for the i/o port
and the irq are different for pc98, and are not very well handled (we use a historical mess of hard-coded values, values from header files and values from hints).
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bde
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86656e8047
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23731f7ff2
@ -76,8 +76,12 @@
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#ifndef SMP
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#endif
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#include <isa/isavar.h>
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/*
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@ -226,7 +230,11 @@ npx_intr(dummy)
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* The BUSY# latch must be cleared in all cases so that the next
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* unmasked npx exception causes an interrupt.
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*/
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#ifdef PC98
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outb(0xf8, 0);
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#else
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outb(0xf0, 0);
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#endif
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/*
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* npxthread is normally non-null here. In that case, schedule an
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@ -275,8 +283,13 @@ npx_probe(dev)
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IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE);
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if (ioport_res == NULL)
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panic("npx: can't get ports");
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#ifdef PC98
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 8;
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#else
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 13;
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#endif
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irq_rid = 0;
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irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num,
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irq_num, 1, RF_ACTIVE);
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@ -291,8 +304,12 @@ npx_probe(dev)
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* Partially reset the coprocessor, if any. Some BIOS's don't reset
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* it after a warm boot.
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*/
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#ifdef PC98
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outb(0xf8,0);
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#else
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outb(0xf1, 0); /* full reset on some systems, NOP on others */
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outb(0xf0, 0); /* clear BUSY# latch */
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#endif
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/*
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* Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
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* instructions. We must set the CR0_MP bit and use the CR0_TS
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@ -76,8 +76,12 @@
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#ifndef SMP
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#endif
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#include <isa/isavar.h>
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/*
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@ -226,7 +230,11 @@ npx_intr(dummy)
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* The BUSY# latch must be cleared in all cases so that the next
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* unmasked npx exception causes an interrupt.
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*/
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#ifdef PC98
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outb(0xf8, 0);
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#else
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outb(0xf0, 0);
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#endif
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/*
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* npxthread is normally non-null here. In that case, schedule an
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@ -275,8 +283,13 @@ npx_probe(dev)
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IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE);
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if (ioport_res == NULL)
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panic("npx: can't get ports");
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#ifdef PC98
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 8;
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#else
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 13;
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#endif
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irq_rid = 0;
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irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num,
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irq_num, 1, RF_ACTIVE);
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@ -291,8 +304,12 @@ npx_probe(dev)
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* Partially reset the coprocessor, if any. Some BIOS's don't reset
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* it after a warm boot.
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*/
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#ifdef PC98
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outb(0xf8,0);
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#else
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outb(0xf1, 0); /* full reset on some systems, NOP on others */
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outb(0xf0, 0); /* clear BUSY# latch */
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#endif
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/*
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* Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
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* instructions. We must set the CR0_MP bit and use the CR0_TS
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@ -76,8 +76,12 @@
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#ifndef SMP
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#endif
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#include <isa/isavar.h>
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/*
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@ -226,7 +230,11 @@ npx_intr(dummy)
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* The BUSY# latch must be cleared in all cases so that the next
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* unmasked npx exception causes an interrupt.
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*/
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#ifdef PC98
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outb(0xf8, 0);
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#else
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outb(0xf0, 0);
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#endif
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/*
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* npxthread is normally non-null here. In that case, schedule an
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@ -275,8 +283,13 @@ npx_probe(dev)
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IO_NPX, IO_NPX, IO_NPXSIZE, RF_ACTIVE);
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if (ioport_res == NULL)
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panic("npx: can't get ports");
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#ifdef PC98
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 8;
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#else
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if (resource_int_value("npx", 0, "irq", &irq_num) != 0)
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irq_num = 13;
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#endif
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irq_rid = 0;
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irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &ioport_rid, irq_num,
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irq_num, 1, RF_ACTIVE);
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@ -291,8 +304,12 @@ npx_probe(dev)
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* Partially reset the coprocessor, if any. Some BIOS's don't reset
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* it after a warm boot.
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*/
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#ifdef PC98
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outb(0xf8,0);
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#else
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outb(0xf1, 0); /* full reset on some systems, NOP on others */
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outb(0xf0, 0); /* clear BUSY# latch */
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#endif
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/*
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* Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
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* instructions. We must set the CR0_MP bit and use the CR0_TS
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