MIPS n64 support - support kstack in XKSEG.
- enable KX on entry from user-space, we need KX set to save to XKSEG addresses. - add MIPS_XKSEG_START to genassym.c - Add n64 case for swth.S
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@ -426,6 +426,12 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
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/*
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* Save all of the registers except for the kernel temporaries in u.u_pcb.
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*/
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mfc0 k0, MIPS_COP_0_STATUS
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HAZARD_DELAY
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#ifdef __mips_n64
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ori k1, k0, MIPS_SR_KX
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mtc0 k1, MIPS_COP_0_STATUS
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#endif
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GET_CPU_PCPU(k1)
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PTR_L k1, PC_CURPCB(k1)
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SAVE_U_PCB_REG(AT, AST, k1)
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@ -443,7 +449,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
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SAVE_U_PCB_REG(t2, T2, k1)
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SAVE_U_PCB_REG(t3, T3, k1)
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SAVE_U_PCB_REG(ta0, TA0, k1)
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mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
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move a0, k0 # First arg is the status reg.
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SAVE_U_PCB_REG(ta1, TA1, k1)
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SAVE_U_PCB_REG(ta2, TA2, k1)
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SAVE_U_PCB_REG(ta3, TA3, k1)
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@ -642,6 +648,12 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
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* Save the relevant user registers into the u.u_pcb struct.
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* We don't need to save s0 - s8 because the compiler does it for us.
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*/
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mfc0 k0, MIPS_COP_0_STATUS
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HAZARD_DELAY
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#ifdef __mips_n64
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ori k1, k0, MIPS_SR_KX
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mtc0 k1, MIPS_COP_0_STATUS
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#endif
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GET_CPU_PCPU(k1)
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PTR_L k1, PC_CURPCB(k1)
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SAVE_U_PCB_REG(AT, AST, k1)
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@ -680,7 +692,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
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mflo v0 # get lo/hi late to avoid stall
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mfhi v1
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mfc0 a0, MIPS_COP_0_STATUS
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move a0, k0
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mfc0 a1, MIPS_COP_0_CAUSE
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MFC0 a3, MIPS_COP_0_EXC_PC
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SAVE_U_PCB_REG(v0, MULLO, k1)
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@ -103,3 +103,4 @@ ASSYM(MAXCOMLEN, MAXCOMLEN);
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ASSYM(MIPS_KSEG0_START, MIPS_KSEG0_START);
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ASSYM(MIPS_KSEG1_START, MIPS_KSEG1_START);
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ASSYM(MIPS_KSEG2_START, MIPS_KSEG2_START);
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ASSYM(MIPS_XKSEG_START, MIPS_XKSEG_START);
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@ -278,10 +278,12 @@ blocked_loop:
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PTR_L a2, TD_PCB(a1)
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PTR_S a2, PC_CURPCB(a3)
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PTR_L v0, TD_KSTACK(a1)
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#if !defined(__mips_n64)
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#if defined(__mips_n64)
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PTR_LI s0, MIPS_XKSEG_START
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#else
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PTR_LI s0, MIPS_KSEG2_START # If Uarea addr is below kseg2,
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bltu v0, s0, sw2 # no need to insert in TLB.
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#endif
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bltu v0, s0, sw2 # no need to insert in TLB.
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lw a1, TD_UPTE + 0(s7) # a1 = u. pte #0
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lw a2, TD_UPTE + 4(s7) # a2 = u. pte #1
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/*
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