aw_mmc: Do not fully init the controller in attach
Only do a reset of the controller at attach and init it at power_up. We use to enable some interrupts in reset, only enable the interrupts we are interested in when doing a request. While here remove the regulators handling in power_on as it is very wrong and will be dealt with in another commit. Tested on: A31, A64
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manu
parent
9ce08fe12f
commit
25129c5588
@ -140,6 +140,7 @@ static int aw_mmc_attach(device_t);
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static int aw_mmc_detach(device_t);
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static int aw_mmc_setup_dma(struct aw_mmc_softc *);
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static int aw_mmc_reset(struct aw_mmc_softc *);
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static int aw_mmc_init(struct aw_mmc_softc *);
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static void aw_mmc_intr(void *);
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static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t);
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@ -475,18 +476,37 @@ aw_mmc_reset(struct aw_mmc_softc *sc)
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if (timeout == 0)
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return (ETIMEDOUT);
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return (0);
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}
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static int
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aw_mmc_init(struct aw_mmc_softc *sc)
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{
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int ret;
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ret = aw_mmc_reset(sc);
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if (ret != 0)
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return (ret);
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/* Set the timeout. */
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AW_MMC_WRITE_4(sc, AW_MMC_TMOR,
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AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) |
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AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK));
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/* Unmask interrupts. */
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AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0);
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/* Clear pending interrupts. */
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AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
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/* Debug register, undocumented */
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AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb);
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/* Function select register */
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AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000);
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AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff);
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/* Unmask interrupts. */
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AW_MMC_WRITE_4(sc, AW_MMC_IMKR,
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AW_MMC_INT_CMD_DONE | AW_MMC_INT_ERR_BIT |
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AW_MMC_INT_DATA_OVER | AW_MMC_INT_AUTO_STOP_DONE);
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/* Enable interrupts and AHB access. */
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AW_MMC_WRITE_4(sc, AW_MMC_GCTL,
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AW_MMC_READ_4(sc, AW_MMC_GCTL) | AW_MMC_CTRL_INT_ENB);
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@ -655,7 +675,7 @@ aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
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int blksz;
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struct aw_mmc_softc *sc;
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struct mmc_command *cmd;
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uint32_t cmdreg;
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uint32_t cmdreg, imask;
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int err;
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sc = device_get_softc(bus);
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@ -664,11 +684,19 @@ aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
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AW_MMC_UNLOCK(sc);
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return (EBUSY);
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}
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sc->aw_req = req;
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cmd = req->cmd;
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cmdreg = AW_MMC_CMDR_LOAD;
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imask = AW_MMC_INT_ERR_BIT;
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sc->aw_intr_wait = 0;
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sc->aw_intr = 0;
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sc->aw_resid = 0;
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cmd->error = MMC_ERR_NONE;
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if (cmd->opcode == MMC_GO_IDLE_STATE)
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cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ;
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if (cmd->flags & MMC_RSP_PRESENT)
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cmdreg |= AW_MMC_CMDR_RESP_RCV;
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if (cmd->flags & MMC_RSP_136)
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@ -676,30 +704,52 @@ aw_mmc_request(device_t bus, device_t child, struct mmc_request *req)
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if (cmd->flags & MMC_RSP_CRC)
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cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC;
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sc->aw_intr = 0;
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sc->aw_resid = 0;
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sc->aw_intr_wait = AW_MMC_INT_CMD_DONE;
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cmd->error = MMC_ERR_NONE;
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if (cmd->data != NULL) {
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sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
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if (cmd->data) {
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cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER;
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if (cmd->data->flags & MMC_DATA_MULTI) {
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cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG;
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imask |= AW_MMC_INT_AUTO_STOP_DONE;
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sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE;
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} else {
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sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER;
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imask |= AW_MMC_INT_DATA_OVER;
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}
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if (cmd->data->flags & MMC_DATA_WRITE)
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cmdreg |= AW_MMC_CMDR_DIR_WRITE;
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blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
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AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz);
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AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len);
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} else {
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imask |= AW_MMC_INT_CMD_DONE;
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}
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/* Enable the interrupts we are interested in */
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AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask);
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AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff);
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/* Enable auto stop if needed */
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AW_MMC_WRITE_4(sc, AW_MMC_A12A,
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cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff);
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/* Write the command argument */
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AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
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/*
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* If we don't have data start the request
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* if we do prepare the dma request and start the request
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*/
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if (cmd->data == NULL) {
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AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
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} else {
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err = aw_mmc_prepare_dma(sc);
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if (err != 0)
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device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err);
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AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
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}
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AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg);
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AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode);
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callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz,
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aw_mmc_timeout, sc);
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AW_MMC_UNLOCK(sc);
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@ -914,16 +964,20 @@ aw_mmc_update_ios(device_t bus, device_t child)
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break;
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}
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/* Set the voltage */
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if (ios->power_mode == power_off) {
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switch (ios->power_mode) {
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case power_on:
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break;
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case power_off:
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if (bootverbose)
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device_printf(sc->aw_dev, "Powering down sd/mmc\n");
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if (sc->aw_reg_vmmc)
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regulator_disable(sc->aw_reg_vmmc);
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if (sc->aw_reg_vqmmc)
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regulator_disable(sc->aw_reg_vqmmc);
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} else if (sc->aw_vdd != ios->vdd)
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aw_mmc_set_power(sc, ios->vdd);
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aw_mmc_reset(sc);
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break;
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case power_up:
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if (bootverbose)
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device_printf(sc->aw_dev, "Powering up sd/mmc\n");
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aw_mmc_init(sc);
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break;
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};
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/* Enable ddr mode if needed */
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reg = AW_MMC_READ_4(sc, AW_MMC_GCTL);
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@ -47,6 +47,7 @@
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#define AW_MMC_STAR 0x3C /* Status Register */
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#define AW_MMC_FWLR 0x40 /* FIFO Threshold Watermark Register */
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#define AW_MMC_FUNS 0x44 /* Function Select Register */
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#define AW_MMC_DBGC 0x50 /* Debug register */
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#define AW_MMC_CSDC 0x54 /* CRC status detect controler register (A64 smhc2 only) */
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#define AW_MMC_A12A 0x58 /* Auto command 12 argument register */
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#define AW_MMC_NTSR 0x5C /* SD new timing register (H3, A64 smhc0/1 only) */
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