Import DTS from Linux 5.8
This commit is contained in:
Emmanuel Vadot
parent
5df7ea339a
commit
2554fe8f89
@ -1,5 +1,8 @@
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.. SPDX-License-Identifier: GPL-2.0
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Devicetree (DT) ABI
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===================
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Devicetree (DT) ABI
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===================
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I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit
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summary document:
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@ -2,13 +2,20 @@
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DT_DOC_CHECKER ?= dt-doc-validate
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DT_EXTRACT_EX ?= dt-extract-example
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DT_MK_SCHEMA ?= dt-mk-schema
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DT_MK_SCHEMA_USERONLY_FLAG := $(if $(DT_SCHEMA_FILES), -u)
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DT_SCHEMA_MIN_VERSION = 2020.5
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PHONY += check_dtschema_version
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check_dtschema_version:
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@{ echo $(DT_SCHEMA_MIN_VERSION); \
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$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
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{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
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quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
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cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
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$(DT_EXTRACT_EX) $< > $@
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$(obj)/%.example.dts: $(src)/%.yaml FORCE
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$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
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$(call if_changed,chk_binding)
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# Use full schemas when checking %.example.dts
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@ -27,21 +34,40 @@ quiet_cmd_mk_schema = SCHEMA $@
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DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
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DT_SCHEMA_FILES ?= $(DT_DOCS)
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override DTC_FLAGS := \
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-Wno-avoid_unnecessary_addr_size \
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-Wno-graph_child_address \
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-Wno-interrupt_provider
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$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE
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$(call if_changed,mk_schema)
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ifeq ($(DT_SCHEMA_FILES),)
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# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
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# Just copy processed-schema-examples.yaml
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$(obj)/processed-schema.yaml: $(obj)/processed-schema-examples.yaml FORCE
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$(call if_changed,copy)
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DT_SCHEMA_FILES = $(DT_DOCS)
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else
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# If DT_SCHEMA_FILES is specified, use it for processed-schema.yaml
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$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u
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$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
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$(call if_changed,mk_schema)
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endif
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extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
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extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
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extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
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extra-$(CHECK_DTBS) += processed-schema.yaml
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override DTC_FLAGS := \
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-Wno-avoid_unnecessary_addr_size \
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-Wno-graph_child_address
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$(obj)/processed-schema-examples.yaml: $(DT_DOCS) FORCE
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$(call if_changed,mk_schema)
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$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := $(DT_MK_SCHEMA_USERONLY_FLAG)
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$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) FORCE
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$(call if_changed,mk_schema)
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extra-y += processed-schema.yaml
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# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
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# build artifacts here before they are processed by scripts/Makefile.clean
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clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
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-name '*.example.dt.yaml' \) -delete 2>/dev/null)
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@ -13,8 +13,8 @@ properties:
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compatible:
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items:
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- enum:
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- altr,socfpga-cyclone5
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- altr,socfpga-arria5
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- altr,socfpga-arria10
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- altr,socfpga-cyclone5
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- altr,socfpga-arria5
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- altr,socfpga-arria10
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- const: altr,socfpga
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...
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@ -17,7 +17,7 @@ description: |+
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any time. Be sure to use a device tree binary and a kernel image
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generated from the same source tree.
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Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
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Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
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stable binding/ABI.
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properties:
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@ -107,6 +107,7 @@ properties:
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- amlogic,p231
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- libretech,aml-s905d-pc
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- phicomm,n1
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- smartlabs,sml5442tw
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- const: amlogic,s905d
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- const: amlogic,meson-gxl
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@ -148,6 +149,8 @@ properties:
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- description: Boards with the Amlogic Meson G12B S922X SoC
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items:
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- enum:
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- azw,gtking
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- azw,gtking-pro
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- hardkernel,odroid-n2
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- khadas,vim3
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- ugoos,am6
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@ -159,6 +162,7 @@ properties:
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- enum:
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- seirobotics,sei610
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- khadas,vim3l
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- hardkernel,odroid-c4
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- const: amlogic,sm1
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- description: Boards with the Amlogic Meson A1 A113L SoC
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@ -25,7 +25,7 @@ select:
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properties:
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compatible:
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items:
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items:
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- const: amlogic,meson-gx-ao-secure
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- const: syscon
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@ -14,7 +14,7 @@ Required properties:
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The scmi node with the following properties shall be under the /firmware/ node.
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- compatible : shall be "arm,scmi"
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- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
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- mboxes: List of phandle and mailbox channel specifiers. It should contain
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exactly one or two mailboxes, one for transmitting messages("tx")
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and another optional for receiving the notifications("rx") if
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@ -25,6 +25,7 @@ The scmi node with the following properties shall be under the /firmware/ node.
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protocol identifier for a given sub-node.
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- #size-cells : should be '0' as 'reg' property doesn't have any size
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associated with it.
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- arm,smc-id : SMC id required when using smc or hvc transports
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Optional properties:
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@ -131,26 +131,23 @@ properties:
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property, describing the physical location of the children nodes.
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0 means motherboard site, while 1 and 2 are daughterboard sites, and
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0xf means "sisterboard" which is the site containing the main CPU tile.
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/uint32'
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- minimum: 0
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maximum: 15
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 15
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arm,vexpress,position:
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description: When daughterboards are stacked on one site, their position
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in the stack be be described this attribute.
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/uint32'
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- minimum: 0
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maximum: 3
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 3
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arm,vexpress,dcc:
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description: When describing tiles consisting of more than one DCC, its
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number can be specified with this attribute.
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/uint32'
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- minimum: 0
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maximum: 3
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$ref: '/schemas/types.yaml#/definitions/uint32'
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minimum: 0
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maximum: 3
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patternProperties:
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"^bus@[0-9a-f]+$":
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@ -162,8 +159,7 @@ patternProperties:
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"simple-bus". If the compatible is placed in the "motherboard" node,
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it is stricter and always has two compatibles.
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type: object
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allOf:
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- $ref: '/schemas/simple-bus.yaml'
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$ref: '/schemas/simple-bus.yaml'
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properties:
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compatible:
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@ -195,11 +191,11 @@ patternProperties:
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- const: simple-bus
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arm,v2m-memory-map:
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description: This describes the memory map type.
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/string'
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- enum:
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- rs1
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- rs2
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$ref: '/schemas/types.yaml#/definitions/string'
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enum:
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- rs1
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- rs2
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required:
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- compatible
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required:
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@ -82,6 +82,13 @@ properties:
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: Microchip SAMA5D2 Industrial Connectivity Platform
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items:
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- const: microchip,sama5d2-icp
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- const: atmel,sama5d27
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- const: atmel,sama5d2
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- const: atmel,sama5
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- description: SAM9X60-EK board
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items:
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- const: microchip,sam9x60ek
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@ -13,6 +13,6 @@ properties:
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compatible:
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items:
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- enum:
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- bitmain,sophon-edge
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- bitmain,sophon-edge
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- const: bitmain,bm1880
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...
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49
Bindings/arm/calxeda/hb-sregs.yaml
Normal file
49
Bindings/arm/calxeda/hb-sregs.yaml
Normal file
@ -0,0 +1,49 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Calxeda Highbank system registers
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description: |
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The Calxeda Highbank system has a block of MMIO registers controlling
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several generic system aspects. Those can be used to control some power
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management, they also contain some gate and PLL clocks.
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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properties:
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compatible:
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const: calxeda,hb-sregs
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reg:
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maxItems: 1
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clocks:
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type: object
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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sregs@fff3c000 {
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compatible = "calxeda,hb-sregs";
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reg = <0xfff3c000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333000>;
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};
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};
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};
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@ -1,15 +0,0 @@
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Calxeda Highbank L2 cache ECC
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Properties:
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- compatible : Should be "calxeda,hb-sregs-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt.
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Example:
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4 0 72 4>;
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};
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42
Bindings/arm/calxeda/l2ecc.yaml
Normal file
42
Bindings/arm/calxeda/l2ecc.yaml
Normal file
@ -0,0 +1,42 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Calxeda Highbank L2 cache ECC
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description: |
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Binding for the Calxeda Highbank L2 cache controller ECC device.
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This does not cover the actual L2 cache controller control registers,
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but just the error reporting functionality.
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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properties:
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compatible:
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const: "calxeda,hb-sregs-l2-ecc"
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: single bit error interrupt
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- description: double bit error interrupt
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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sregs@fff3c200 {
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compatible = "calxeda,hb-sregs-l2-ecc";
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reg = <0xfff3c200 0x100>;
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interrupts = <0 71 4>, <0 72 4>;
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};
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@ -140,16 +140,14 @@ patternProperties:
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maxItems: 1
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arm,trig-in-sigs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of CTI trigger in signal numbers in use by a trig-conns node.
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arm,trig-in-types:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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@ -159,16 +157,14 @@ patternProperties:
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completely, then the types will default to GEN_IO.
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arm,trig-out-sigs:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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List of CTI trigger out signal numbers in use by a trig-conns node.
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arm,trig-out-types:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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@ -178,8 +174,7 @@ patternProperties:
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or omitted completely, then the types will default to GEN_IO.
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arm,trig-filters:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32-array
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 32
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description:
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@ -187,8 +182,7 @@ patternProperties:
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active, unless filtering is disabled on the driver.
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arm,trig-conn-name:
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allOf:
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- $ref: /schemas/types.yaml#/definitions/string
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$ref: /schemas/types.yaml#/definitions/string
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description:
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Defines a connection name that will be displayed, if the cpu or
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arm,cs-dev-assoc properties are not being used in this connection.
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@ -301,7 +295,7 @@ examples:
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- |
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cti@20110000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0 0x20110000 0 0x1000>;
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reg = <0x20110000 0x1000>;
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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@ -167,53 +167,53 @@ properties:
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- qcom,kryo260
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- qcom,kryo280
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- qcom,kryo385
|
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- qcom,kryo468
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- qcom,kryo485
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- qcom,scorpion
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enable-method:
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allOf:
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- $ref: '/schemas/types.yaml#/definitions/string'
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- oneOf:
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# On ARM v8 64-bit this property is required
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- enum:
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- psci
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- spin-table
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# On ARM 32-bit systems this property is optional
|
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- enum:
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- actions,s500-smp
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- allwinner,sun6i-a31
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- allwinner,sun8i-a23
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- allwinner,sun9i-a80-smp
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- allwinner,sun8i-a83t-smp
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- amlogic,meson8-smp
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- amlogic,meson8b-smp
|
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- arm,realview-smp
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- aspeed,ast2600-smp
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- brcm,bcm11351-cpu-method
|
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- brcm,bcm23550
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- brcm,bcm2836-smp
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- brcm,bcm63138
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- brcm,bcm-nsp-smp
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- brcm,brahma-b15
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- marvell,armada-375-smp
|
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- marvell,armada-380-smp
|
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- marvell,armada-390-smp
|
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- marvell,armada-xp-smp
|
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- marvell,98dx3236-smp
|
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- marvell,mmp3-smp
|
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- mediatek,mt6589-smp
|
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- mediatek,mt81xx-tz-smp
|
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- qcom,gcc-msm8660
|
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- qcom,kpss-acc-v1
|
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- qcom,kpss-acc-v2
|
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- renesas,apmu
|
||||
- renesas,r9a06g032-smp
|
||||
- rockchip,rk3036-smp
|
||||
- rockchip,rk3066-smp
|
||||
- socionext,milbeaut-m10v-smp
|
||||
- ste,dbx500-smp
|
||||
- ti,am3352
|
||||
- ti,am4372
|
||||
$ref: '/schemas/types.yaml#/definitions/string'
|
||||
oneOf:
|
||||
# On ARM v8 64-bit this property is required
|
||||
- enum:
|
||||
- psci
|
||||
- spin-table
|
||||
# On ARM 32-bit systems this property is optional
|
||||
- enum:
|
||||
- actions,s500-smp
|
||||
- allwinner,sun6i-a31
|
||||
- allwinner,sun8i-a23
|
||||
- allwinner,sun9i-a80-smp
|
||||
- allwinner,sun8i-a83t-smp
|
||||
- amlogic,meson8-smp
|
||||
- amlogic,meson8b-smp
|
||||
- arm,realview-smp
|
||||
- aspeed,ast2600-smp
|
||||
- brcm,bcm11351-cpu-method
|
||||
- brcm,bcm23550
|
||||
- brcm,bcm2836-smp
|
||||
- brcm,bcm63138
|
||||
- brcm,bcm-nsp-smp
|
||||
- brcm,brahma-b15
|
||||
- marvell,armada-375-smp
|
||||
- marvell,armada-380-smp
|
||||
- marvell,armada-390-smp
|
||||
- marvell,armada-xp-smp
|
||||
- marvell,98dx3236-smp
|
||||
- marvell,mmp3-smp
|
||||
- mediatek,mt6589-smp
|
||||
- mediatek,mt81xx-tz-smp
|
||||
- qcom,gcc-msm8660
|
||||
- qcom,kpss-acc-v1
|
||||
- qcom,kpss-acc-v2
|
||||
- renesas,apmu
|
||||
- renesas,r9a06g032-smp
|
||||
- rockchip,rk3036-smp
|
||||
- rockchip,rk3066-smp
|
||||
- socionext,milbeaut-m10v-smp
|
||||
- ste,dbx500-smp
|
||||
- ti,am3352
|
||||
- ti,am4372
|
||||
|
||||
cpu-release-addr:
|
||||
$ref: '/schemas/types.yaml#/definitions/uint64'
|
||||
|
||||
@ -47,7 +47,7 @@ Required properties:
|
||||
&lsio_mu1 1 2
|
||||
&lsio_mu1 1 3
|
||||
&lsio_mu1 3 3>;
|
||||
See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
|
||||
See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
|
||||
for detailed mailbox binding.
|
||||
|
||||
Note: Each mu which supports general interrupt should have an alias correctly
|
||||
@ -108,7 +108,8 @@ This binding uses the i.MX common pinctrl binding[3].
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qm-iomuxc",
|
||||
"fsl,imx8qxp-iomuxc".
|
||||
"fsl,imx8qxp-iomuxc",
|
||||
"fsl,imx8dxl-iomuxc".
|
||||
|
||||
Required properties for Pinctrl sub nodes:
|
||||
- fsl,pins: Each entry consists of 3 integers which represents
|
||||
@ -116,7 +117,8 @@ Required properties for Pinctrl sub nodes:
|
||||
integers <pin_id mux_mode> are specified using a
|
||||
PIN_FUNC_ID macro, which can be found in
|
||||
<dt-bindings/pinctrl/pads-imx8qm.h>,
|
||||
<dt-bindings/pinctrl/pads-imx8qxp.h>.
|
||||
<dt-bindings/pinctrl/pads-imx8qxp.h>,
|
||||
<dt-bindings/pinctrl/pads-imx8dxl.h>.
|
||||
The last integer CONFIG is the pad setting value like
|
||||
pull-up on this pin.
|
||||
|
||||
|
||||
@ -119,6 +119,7 @@ properties:
|
||||
- fsl,imx6q-sabreauto
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
|
||||
@ -170,6 +171,7 @@ properties:
|
||||
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
@ -177,7 +179,9 @@ properties:
|
||||
- technologic,imx6dl-ts4900
|
||||
- technologic,imx6dl-ts7970
|
||||
- toradex,colibri_imx6dl # Colibri iMX6 Module
|
||||
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
|
||||
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
|
||||
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3
|
||||
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
|
||||
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
|
||||
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
|
||||
|
||||
@ -70,43 +70,39 @@ properties:
|
||||
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Minimum valid values are 1. Controllers
|
||||
without setup latency control should use a value of 0.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,tag-latency:
|
||||
description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
|
||||
read, write and setup latencies. Controllers without setup latency control
|
||||
should use 0. Controllers without separate read and write Tag RAM latency
|
||||
values should only use the first cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
arm,dirty-latency:
|
||||
description: Cycles of latency for Dirty RAMs. This is a single cell.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
maximum: 8
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 8
|
||||
|
||||
arm,filter-ranges:
|
||||
description: <start length> Starting address and length of window to
|
||||
filter. Addresses in the filter window are directed to the M1 port. Other
|
||||
addresses will go to the M0 port.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
arm,io-coherent:
|
||||
description: indicates that the system is operating in an hardware
|
||||
@ -131,36 +127,31 @@ properties:
|
||||
arm,double-linefill:
|
||||
description: Override double linefill enable setting. Enable if
|
||||
non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-incr:
|
||||
description: Override double linefill on INCR read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,double-linefill-wrap:
|
||||
description: Override double linefill on WRAP read. Enable
|
||||
if non-zero, disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-drop:
|
||||
description: Override prefetch drop enable setting. Enable if non-zero,
|
||||
disable if zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,prefetch-offset:
|
||||
description: Override prefetch offset value.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
|
||||
|
||||
arm,shared-override:
|
||||
description: The default behavior of the L220 or PL310 cache
|
||||
@ -193,35 +184,31 @@ properties:
|
||||
description: |
|
||||
Data prefetch. Value: <0> (forcibly disable), <1>
|
||||
(forcibly enable), property absent (retain settings set by firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
prefetch-instr:
|
||||
description: |
|
||||
Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,dynamic-clock-gating:
|
||||
description: |
|
||||
L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,standby-mode:
|
||||
description: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferably retain firmware settings)
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1]
|
||||
|
||||
arm,early-bresp-disable:
|
||||
description: Disable the CA9 optimization Early BRESP (PL310)
|
||||
|
||||
@ -84,6 +84,28 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8135-evbp1
|
||||
- const: mediatek,mt8135
|
||||
- description: Google Elm (Acer Chromebook R13)
|
||||
items:
|
||||
- const: google,elm-rev8
|
||||
- const: google,elm-rev7
|
||||
- const: google,elm-rev6
|
||||
- const: google,elm-rev5
|
||||
- const: google,elm-rev4
|
||||
- const: google,elm-rev3
|
||||
- const: google,elm
|
||||
- const: mediatek,mt8173
|
||||
- description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...)
|
||||
items:
|
||||
- const: google,hana-rev6
|
||||
- const: google,hana-rev5
|
||||
- const: google,hana-rev4
|
||||
- const: google,hana-rev3
|
||||
- const: google,hana
|
||||
- const: mediatek,mt8173
|
||||
- description: Google Hana rev7 (Poin2 Chromebook 11C)
|
||||
items:
|
||||
- const: google,hana-rev7
|
||||
- const: mediatek,mt8173
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8173-evb
|
||||
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-apmixedsys"
|
||||
- "mediatek,mt2712-apmixedsys", "syscon"
|
||||
- "mediatek,mt6765-apmixedsys", "syscon"
|
||||
- "mediatek,mt6779-apmixedsys", "syscon"
|
||||
- "mediatek,mt6797-apmixedsys"
|
||||
- "mediatek,mt7622-apmixedsys"
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-audsys", "syscon"
|
||||
- "mediatek,mt6765-audsys", "syscon"
|
||||
- "mediatek,mt6779-audio", "syscon"
|
||||
- "mediatek,mt7622-audsys", "syscon"
|
||||
- "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
|
||||
|
||||
@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-camsys", "syscon"
|
||||
- "mediatek,mt6779-camsys", "syscon"
|
||||
- "mediatek,mt8183-camsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-imgsys", "syscon"
|
||||
- "mediatek,mt2712-imgsys", "syscon"
|
||||
- "mediatek,mt6765-imgsys", "syscon"
|
||||
- "mediatek,mt6779-imgsys", "syscon"
|
||||
- "mediatek,mt6797-imgsys", "syscon"
|
||||
- "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
|
||||
|
||||
@ -9,6 +9,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-infracfg", "syscon"
|
||||
- "mediatek,mt2712-infracfg", "syscon"
|
||||
- "mediatek,mt6765-infracfg", "syscon"
|
||||
- "mediatek,mt6779-infracfg_ao", "syscon"
|
||||
- "mediatek,mt6797-infracfg", "syscon"
|
||||
- "mediatek,mt7622-infracfg", "syscon"
|
||||
|
||||
28
Bindings/arm/mediatek/mediatek,mipi0a.txt
Normal file
28
Bindings/arm/mediatek/mediatek,mipi0a.txt
Normal file
@ -0,0 +1,28 @@
|
||||
Mediatek mipi0a (mipi_rx_ana_csi0a) controller
|
||||
============================
|
||||
|
||||
The Mediatek mipi0a controller provides various clocks
|
||||
to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-mipi0a", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mipi0a controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The mipi0a controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
mipi0a: clock-controller@11c10000 {
|
||||
compatible = "mediatek,mt6765-mipi0a", "syscon";
|
||||
reg = <0 0x11c10000 0 0x1000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,13 +1,15 @@
|
||||
Mediatek mmsys controller
|
||||
============================
|
||||
|
||||
The Mediatek mmsys controller provides various clocks to the system.
|
||||
The Mediatek mmsys system controller provides clock control, routing control,
|
||||
and miscellaneous control in mmsys partition.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-mmsys", "syscon"
|
||||
- "mediatek,mt2712-mmsys", "syscon"
|
||||
- "mediatek,mt6765-mmsys", "syscon"
|
||||
- "mediatek,mt6779-mmsys", "syscon"
|
||||
- "mediatek,mt6797-mmsys", "syscon"
|
||||
- "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
|
||||
@ -15,13 +17,13 @@ Required Properties:
|
||||
- "mediatek,mt8183-mmsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The mmsys controller uses the common clk binding from
|
||||
For the clock control, the mmsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
Example:
|
||||
|
||||
mmsys: clock-controller@14000000 {
|
||||
mmsys: syscon@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
@ -1,36 +0,0 @@
|
||||
Mediatek pericfg controller
|
||||
===========================
|
||||
|
||||
The Mediatek pericfg controller provides various clocks and reset
|
||||
outputs to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt2712-pericfg", "syscon"
|
||||
- "mediatek,mt7622-pericfg", "syscon"
|
||||
- "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"
|
||||
- "mediatek,mt7629-pericfg", "syscon"
|
||||
- "mediatek,mt8135-pericfg", "syscon"
|
||||
- "mediatek,mt8173-pericfg", "syscon"
|
||||
- "mediatek,mt8183-pericfg", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
- #reset-cells: Must be 1
|
||||
|
||||
The pericfg controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
Also it uses the common reset controller binding from
|
||||
Documentation/devicetree/bindings/reset/reset.txt.
|
||||
The available reset outputs are defined in
|
||||
dt-bindings/reset/mt*-resets.h
|
||||
|
||||
Example:
|
||||
|
||||
pericfg: power-controller@10003000 {
|
||||
compatible = "mediatek,mt8173-pericfg", "syscon";
|
||||
reg = <0 0x10003000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
65
Bindings/arm/mediatek/mediatek,pericfg.yaml
Normal file
65
Bindings/arm/mediatek/mediatek,pericfg.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Peripheral Configuration Controller
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
||||
|
||||
description:
|
||||
The Mediatek pericfg controller provides various clocks and reset outputs
|
||||
to the system.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2701-pericfg
|
||||
- mediatek,mt2712-pericfg
|
||||
- mediatek,mt6765-pericfg
|
||||
- mediatek,mt7622-pericfg
|
||||
- mediatek,mt7629-pericfg
|
||||
- mediatek,mt8135-pericfg
|
||||
- mediatek,mt8173-pericfg
|
||||
- mediatek,mt8183-pericfg
|
||||
- mediatek,mt8516-pericfg
|
||||
- const: syscon
|
||||
- items:
|
||||
# Special case for mt7623 for backward compatibility
|
||||
- const: mediatek,mt7623-pericfg
|
||||
- const: mediatek,mt2701-pericfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
pericfg@10003000 {
|
||||
compatible = "mediatek,mt8173-pericfg", "syscon";
|
||||
reg = <0x10003000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
pericfg@10003000 {
|
||||
compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
|
||||
reg = <0x10003000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -8,6 +8,7 @@ Required Properties:
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt2701-topckgen"
|
||||
- "mediatek,mt2712-topckgen", "syscon"
|
||||
- "mediatek,mt6765-topckgen", "syscon"
|
||||
- "mediatek,mt6779-topckgen", "syscon"
|
||||
- "mediatek,mt6797-topckgen"
|
||||
- "mediatek,mt7622-topckgen"
|
||||
|
||||
27
Bindings/arm/mediatek/mediatek,vcodecsys.txt
Normal file
27
Bindings/arm/mediatek/mediatek,vcodecsys.txt
Normal file
@ -0,0 +1,27 @@
|
||||
Mediatek vcodecsys controller
|
||||
============================
|
||||
|
||||
The Mediatek vcodecsys controller provides various clocks to the system.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: Should be one of:
|
||||
- "mediatek,mt6765-vcodecsys", "syscon"
|
||||
- #clock-cells: Must be 1
|
||||
|
||||
The vcodecsys controller uses the common clk binding from
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
|
||||
The vcodecsys controller also uses the common power domain from
|
||||
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||
The available power doamins are defined in dt-bindings/power/mt*-power.h.
|
||||
|
||||
Example:
|
||||
|
||||
venc_gcon: clock-controller@17000000 {
|
||||
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
||||
reg = <0 0x17000000 0 0x10000>;
|
||||
power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -17,9 +17,8 @@ properties:
|
||||
- nxp,lpc3230
|
||||
- nxp,lpc3240
|
||||
- items:
|
||||
- enum:
|
||||
- ea,ea3250
|
||||
- phytec,phy3250
|
||||
- const: nxp,lpc3250
|
||||
|
||||
- enum:
|
||||
- ea,ea3250
|
||||
- phytec,phy3250
|
||||
- const: nxp,lpc3250
|
||||
...
|
||||
|
||||
@ -69,13 +69,11 @@ properties:
|
||||
|
||||
method:
|
||||
description: The method of calling the PSCI firmware.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/string-array
|
||||
- enum:
|
||||
# SMC #0, with the register assignments specified in this binding.
|
||||
- smc
|
||||
# HVC #0, with the register assignments specified in this binding.
|
||||
- hvc
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
enum:
|
||||
- smc
|
||||
# HVC #0, with the register assignments specified in this binding.
|
||||
- hvc
|
||||
|
||||
cpu_suspend:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
@ -107,8 +105,8 @@ properties:
|
||||
|
||||
patternProperties:
|
||||
"^power-domain-":
|
||||
allOf:
|
||||
- $ref: "../power/power-domain.yaml#"
|
||||
$ref: "../power/power-domain.yaml#"
|
||||
|
||||
type: object
|
||||
description: |
|
||||
ARM systems can have multiple cores, sometimes in an hierarchical
|
||||
|
||||
@ -37,6 +37,8 @@ description: |
|
||||
msm8994
|
||||
msm8996
|
||||
sc7180
|
||||
sdm630
|
||||
sdm660
|
||||
sdm845
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
@ -153,6 +155,11 @@ properties:
|
||||
- qcom,sc7180-idp
|
||||
- const: qcom,sc7180
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- xiaomi,lavender
|
||||
- const: qcom,sdm660
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq6018-cp01-c1
|
||||
|
||||
@ -14,6 +14,13 @@ properties:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
# RTD1195 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- mele,x1000 # MeLE X1000
|
||||
- realtek,horseradish # Realtek Horseradish EVB
|
||||
- const: realtek,rtd1195
|
||||
|
||||
# RTD1293 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
@ -25,6 +32,7 @@ properties:
|
||||
- enum:
|
||||
- mele,v9 # MeLE V9
|
||||
- probox2,ava # ProBox2 AVA
|
||||
- xnano,x5 # Xnano X5
|
||||
- zidoo,x9s # Zidoo X9S
|
||||
- const: realtek,rtd1295
|
||||
|
||||
@ -33,4 +41,17 @@ properties:
|
||||
- enum:
|
||||
- synology,ds418 # Synology DiskStation DS418
|
||||
- const: realtek,rtd1296
|
||||
|
||||
# RTD1395 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- bananapi,bpi-m4 # Banana Pi BPI-M4
|
||||
- realtek,lion-skin # Realtek Lion Skin EVB
|
||||
- const: realtek,rtd1395
|
||||
|
||||
# RTD1619 SoC based boards
|
||||
- items:
|
||||
- enum:
|
||||
- realtek,mjolnir # Realtek Mjolnir EVB
|
||||
- const: realtek,rtd1619
|
||||
...
|
||||
|
||||
@ -33,5 +33,5 @@ examples:
|
||||
- |
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
reg = <0xff000044 4>;
|
||||
};
|
||||
|
||||
@ -54,6 +54,16 @@ properties:
|
||||
|
||||
- description: RZ/G1H (R8A77420)
|
||||
items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven)
|
||||
- iwave,g21m
|
||||
- const: renesas,r8a7742
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
# iWave Systems RZ/G1H Qseven Development Platform (iW-RainboW-G21D-Qseven)
|
||||
- iwave,g21d
|
||||
- const: iwave,g21m
|
||||
- const: renesas,r8a7742
|
||||
|
||||
- description: RZ/G1M (R8A77430)
|
||||
|
||||
@ -358,6 +358,11 @@ properties:
|
||||
- const: haoyu,marsboard-rk3066
|
||||
- const: rockchip,rk3066a
|
||||
|
||||
- description: Hardkernel Odroid Go Advance
|
||||
items:
|
||||
- const: hardkernel,rk3326-odroid-go2
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Hugsun X99 TV Box
|
||||
items:
|
||||
- const: hugsun,x99
|
||||
|
||||
@ -22,9 +22,8 @@ properties:
|
||||
Adaptive Supply Voltage bin selection. This can be used
|
||||
to determine the ASV bin of an SoC if respective information
|
||||
is missing in the CHIPID registers or in the OTP memory.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [ 0, 1, 2, 3 ]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@ -52,6 +52,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- insignal,origen # Insignal Origen
|
||||
- samsung,i9100 # Samsung Galaxy S2 (GT-I9100)
|
||||
- samsung,smdkv310 # Samsung SMDKV310 eval
|
||||
- samsung,trats # Samsung Tizen Reference
|
||||
- samsung,universal_c210 # Samsung C210
|
||||
|
||||
@ -17,45 +17,46 @@ properties:
|
||||
- description: LD4 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld4-ref
|
||||
- socionext,uniphier-ld4-ref
|
||||
- const: socionext,uniphier-ld4
|
||||
- description: Pro4 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pro4-ace
|
||||
- socionext,uniphier-pro4-ref
|
||||
- socionext,uniphier-pro4-sanji
|
||||
- socionext,uniphier-pro4-ace
|
||||
- socionext,uniphier-pro4-ref
|
||||
- socionext,uniphier-pro4-sanji
|
||||
- const: socionext,uniphier-pro4
|
||||
- description: sLD8 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-sld8-ref
|
||||
- socionext,uniphier-sld8-ref
|
||||
- const: socionext,uniphier-sld8
|
||||
- description: PXs2 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pxs2-gentil
|
||||
- socionext,uniphier-pxs2-vodka
|
||||
- socionext,uniphier-pxs2-gentil
|
||||
- socionext,uniphier-pxs2-vodka
|
||||
- const: socionext,uniphier-pxs2
|
||||
- description: LD6b SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld6b-ref
|
||||
- socionext,uniphier-ld6b-ref
|
||||
- const: socionext,uniphier-ld6b
|
||||
- description: LD11 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld11-global
|
||||
- socionext,uniphier-ld11-ref
|
||||
- socionext,uniphier-ld11-global
|
||||
- socionext,uniphier-ld11-ref
|
||||
- const: socionext,uniphier-ld11
|
||||
- description: LD20 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-ld20-global
|
||||
- socionext,uniphier-ld20-ref
|
||||
- socionext,uniphier-ld20-akebi96
|
||||
- socionext,uniphier-ld20-global
|
||||
- socionext,uniphier-ld20-ref
|
||||
- const: socionext,uniphier-ld20
|
||||
- description: PXs3 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pxs3-ref
|
||||
- socionext,uniphier-pxs3-ref
|
||||
- const: socionext,uniphier-pxs3
|
||||
|
||||
@ -20,7 +20,7 @@ description: |
|
||||
[2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/simple-bus.yaml#
|
||||
- $ref: /schemas/simple-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@ -14,9 +14,9 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32mp157-syscfg
|
||||
- const: syscon
|
||||
- enum:
|
||||
- st,stm32mp157-syscfg
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -38,6 +38,9 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- arrow,stm32mp157a-avenger96 # Avenger96
|
||||
- lxa,stm32mp157c-mc1
|
||||
- shiratech,stm32mp157a-iot-box # IoT Box
|
||||
- shiratech,stm32mp157a-stinger96 # Stinger96
|
||||
- st,stm32mp157c-ed1
|
||||
- st,stm32mp157a-dk1
|
||||
- st,stm32mp157c-dk2
|
||||
|
||||
@ -561,6 +561,11 @@ properties:
|
||||
- const: olimex,a20-olinuxino-lime
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino LIME (with eMMC)
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-lime-emmc
|
||||
- const: allwinner,sun7i-a20
|
||||
|
||||
- description: Olimex A20-OlinuXino LIME2
|
||||
items:
|
||||
- const: olimex,a20-olinuxino-lime2
|
||||
|
||||
@ -13,7 +13,7 @@ considered "unstable". Any Marvell Berlin device tree binding may change at any
|
||||
time. Be sure to use a device tree binary and a kernel image generated from the
|
||||
same source tree.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a
|
||||
Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a
|
||||
stable binding/ABI.
|
||||
|
||||
---------------------------------------------------------------
|
||||
|
||||
@ -85,9 +85,8 @@ properties:
|
||||
CPU power good signal from external PMIC to PMC is enabled.
|
||||
|
||||
nvidia,suspend-mode:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- enum: [0, 1, 2]
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2]
|
||||
description:
|
||||
The suspend mode that the platform should use.
|
||||
Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
|
||||
@ -323,7 +322,7 @@ examples:
|
||||
|
||||
tegra_pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
#clock-cells = <1>;
|
||||
|
||||
@ -26,8 +26,8 @@ properties:
|
||||
oneOf:
|
||||
- const: faraday,ftide010
|
||||
- items:
|
||||
- const: cortina,gemini-pata
|
||||
- const: faraday,ftide010
|
||||
- const: cortina,gemini-pata
|
||||
- const: faraday,ftide010
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -17,6 +17,7 @@ properties:
|
||||
- renesas,sata-r8a7779 # R-Car H1
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,sata-r8a7742 # RZ/G1H
|
||||
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
|
||||
- renesas,sata-r8a7790 # R-Car H2 other than ES1
|
||||
- renesas,sata-r8a7791 # R-Car M2-W
|
||||
|
||||
@ -1,44 +0,0 @@
|
||||
* Calxeda AHCI SATA Controller
|
||||
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
The Calxeda SATA controller mostly conforms to the AHCI interface
|
||||
with some special extensions to add functionality.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "calxeda,hb-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
|
||||
SATA port to a combophy and a lane within that
|
||||
combophy
|
||||
- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
|
||||
which indicates that the driver supports SGPIO
|
||||
indicator lights using the indicated GPIOs
|
||||
- calxeda,led-order : a u32 array that map port numbers to offsets within the
|
||||
SGPIO bitstream.
|
||||
- calxeda,tx-atten : a u32 array that contains TX attenuation override
|
||||
codes, one per port. The upper 3 bytes are always
|
||||
0 and thus ignored.
|
||||
- calxeda,pre-clocks : a u32 that indicates the number of additional clock
|
||||
cycles to transmit before sending an SGPIO pattern
|
||||
- calxeda,post-clocks: a u32 that indicates the number of additional clock
|
||||
cycles to transmit after sending an SGPIO pattern
|
||||
|
||||
Example:
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
dma-coherent;
|
||||
calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
|
||||
&combophy0 2 &combophy0 3>;
|
||||
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
|
||||
calxeda,led-order = <4 0 1 2 3>;
|
||||
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
|
||||
calxeda,pre-clocks = <10>;
|
||||
calxeda,post-clocks = <0>;
|
||||
};
|
||||
92
Bindings/ata/sata_highbank.yaml
Normal file
92
Bindings/ata/sata_highbank.yaml
Normal file
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Calxeda AHCI SATA Controller
|
||||
|
||||
description: |
|
||||
The Calxeda SATA controller mostly conforms to the AHCI interface
|
||||
with some special extensions to add functionality, to map GPIOs for
|
||||
activity LEDs and for mapping the ComboPHYs.
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: calxeda,hb-ahci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
calxeda,pre-clocks:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Indicates the number of additional clock cycles to transmit before
|
||||
sending an SGPIO pattern.
|
||||
|
||||
calxeda,post-clocks:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Indicates the number of additional clock cycles to transmit after
|
||||
sending an SGPIO pattern.
|
||||
|
||||
calxeda,led-order:
|
||||
description: Maps port numbers to offsets within the SGPIO bitstream.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,port-phys:
|
||||
description: |
|
||||
phandle-combophy and lane assignment, which maps each SATA port to a
|
||||
combophy and a lane within that combophy
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,tx-atten:
|
||||
description: |
|
||||
Contains TX attenuation override codes, one per port.
|
||||
The upper 24 bits of each entry are always 0 and thus ignored.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
calxeda,sgpio-gpio:
|
||||
description: |
|
||||
phandle-gpio bank, bit offset, and default on or off, which indicates
|
||||
that the driver supports SGPIO indicator lights using the indicated
|
||||
GPIOs.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata@ffe08000 {
|
||||
compatible = "calxeda,hb-ahci";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
dma-coherent;
|
||||
calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
|
||||
<&combophy0 2>, <&combophy0 3>;
|
||||
calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
|
||||
calxeda,led-order = <4 0 1 2 3>;
|
||||
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
|
||||
calxeda,pre-clocks = <10>;
|
||||
calxeda,post-clocks = <0>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,45 +0,0 @@
|
||||
DT bindings for the Hitachi HD44780 Character LCD Controller
|
||||
|
||||
The Hitachi HD44780 Character LCD Controller is commonly used on character LCDs
|
||||
that can display one or more lines of text. It exposes an M6800 bus interface,
|
||||
which can be used in either 4-bit or 8-bit mode.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must contain "hit,hd44780",
|
||||
- data-gpios: Must contain an array of either 4 or 8 GPIO specifiers,
|
||||
referring to the GPIO pins connected to the data signal lines DB0-DB7
|
||||
(8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface,
|
||||
- enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin
|
||||
connected to the "E" (Enable) signal line of the LCD Controller's bus
|
||||
interface,
|
||||
- rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin
|
||||
connected to the "RS" (Register Select) signal line of the LCD Controller's
|
||||
bus interface,
|
||||
- display-height-chars: Height of the display, in character cells,
|
||||
- display-width-chars: Width of the display, in character cells.
|
||||
|
||||
Optional properties:
|
||||
- rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin
|
||||
connected to the "RW" (Read/Write) signal line of the LCD Controller's bus
|
||||
interface,
|
||||
- backlight-gpios: Must contain a GPIO specifier, referring to the GPIO pin
|
||||
used for enabling the LCD's backlight,
|
||||
- internal-buffer-width: Internal buffer width (default is 40 for displays
|
||||
with 1 or 2 lines, and display-width-chars for displays with more than 2
|
||||
lines).
|
||||
|
||||
Example:
|
||||
|
||||
auxdisplay {
|
||||
compatible = "hit,hd44780";
|
||||
|
||||
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 1 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 2 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
};
|
||||
96
Bindings/auxdisplay/hit,hd44780.yaml
Normal file
96
Bindings/auxdisplay/hit,hd44780.yaml
Normal file
@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/auxdisplay/hit,hd44780.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hitachi HD44780 Character LCD Controller
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert@linux-m68k.org>
|
||||
|
||||
description:
|
||||
The Hitachi HD44780 Character LCD Controller is commonly used on character
|
||||
LCDs that can display one or more lines of text. It exposes an M6800 bus
|
||||
interface, which can be used in either 4-bit or 8-bit mode.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: hit,hd44780
|
||||
|
||||
data-gpios:
|
||||
description:
|
||||
GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
|
||||
DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
|
||||
oneOf:
|
||||
- maxItems: 4
|
||||
- maxItems: 8
|
||||
|
||||
enable-gpios:
|
||||
description:
|
||||
GPIO pin connected to the "E" (Enable) signal line of the LCD
|
||||
Controller's bus interface.
|
||||
maxItems: 1
|
||||
|
||||
rs-gpios:
|
||||
description:
|
||||
GPIO pin connected to the "RS" (Register Select) signal line of the LCD
|
||||
Controller's bus interface.
|
||||
maxItems: 1
|
||||
|
||||
rw-gpios:
|
||||
description:
|
||||
GPIO pin connected to the "RW" (Read/Write) signal line of the LCD
|
||||
Controller's bus interface.
|
||||
maxItems: 1
|
||||
|
||||
backlight-gpios:
|
||||
description: GPIO pin used for enabling the LCD's backlight.
|
||||
maxItems: 1
|
||||
|
||||
display-height-chars:
|
||||
description: Height of the display, in character cells,
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 4
|
||||
|
||||
display-width-chars:
|
||||
description: Width of the display, in character cells.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 64
|
||||
|
||||
internal-buffer-width:
|
||||
description:
|
||||
Internal buffer width (default is 40 for displays with 1 or 2 lines, and
|
||||
display-width-chars for displays with more than 2 lines).
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
maximum: 64
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- data-gpios
|
||||
- enable-gpios
|
||||
- rs-gpios
|
||||
- display-height-chars
|
||||
- display-width-chars
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
auxdisplay {
|
||||
compatible = "hit,hd44780";
|
||||
|
||||
data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 1 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 2 GPIO_ACTIVE_HIGH>,
|
||||
<&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
display-height-chars = <2>;
|
||||
display-width-chars = <16>;
|
||||
};
|
||||
@ -31,12 +31,11 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
allwinner,sram:
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#definitions/phandle-array
|
||||
- maxItems: 1
|
||||
description:
|
||||
The SRAM that needs to be claimed to access the display engine
|
||||
bus.
|
||||
$ref: /schemas/types.yaml#definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
|
||||
@ -21,8 +21,8 @@ properties:
|
||||
oneOf:
|
||||
- const: allwinner,sun8i-a23-rsb
|
||||
- items:
|
||||
- const: allwinner,sun8i-a83t-rsb
|
||||
- const: allwinner,sun8i-a23-rsb
|
||||
- const: allwinner,sun8i-a83t-rsb
|
||||
- const: allwinner,sun8i-a23-rsb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
83
Bindings/bus/arm,integrator-ap-lm.yaml
Normal file
83
Bindings/bus/arm,integrator-ap-lm.yaml
Normal file
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Integrator/AP Logic Module extension bus
|
||||
|
||||
maintainers:
|
||||
- Linus Walleij <linusw@kernel.org>
|
||||
|
||||
description: The Integrator/AP is a prototyping platform and as such has a
|
||||
site for stacking up to four logic modules (LM) designed specifically for
|
||||
use with this platform. A special system controller register can be read to
|
||||
determine if a logic module is connected at index 0, 1, 2 or 3. The logic
|
||||
module connector is described in this binding. The logic modules per se
|
||||
then have their own specific per-module bindings and they will be described
|
||||
as subnodes under this logic module extension bus.
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: arm,integrator-ap-lm
|
||||
|
||||
ranges: true
|
||||
dma-ranges: true
|
||||
|
||||
patternProperties:
|
||||
"^bus(@[0-9a-f]*)?$":
|
||||
description: Nodes on the Logic Module bus represent logic modules
|
||||
and are named with bus. The first module is at 0xc0000000, the second
|
||||
at 0xd0000000 and so on until the top of the memory of the system at
|
||||
0xffffffff. All information about the memory used by the module is
|
||||
in ranges and dma-ranges.
|
||||
type: object
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus@c0000000 {
|
||||
compatible = "arm,integrator-ap-lm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xc0000000 0xc0000000 0x40000000>;
|
||||
dma-ranges;
|
||||
|
||||
bus@c0000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xc0000000 0x10000000>;
|
||||
/* The Logic Modules sees the Core Module 0 RAM @80000000 */
|
||||
dma-ranges = <0x00000000 0x80000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
serial@100000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x00100000 0x1000>;
|
||||
interrupts-extended = <&impd1_vic 1>;
|
||||
};
|
||||
|
||||
impd1_vic: interrupt-controller@3000000 {
|
||||
compatible = "arm,pl192-vic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x03000000 0x1000>;
|
||||
valid-mask = <0x00000bff>;
|
||||
interrupts-extended = <&pic 9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
additionalProperties: false
|
||||
90
Bindings/bus/baikal,bt1-apb.yaml
Normal file
90
Bindings/bus/baikal,bt1-apb.yaml
Normal file
@ -0,0 +1,90 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 APB-bus
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
|
||||
which routes them to the AXI-APB bridge. This interface is a single master
|
||||
multiple slaves bus in turn serializing IO accesses and routing them to the
|
||||
addressed APB slave devices. In case of any APB protocol collisions, slave
|
||||
device not responding on timeout an IRQ is raised with an erroneous address
|
||||
reported to the APB terminator (APB Errors Handler Block).
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/simple-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: baikal,bt1-apb
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: APB EHB MMIO registers
|
||||
- description: APB MMIO region with no any device mapped
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: ehb
|
||||
- const: nodev
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: APB reference clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: APB domain reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: prst
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
bus@1f059000 {
|
||||
compatible = "baikal,bt1-apb", "simple-bus";
|
||||
reg = <0x1f059000 0x1000>,
|
||||
<0x1d000000 0x2040000>;
|
||||
reg-names = "ehb", "nodev";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges;
|
||||
|
||||
interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&ccu_sys 1>;
|
||||
clock-names = "pclk";
|
||||
|
||||
resets = <&ccu_sys 1>;
|
||||
reset-names = "prst";
|
||||
};
|
||||
...
|
||||
107
Bindings/bus/baikal,bt1-axi.yaml
Normal file
107
Bindings/bus/baikal,bt1-axi.yaml
Normal file
@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 AXI-bus
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
|
||||
high-speed peripheral IP-cores with RAM controller and with MIPS P5600
|
||||
cores. Traffic arbitration is done by means of DW AXI Interconnect (so
|
||||
called AXI Main Interconnect) routing IO requests from one block to
|
||||
another: from CPU to SoC peripherals and between some SoC peripherals
|
||||
(mostly between peripheral devices and RAM, but also between DMA and
|
||||
some peripherals). In case of any protocol error, device not responding
|
||||
an IRQ is raised and a faulty situation is reported to the AXI EHB
|
||||
(Errors Handler Block) embedded on top of the DW AXI Interconnect and
|
||||
accessible by means of the Baikal-T1 System Controller.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/simple-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: baikal,bt1-axi
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Synopsys DesignWare AXI Interconnect QoS registers
|
||||
- description: AXI EHB MMIO system controller registers
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: qos
|
||||
- const: ehb
|
||||
|
||||
'#interconnect-cells':
|
||||
const: 1
|
||||
|
||||
syscon:
|
||||
$ref: /schemas/types.yaml#definitions/phandle
|
||||
description: Phandle to the Baikal-T1 System Controller DT node
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main Interconnect uplink reference clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aclk
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: Main Interconnect reset line
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: arst
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- syscon
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
bus@1f05a000 {
|
||||
compatible = "baikal,bt1-axi", "simple-bus";
|
||||
reg = <0x1f05a000 0x1000>,
|
||||
<0x1f04d110 0x8>;
|
||||
reg-names = "qos", "ehb";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interconnect-cells = <1>;
|
||||
|
||||
syscon = <&syscon>;
|
||||
|
||||
ranges;
|
||||
|
||||
interrupts = <GIC_SHARED 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&ccu_axi 0>;
|
||||
clock-names = "aclk";
|
||||
|
||||
resets = <&ccu_axi 0>;
|
||||
reset-names = "arst";
|
||||
};
|
||||
...
|
||||
@ -80,14 +80,14 @@ examples:
|
||||
ranges = <1 0x00000000 0x42000000 0x02000000>,
|
||||
<5 0x00000000 0x46000000 0x01000000>;
|
||||
|
||||
ethernet@1,01f00000 {
|
||||
ethernet@1,1f00000 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <1 0x01f00000 0x1000>;
|
||||
interrupts = <0 48 4>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
uart@5,00200000 {
|
||||
serial@5,200000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <5 0x00200000 0x20>;
|
||||
interrupts = <0 49 4>;
|
||||
|
||||
@ -52,12 +52,12 @@ properties:
|
||||
- const: allwinner,sun4i-a10-dram-gates-clk
|
||||
|
||||
- items:
|
||||
- const: allwinner,sun5i-a13-dram-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
- const: allwinner,sun5i-a13-dram-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
|
||||
- items:
|
||||
- const: allwinner,sun8i-h3-apb0-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
- const: allwinner,sun8i-h3-apb0-gates-clk
|
||||
- const: allwinner,sun4i-a10-gates-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
188
Bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
188
Bindings/clock/baikal,bt1-ccu-div.yaml
Normal file
@ -0,0 +1,188 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit Dividers
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
|
||||
later ones are described in this binding. Each clock domain can be also
|
||||
individually reset by using the domain clocks divider configuration
|
||||
registers. Baikal-T1 CCU is logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs).
|
||||
3) AXI-bus clock dividers (AXI) - described in this binding file.
|
||||
4) System devices reference clock dividers (SYS) - described in this binding
|
||||
file.
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each sub-block is represented as a separate DT node and has an individual
|
||||
driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
|
||||
then passed over CCU dividers to create signals required for the target clock
|
||||
domain (like AXI-bus or System Device consumers). The dividers have the
|
||||
following structure:
|
||||
|
||||
+--------------+
|
||||
CLKIN --|->+----+ 1|\ |
|
||||
SETCLK--|--|/DIV|->| | |
|
||||
CLKDIV--|--| | | |-|->CLKLOUT
|
||||
LOCK----|--+----+ | | |
|
||||
| |/ |
|
||||
| | |
|
||||
EN------|-----------+ |
|
||||
RST-----|--------------|->RSTOUT
|
||||
+--------------+
|
||||
|
||||
where CLKIN is the reference clock coming either from CCU PLLs or from an
|
||||
external clock oscillator, SETCLK - a command to update the output clock in
|
||||
accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
|
||||
the output clock stabilization, EN - enable/disable the divider block,
|
||||
RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
|
||||
peculiarities the dividers may lack of some functionality depicted on the
|
||||
figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
|
||||
clock provider just doesn't expose either switching functions, or the rate
|
||||
configuration, or both of them.
|
||||
|
||||
The clock dividers, which output clock is then consumed by the SoC individual
|
||||
devices, are united into a single clocks provider called System Devices CCU.
|
||||
Similarly the dividers with output clocks utilized as AXI-bus reference clocks
|
||||
are called AXI-bus CCU. Both of them use the common clock bindings with no
|
||||
custom properties. The list of exported clocks and reset signals can be found
|
||||
in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
|
||||
'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
|
||||
are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
|
||||
to be a children of later one.
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: baikal,bt1-ccu-axi
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock
|
||||
- description: CCU SATA PLL output clock
|
||||
- description: CCU PCIe PLL output clock
|
||||
- description: CCU Ethernet PLL output clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref_clk
|
||||
- const: sata_clk
|
||||
- const: pcie_clk
|
||||
- const: eth_clk
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- baikal,bt1-ccu-axi
|
||||
- baikal,bt1-ccu-sys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# AXI-bus Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d030 {
|
||||
compatible = "baikal,bt1-ccu-axi";
|
||||
reg = <0x1f04d030 0x030>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "sata_clk", "pcie_clk", "eth_clk";
|
||||
};
|
||||
# System Devices Clock Control Unit node:
|
||||
- |
|
||||
#include <dt-bindings/clock/bt1-ccu.h>
|
||||
|
||||
clock-controller@1f04d060 {
|
||||
compatible = "baikal,bt1-ccu-sys";
|
||||
reg = <0x1f04d060 0x0a0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>,
|
||||
<&ccu_pll CCU_SATA_PLL>,
|
||||
<&ccu_pll CCU_PCIE_PLL>,
|
||||
<&ccu_pll CCU_ETH_PLL>;
|
||||
clock-names = "ref_clk", "sata_clk", "pcie_clk",
|
||||
"eth_clk";
|
||||
};
|
||||
# Required Clock Control Unit PLL node:
|
||||
- |
|
||||
ccu_pll: clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
...
|
||||
131
Bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
131
Bindings/clock/baikal,bt1-ccu-pll.yaml
Normal file
@ -0,0 +1,131 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Baikal-T1 Clock Control Unit PLL
|
||||
|
||||
maintainers:
|
||||
- Serge Semin <fancer.lancer@gmail.com>
|
||||
|
||||
description: |
|
||||
Clocks Control Unit is the core of Baikal-T1 SoC System Controller
|
||||
responsible for the chip subsystems clocking and resetting. The CCU is
|
||||
connected with an external fixed rate oscillator, which signal is transformed
|
||||
into clocks of various frequencies and then propagated to either individual
|
||||
IP-blocks or to groups of blocks (clock domains). The transformation is done
|
||||
by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
|
||||
It's logically divided into the next components:
|
||||
1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
|
||||
in general can provide any frequency supported by the CCU PLLs).
|
||||
2) PLLs clocks generators (PLLs) - described in this binding file.
|
||||
3) AXI-bus clock dividers (AXI).
|
||||
4) System devices reference clock dividers (SYS).
|
||||
which are connected with each other as shown on the next figure:
|
||||
|
||||
+---------------+
|
||||
| Baikal-T1 CCU |
|
||||
| +----+------|- MIPS P5600 cores
|
||||
| +-|PLLs|------|- DDR controller
|
||||
| | +----+ |
|
||||
+----+ | | | | |
|
||||
|XTAL|--|-+ | | +---+-|
|
||||
+----+ | | | +-|AXI|-|- AXI-bus
|
||||
| | | +---+-|
|
||||
| | | |
|
||||
| | +----+---+-|- APB-bus
|
||||
| +-------|SYS|-|- Low-speed Devices
|
||||
| +---+-|- High-speed Devices
|
||||
+---------------+
|
||||
|
||||
Each CCU sub-block is represented as a separate dts-node and has an
|
||||
individual driver to be bound with.
|
||||
|
||||
In order to create signals of wide range frequencies the external oscillator
|
||||
output is primarily connected to a set of CCU PLLs. There are five PLLs
|
||||
to create a clock for the MIPS P5600 cores, the embedded DDR controller,
|
||||
SATA, Ethernet and PCIe domains. The last three domains though named by the
|
||||
biggest system interfaces in fact include nearly all of the rest SoC
|
||||
peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
|
||||
with an interface wrapper (so called safe PLL' clocks switcher) to simplify
|
||||
the PLL configuration procedure. The PLLs work as depicted on the next
|
||||
diagram:
|
||||
|
||||
+--------------------------+
|
||||
| |
|
||||
+-->+---+ +---+ +---+ | +---+ 0|\
|
||||
CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
|
||||
+---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
|
||||
CLKOD---------C----------------+ 1| |
|
||||
+--------C--------------------------->|/
|
||||
| | ^
|
||||
Rclk-+->+---+ | |
|
||||
CLKR--->|/NR|-+ |
|
||||
+---+ |
|
||||
BYPASS--------------------------------------+
|
||||
BWADJ--->
|
||||
|
||||
where Rclk is the reference clock coming from XTAL, NR - reference clock
|
||||
divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
|
||||
output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
|
||||
the binding supports the PLL dividers configuration in accordance with a
|
||||
requested rate, while bypassing and bandwidth adjustment settings can be
|
||||
added in future if it gets to be necessary.
|
||||
|
||||
The PLLs CLKOUT is then either directly connected with the corresponding
|
||||
clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
|
||||
divider to create a signal required for the clock domain.
|
||||
|
||||
The CCU PLL dts-node uses the common clock bindings with no custom
|
||||
parameters. The list of exported clocks can be found in
|
||||
'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
|
||||
Baikal-T1 SoC System Controller its DT node is supposed to be a child of
|
||||
later one.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: baikal,bt1-ccu-pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
description: External reference clock
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: ref_clk
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Unit PLL node:
|
||||
- |
|
||||
clock-controller@1f04d000 {
|
||||
compatible = "baikal,bt1-ccu-pll";
|
||||
reg = <0x1f04d000 0x028>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk25m>;
|
||||
clock-names = "ref_clk";
|
||||
};
|
||||
# Required external oscillator:
|
||||
- |
|
||||
clk25m: clock-oscillator-25m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "clk25m";
|
||||
};
|
||||
...
|
||||
@ -65,7 +65,7 @@ examples:
|
||||
- |
|
||||
uart0: serial@58018000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x0 0x58018000 0x0 0x2000>;
|
||||
reg = <0x58018000 0x2000>;
|
||||
clocks = <&clk 45>, <&clk 46>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <0 9 4>;
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
Device Tree Clock bindings for Calxeda highbank platform
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"calxeda,hb-pll-clock" - for a PLL clock
|
||||
"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
|
||||
A9 clock.
|
||||
"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
|
||||
"calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller.
|
||||
- reg : shall be the control register offset from SYSREGs base for the clock.
|
||||
- clocks : shall be the input parent clock phandle for the clock. This is
|
||||
either an oscillator or a pll output.
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
82
Bindings/clock/calxeda.yaml
Normal file
82
Bindings/clock/calxeda.yaml
Normal file
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/calxeda.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Device Tree Clock bindings for Calxeda highbank platform
|
||||
|
||||
description: |
|
||||
This binding covers the Calxeda SoC internal peripheral and bus clocks
|
||||
as used by peripherals. The clocks live inside the "system register"
|
||||
region of the SoC, so are typically presented as children of an
|
||||
"hb-sregs" node.
|
||||
|
||||
maintainers:
|
||||
- Andre Przywara <andre.przywara@arm.com>
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- calxeda,hb-pll-clock
|
||||
- calxeda,hb-a9periph-clock
|
||||
- calxeda,hb-a9bus-clock
|
||||
- calxeda,hb-emmc-clock
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#clock-cells"
|
||||
- compatible
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sregs@3fffc000 {
|
||||
compatible = "calxeda,hb-sregs";
|
||||
reg = <0x3fffc000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: oscillator {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <33333000>;
|
||||
};
|
||||
|
||||
ddrpll: ddrpll@108 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x108>;
|
||||
};
|
||||
|
||||
a9pll: a9pll@100 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x100>;
|
||||
};
|
||||
|
||||
a9periphclk: a9periphclk@104 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "calxeda,hb-a9periph-clock";
|
||||
clocks = <&a9pll>;
|
||||
reg = <0x104>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,94 +0,0 @@
|
||||
Cirrus Logic Lochnagar Audio Development Board
|
||||
|
||||
Lochnagar is an evaluation and development board for Cirrus Logic
|
||||
Smart CODEC and Amp devices. It allows the connection of most Cirrus
|
||||
Logic devices on mini-cards, as well as allowing connection of
|
||||
various application processor systems to provide a full evaluation
|
||||
platform. Audio system topology, clocking and power can all be
|
||||
controlled through the Lochnagar, allowing the device under test
|
||||
to be used in a variety of possible use cases.
|
||||
|
||||
This binding document describes the binding for the clock portion of
|
||||
the driver.
|
||||
|
||||
Also see these documents for generic binding information:
|
||||
[1] Clock : ../clock/clock-bindings.txt
|
||||
|
||||
And these for relevant defines:
|
||||
[2] include/dt-bindings/clock/lochnagar.h
|
||||
|
||||
This binding must be part of the Lochnagar MFD binding:
|
||||
[3] ../mfd/cirrus,lochnagar.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : One of the following strings:
|
||||
"cirrus,lochnagar1-clk"
|
||||
"cirrus,lochnagar2-clk"
|
||||
|
||||
- #clock-cells : Must be 1. The first cell indicates the clock
|
||||
number, see [2] for available clocks and [1].
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks : Must contain an entry for each clock in clock-names.
|
||||
- clock-names : May contain entries for each of the following
|
||||
clocks:
|
||||
- ln-cdc-clkout : Output clock from CODEC card.
|
||||
- ln-dsp-clkout : Output clock from DSP card.
|
||||
- ln-gf-mclk1,ln-gf-mclk2,ln-gf-mclk3,ln-gf-mclk4 : Optional
|
||||
input audio clocks from host system.
|
||||
- ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from
|
||||
external connector.
|
||||
- ln-spdif-mclk : Optional input audio clock from SPDIF.
|
||||
- ln-spdif-clkout : Optional input audio clock from SPDIF.
|
||||
- ln-adat-mclk : Optional input audio clock from ADAT.
|
||||
- ln-pmic-32k : On board fixed clock.
|
||||
- ln-clk-12m : On board fixed clock.
|
||||
- ln-clk-11m : On board fixed clock.
|
||||
- ln-clk-24m : On board fixed clock.
|
||||
- ln-clk-22m : On board fixed clock.
|
||||
- ln-clk-8m : On board fixed clock.
|
||||
- ln-usb-clk-24m : On board fixed clock.
|
||||
- ln-usb-clk-12m : On board fixed clock.
|
||||
|
||||
- assigned-clocks : A list of Lochnagar clocks to be reparented, see
|
||||
[2] for available clocks.
|
||||
- assigned-clock-parents : Parents to be assigned to the clocks
|
||||
listed in "assigned-clocks".
|
||||
|
||||
Optional nodes:
|
||||
|
||||
- fixed-clock nodes may be registered for the following on board clocks:
|
||||
- ln-pmic-32k : 32768 Hz
|
||||
- ln-clk-12m : 12288000 Hz
|
||||
- ln-clk-11m : 11298600 Hz
|
||||
- ln-clk-24m : 24576000 Hz
|
||||
- ln-clk-22m : 22579200 Hz
|
||||
- ln-clk-8m : 8192000 Hz
|
||||
- ln-usb-clk-24m : 24576000 Hz
|
||||
- ln-usb-clk-12m : 12288000 Hz
|
||||
|
||||
Example:
|
||||
|
||||
lochnagar {
|
||||
lochnagar-clk {
|
||||
compatible = "cirrus,lochnagar2-clk";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk-audio>, <&clk_pmic>;
|
||||
clock-names = "ln-gf-mclk2", "ln-pmic-32k";
|
||||
|
||||
assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>,
|
||||
<&lochnagar-clk LOCHNAGAR_CDC_MCLK2>;
|
||||
assigned-clock-parents = <&clk-audio>,
|
||||
<&clk-pmic>;
|
||||
};
|
||||
|
||||
clk-pmic: clk-pmic {
|
||||
compatible = "fixed-clock";
|
||||
clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
78
Bindings/clock/cirrus,lochnagar.yaml
Normal file
78
Bindings/clock/cirrus,lochnagar.yaml
Normal file
@ -0,0 +1,78 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cirrus Logic Lochnagar Audio Development Board
|
||||
|
||||
maintainers:
|
||||
- patches@opensource.cirrus.com
|
||||
|
||||
description: |
|
||||
Lochnagar is an evaluation and development board for Cirrus Logic
|
||||
Smart CODEC and Amp devices. It allows the connection of most Cirrus
|
||||
Logic devices on mini-cards, as well as allowing connection of various
|
||||
application processor systems to provide a full evaluation platform.
|
||||
Audio system topology, clocking and power can all be controlled through
|
||||
the Lochnagar, allowing the device under test to be used in a variety of
|
||||
possible use cases.
|
||||
|
||||
This binding document describes the binding for the clock portion of the
|
||||
driver.
|
||||
|
||||
Also see these documents for generic binding information:
|
||||
[1] Clock : ../clock/clock-bindings.txt
|
||||
|
||||
And these for relevant defines:
|
||||
[2] include/dt-bindings/clock/lochnagar.h
|
||||
|
||||
This binding must be part of the Lochnagar MFD binding:
|
||||
[3] ../mfd/cirrus,lochnagar.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cirrus,lochnagar1-clk
|
||||
- cirrus,lochnagar2-clk
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
The first cell indicates the clock number, see [2] for available
|
||||
clocks and [1].
|
||||
const: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
enum:
|
||||
- ln-cdc-clkout # Output clock from CODEC card.
|
||||
- ln-dsp-clkout # Output clock from DSP card.
|
||||
- ln-gf-mclk1 # Optional input clock from host system.
|
||||
- ln-gf-mclk2 # Optional input clock from host system.
|
||||
- ln-gf-mclk3 # Optional input clock from host system.
|
||||
- ln-gf-mclk4 # Optional input clock from host system.
|
||||
- ln-psia1-mclk # Optional input clock from external connector.
|
||||
- ln-psia2-mclk # Optional input clock from external connector.
|
||||
- ln-spdif-mclk # Optional input clock from SPDIF.
|
||||
- ln-spdif-clkout # Optional input clock from SPDIF.
|
||||
- ln-adat-mclk # Optional input clock from ADAT.
|
||||
- ln-pmic-32k # On board fixed clock.
|
||||
- ln-clk-12m # On board fixed clock.
|
||||
- ln-clk-11m # On board fixed clock.
|
||||
- ln-clk-24m # On board fixed clock.
|
||||
- ln-clk-22m # On board fixed clock.
|
||||
- ln-clk-8m # On board fixed clock.
|
||||
- ln-usb-clk-24m # On board fixed clock.
|
||||
- ln-usb-clk-12m # On board fixed clock.
|
||||
minItems: 1
|
||||
maxItems: 19
|
||||
|
||||
clocks: true
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
@ -24,9 +24,8 @@ properties:
|
||||
|
||||
clock-div:
|
||||
description: Fixed divider
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32
|
||||
- minimum: 1
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 1
|
||||
|
||||
clock-mult:
|
||||
description: Fixed multiplier
|
||||
|
||||
@ -28,15 +28,14 @@ properties:
|
||||
const: 0
|
||||
|
||||
fsl,vco-hz:
|
||||
description: Optional for VCO frequency of the PLL in Hertz.
|
||||
The VCO frequency of this PLL cannot be changed during runtime
|
||||
only at startup. Therefore, the output frequencies are very
|
||||
limited and might not even closely match the requested frequency.
|
||||
To work around this restriction the user may specify its own
|
||||
desired VCO frequency for the PLL.
|
||||
minimum: 650000000
|
||||
maximum: 1300000000
|
||||
default: 1188000000
|
||||
description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
|
||||
of this PLL cannot be changed during runtime only at startup. Therefore,
|
||||
the output frequencies are very limited and might not even closely match
|
||||
the requested frequency. To work around this restriction the user may specify
|
||||
its own desired VCO frequency for the PLL.
|
||||
minimum: 650000000
|
||||
maximum: 1300000000
|
||||
default: 1188000000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@ -51,7 +50,7 @@ examples:
|
||||
- |
|
||||
dpclk: clock-display@f1f0000 {
|
||||
compatible = "fsl,ls1028a-plldig";
|
||||
reg = <0x0 0xf1f0000 0x0 0xffff>;
|
||||
reg = <0xf1f0000 0xffff>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc_27m>;
|
||||
};
|
||||
|
||||
@ -12,6 +12,7 @@ Required properties:
|
||||
"idt,5p49v5933"
|
||||
"idt,5p49v5935"
|
||||
"idt,5p49v6901"
|
||||
"idt,5p49v6965"
|
||||
- reg: i2c device address, shall be 0x68 or 0x6a.
|
||||
- #clock-cells: from common clock binding; shall be set to 1.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
|
||||
@ -1,26 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx1-ccm".
|
||||
- reg: Address and length of the register set.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@21b000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm: pwm@208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
51
Bindings/clock/imx1-clock.yaml
Normal file
51
Bindings/clock/imx1-clock.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
maintainers:
|
||||
- Alexander Shiyan <shc_work@mail.ru>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx1-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx1-clock.h>
|
||||
|
||||
clock-controller@21b000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm@208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,27 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX21
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx21-ccm".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts : Should contain CCM interrupt.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx21-ccm";
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
51
Bindings/clock/imx21-clock.yaml
Normal file
51
Bindings/clock/imx21-clock.yaml
Normal file
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx21-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX21
|
||||
|
||||
maintainers:
|
||||
- Alexander Shiyan <shc_work@mail.ru>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx21-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx21-clock.h>
|
||||
|
||||
clock-controller@10027000 {
|
||||
compatible = "fsl,imx21-ccm";
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,70 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX23
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx23-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX23
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll 1
|
||||
ref_cpu 2
|
||||
ref_emi 3
|
||||
ref_pix 4
|
||||
ref_io 5
|
||||
saif_sel 6
|
||||
lcdif_sel 7
|
||||
gpmi_sel 8
|
||||
ssp_sel 9
|
||||
emi_sel 10
|
||||
cpu 11
|
||||
etm_sel 12
|
||||
cpu_pll 13
|
||||
cpu_xtal 14
|
||||
hbus 15
|
||||
xbus 16
|
||||
lcdif_div 17
|
||||
ssp_div 18
|
||||
gpmi_div 19
|
||||
emi_pll 20
|
||||
emi_xtal 21
|
||||
etm_div 22
|
||||
saif_div 23
|
||||
clk32k_div 24
|
||||
rtc 25
|
||||
adc 26
|
||||
spdif_div 27
|
||||
clk32k 28
|
||||
dri 29
|
||||
pwm 30
|
||||
filt 31
|
||||
uart 32
|
||||
ssp 33
|
||||
gpmi 34
|
||||
spdif 35
|
||||
emi 36
|
||||
saif 37
|
||||
lcdif 38
|
||||
etm 39
|
||||
usb 40
|
||||
usb_phy 41
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
auart0: serial@8006c000 {
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
};
|
||||
92
Bindings/clock/imx23-clock.yaml
Normal file
92
Bindings/clock/imx23-clock.yaml
Normal file
@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx23-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX23
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX23
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll 1
|
||||
ref_cpu 2
|
||||
ref_emi 3
|
||||
ref_pix 4
|
||||
ref_io 5
|
||||
saif_sel 6
|
||||
lcdif_sel 7
|
||||
gpmi_sel 8
|
||||
ssp_sel 9
|
||||
emi_sel 10
|
||||
cpu 11
|
||||
etm_sel 12
|
||||
cpu_pll 13
|
||||
cpu_xtal 14
|
||||
hbus 15
|
||||
xbus 16
|
||||
lcdif_div 17
|
||||
ssp_div 18
|
||||
gpmi_div 19
|
||||
emi_pll 20
|
||||
emi_xtal 21
|
||||
etm_div 22
|
||||
saif_div 23
|
||||
clk32k_div 24
|
||||
rtc 25
|
||||
adc 26
|
||||
spdif_div 27
|
||||
clk32k 28
|
||||
dri 29
|
||||
pwm 30
|
||||
filt 31
|
||||
uart 32
|
||||
ssp 33
|
||||
gpmi 34
|
||||
spdif 35
|
||||
emi 36
|
||||
saif 37
|
||||
lcdif 38
|
||||
etm 39
|
||||
usb 40
|
||||
usb_phy 41
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx23-clkctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@80040000 {
|
||||
compatible = "fsl,imx23-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@8006c000 {
|
||||
compatible = "fsl,imx23-auart";
|
||||
reg = <0x8006c000 0x2000>;
|
||||
interrupts = <24 25 23>;
|
||||
clocks = <&clks 32>;
|
||||
};
|
||||
@ -1,160 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX25
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx25-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX25
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
osc 1
|
||||
mpll 2
|
||||
upll 3
|
||||
mpll_cpu_3_4 4
|
||||
cpu_sel 5
|
||||
cpu 6
|
||||
ahb 7
|
||||
usb_div 8
|
||||
ipg 9
|
||||
per0_sel 10
|
||||
per1_sel 11
|
||||
per2_sel 12
|
||||
per3_sel 13
|
||||
per4_sel 14
|
||||
per5_sel 15
|
||||
per6_sel 16
|
||||
per7_sel 17
|
||||
per8_sel 18
|
||||
per9_sel 19
|
||||
per10_sel 20
|
||||
per11_sel 21
|
||||
per12_sel 22
|
||||
per13_sel 23
|
||||
per14_sel 24
|
||||
per15_sel 25
|
||||
per0 26
|
||||
per1 27
|
||||
per2 28
|
||||
per3 29
|
||||
per4 30
|
||||
per5 31
|
||||
per6 32
|
||||
per7 33
|
||||
per8 34
|
||||
per9 35
|
||||
per10 36
|
||||
per11 37
|
||||
per12 38
|
||||
per13 39
|
||||
per14 40
|
||||
per15 41
|
||||
csi_ipg_per 42
|
||||
epit_ipg_per 43
|
||||
esai_ipg_per 44
|
||||
esdhc1_ipg_per 45
|
||||
esdhc2_ipg_per 46
|
||||
gpt_ipg_per 47
|
||||
i2c_ipg_per 48
|
||||
lcdc_ipg_per 49
|
||||
nfc_ipg_per 50
|
||||
owire_ipg_per 51
|
||||
pwm_ipg_per 52
|
||||
sim1_ipg_per 53
|
||||
sim2_ipg_per 54
|
||||
ssi1_ipg_per 55
|
||||
ssi2_ipg_per 56
|
||||
uart_ipg_per 57
|
||||
ata_ahb 58
|
||||
reserved 59
|
||||
csi_ahb 60
|
||||
emi_ahb 61
|
||||
esai_ahb 62
|
||||
esdhc1_ahb 63
|
||||
esdhc2_ahb 64
|
||||
fec_ahb 65
|
||||
lcdc_ahb 66
|
||||
rtic_ahb 67
|
||||
sdma_ahb 68
|
||||
slcdc_ahb 69
|
||||
usbotg_ahb 70
|
||||
reserved 71
|
||||
reserved 72
|
||||
reserved 73
|
||||
reserved 74
|
||||
can1_ipg 75
|
||||
can2_ipg 76
|
||||
csi_ipg 77
|
||||
cspi1_ipg 78
|
||||
cspi2_ipg 79
|
||||
cspi3_ipg 80
|
||||
dryice_ipg 81
|
||||
ect_ipg 82
|
||||
epit1_ipg 83
|
||||
epit2_ipg 84
|
||||
reserved 85
|
||||
esdhc1_ipg 86
|
||||
esdhc2_ipg 87
|
||||
fec_ipg 88
|
||||
reserved 89
|
||||
reserved 90
|
||||
reserved 91
|
||||
gpt1_ipg 92
|
||||
gpt2_ipg 93
|
||||
gpt3_ipg 94
|
||||
gpt4_ipg 95
|
||||
reserved 96
|
||||
reserved 97
|
||||
reserved 98
|
||||
iim_ipg 99
|
||||
reserved 100
|
||||
reserved 101
|
||||
kpp_ipg 102
|
||||
lcdc_ipg 103
|
||||
reserved 104
|
||||
pwm1_ipg 105
|
||||
pwm2_ipg 106
|
||||
pwm3_ipg 107
|
||||
pwm4_ipg 108
|
||||
rngb_ipg 109
|
||||
reserved 110
|
||||
scc_ipg 111
|
||||
sdma_ipg 112
|
||||
sim1_ipg 113
|
||||
sim2_ipg 114
|
||||
slcdc_ipg 115
|
||||
spba_ipg 116
|
||||
ssi1_ipg 117
|
||||
ssi2_ipg 118
|
||||
tsc_ipg 119
|
||||
uart1_ipg 120
|
||||
uart2_ipg 121
|
||||
uart3_ipg 122
|
||||
uart4_ipg 123
|
||||
uart5_ipg 124
|
||||
reserved 125
|
||||
wdt_ipg 126
|
||||
cko_div 127
|
||||
cko_sel 128
|
||||
cko 129
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@53f80000 {
|
||||
compatible = "fsl,imx25-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>;
|
||||
};
|
||||
|
||||
uart1: serial@43f90000 {
|
||||
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 79>, <&clks 50>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
186
Bindings/clock/imx25-clock.yaml
Normal file
186
Bindings/clock/imx25-clock.yaml
Normal file
@ -0,0 +1,186 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX25
|
||||
|
||||
maintainers:
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX25
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
--------------------------
|
||||
dummy 0
|
||||
osc 1
|
||||
mpll 2
|
||||
upll 3
|
||||
mpll_cpu_3_4 4
|
||||
cpu_sel 5
|
||||
cpu 6
|
||||
ahb 7
|
||||
usb_div 8
|
||||
ipg 9
|
||||
per0_sel 10
|
||||
per1_sel 11
|
||||
per2_sel 12
|
||||
per3_sel 13
|
||||
per4_sel 14
|
||||
per5_sel 15
|
||||
per6_sel 16
|
||||
per7_sel 17
|
||||
per8_sel 18
|
||||
per9_sel 19
|
||||
per10_sel 20
|
||||
per11_sel 21
|
||||
per12_sel 22
|
||||
per13_sel 23
|
||||
per14_sel 24
|
||||
per15_sel 25
|
||||
per0 26
|
||||
per1 27
|
||||
per2 28
|
||||
per3 29
|
||||
per4 30
|
||||
per5 31
|
||||
per6 32
|
||||
per7 33
|
||||
per8 34
|
||||
per9 35
|
||||
per10 36
|
||||
per11 37
|
||||
per12 38
|
||||
per13 39
|
||||
per14 40
|
||||
per15 41
|
||||
csi_ipg_per 42
|
||||
epit_ipg_per 43
|
||||
esai_ipg_per 44
|
||||
esdhc1_ipg_per 45
|
||||
esdhc2_ipg_per 46
|
||||
gpt_ipg_per 47
|
||||
i2c_ipg_per 48
|
||||
lcdc_ipg_per 49
|
||||
nfc_ipg_per 50
|
||||
owire_ipg_per 51
|
||||
pwm_ipg_per 52
|
||||
sim1_ipg_per 53
|
||||
sim2_ipg_per 54
|
||||
ssi1_ipg_per 55
|
||||
ssi2_ipg_per 56
|
||||
uart_ipg_per 57
|
||||
ata_ahb 58
|
||||
reserved 59
|
||||
csi_ahb 60
|
||||
emi_ahb 61
|
||||
esai_ahb 62
|
||||
esdhc1_ahb 63
|
||||
esdhc2_ahb 64
|
||||
fec_ahb 65
|
||||
lcdc_ahb 66
|
||||
rtic_ahb 67
|
||||
sdma_ahb 68
|
||||
slcdc_ahb 69
|
||||
usbotg_ahb 70
|
||||
reserved 71
|
||||
reserved 72
|
||||
reserved 73
|
||||
reserved 74
|
||||
can1_ipg 75
|
||||
can2_ipg 76
|
||||
csi_ipg 77
|
||||
cspi1_ipg 78
|
||||
cspi2_ipg 79
|
||||
cspi3_ipg 80
|
||||
dryice_ipg 81
|
||||
ect_ipg 82
|
||||
epit1_ipg 83
|
||||
epit2_ipg 84
|
||||
reserved 85
|
||||
esdhc1_ipg 86
|
||||
esdhc2_ipg 87
|
||||
fec_ipg 88
|
||||
reserved 89
|
||||
reserved 90
|
||||
reserved 91
|
||||
gpt1_ipg 92
|
||||
gpt2_ipg 93
|
||||
gpt3_ipg 94
|
||||
gpt4_ipg 95
|
||||
reserved 96
|
||||
reserved 97
|
||||
reserved 98
|
||||
iim_ipg 99
|
||||
reserved 100
|
||||
reserved 101
|
||||
kpp_ipg 102
|
||||
lcdc_ipg 103
|
||||
reserved 104
|
||||
pwm1_ipg 105
|
||||
pwm2_ipg 106
|
||||
pwm3_ipg 107
|
||||
pwm4_ipg 108
|
||||
rngb_ipg 109
|
||||
reserved 110
|
||||
scc_ipg 111
|
||||
sdma_ipg 112
|
||||
sim1_ipg 113
|
||||
sim2_ipg 114
|
||||
slcdc_ipg 115
|
||||
spba_ipg 116
|
||||
ssi1_ipg 117
|
||||
ssi2_ipg 118
|
||||
tsc_ipg 119
|
||||
uart1_ipg 120
|
||||
uart2_ipg 121
|
||||
uart3_ipg 122
|
||||
uart4_ipg 123
|
||||
uart5_ipg 124
|
||||
reserved 125
|
||||
wdt_ipg 126
|
||||
cko_div 127
|
||||
cko_sel 128
|
||||
cko 129
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx25-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@53f80000 {
|
||||
compatible = "fsl,imx25-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@43f90000 {
|
||||
compatible = "fsl,imx25-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 79>, <&clks 50>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,27 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX27
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx27-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
55
Bindings/clock/imx27-clock.yaml
Normal file
55
Bindings/clock/imx27-clock.yaml
Normal file
@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx27-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX27
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx27-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx27-clock.h>
|
||||
|
||||
clock-controller@10027000 {
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,93 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX28
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx28-clkctrl"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX28
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll0 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
ref_cpu 4
|
||||
ref_emi 5
|
||||
ref_io0 6
|
||||
ref_io1 7
|
||||
ref_pix 8
|
||||
ref_hsadc 9
|
||||
ref_gpmi 10
|
||||
saif0_sel 11
|
||||
saif1_sel 12
|
||||
gpmi_sel 13
|
||||
ssp0_sel 14
|
||||
ssp1_sel 15
|
||||
ssp2_sel 16
|
||||
ssp3_sel 17
|
||||
emi_sel 18
|
||||
etm_sel 19
|
||||
lcdif_sel 20
|
||||
cpu 21
|
||||
ptp_sel 22
|
||||
cpu_pll 23
|
||||
cpu_xtal 24
|
||||
hbus 25
|
||||
xbus 26
|
||||
ssp0_div 27
|
||||
ssp1_div 28
|
||||
ssp2_div 29
|
||||
ssp3_div 30
|
||||
gpmi_div 31
|
||||
emi_pll 32
|
||||
emi_xtal 33
|
||||
lcdif_div 34
|
||||
etm_div 35
|
||||
ptp 36
|
||||
saif0_div 37
|
||||
saif1_div 38
|
||||
clk32k_div 39
|
||||
rtc 40
|
||||
lradc 41
|
||||
spdif_div 42
|
||||
clk32k 43
|
||||
pwm 44
|
||||
uart 45
|
||||
ssp0 46
|
||||
ssp1 47
|
||||
ssp2 48
|
||||
ssp3 49
|
||||
gpmi 50
|
||||
spdif 51
|
||||
emi 52
|
||||
saif0 53
|
||||
saif1 54
|
||||
lcdif 55
|
||||
etm 56
|
||||
fec 57
|
||||
can0 58
|
||||
can1 59
|
||||
usb0 60
|
||||
usb1 61
|
||||
usb0_phy 62
|
||||
usb1_phy 63
|
||||
enet_out 64
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clkctrl@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
auart0: serial@8006a000 {
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
};
|
||||
115
Bindings/clock/imx28-clock.yaml
Normal file
115
Bindings/clock/imx28-clock.yaml
Normal file
@ -0,0 +1,115 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX28
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX28
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
------------------
|
||||
ref_xtal 0
|
||||
pll0 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
ref_cpu 4
|
||||
ref_emi 5
|
||||
ref_io0 6
|
||||
ref_io1 7
|
||||
ref_pix 8
|
||||
ref_hsadc 9
|
||||
ref_gpmi 10
|
||||
saif0_sel 11
|
||||
saif1_sel 12
|
||||
gpmi_sel 13
|
||||
ssp0_sel 14
|
||||
ssp1_sel 15
|
||||
ssp2_sel 16
|
||||
ssp3_sel 17
|
||||
emi_sel 18
|
||||
etm_sel 19
|
||||
lcdif_sel 20
|
||||
cpu 21
|
||||
ptp_sel 22
|
||||
cpu_pll 23
|
||||
cpu_xtal 24
|
||||
hbus 25
|
||||
xbus 26
|
||||
ssp0_div 27
|
||||
ssp1_div 28
|
||||
ssp2_div 29
|
||||
ssp3_div 30
|
||||
gpmi_div 31
|
||||
emi_pll 32
|
||||
emi_xtal 33
|
||||
lcdif_div 34
|
||||
etm_div 35
|
||||
ptp 36
|
||||
saif0_div 37
|
||||
saif1_div 38
|
||||
clk32k_div 39
|
||||
rtc 40
|
||||
lradc 41
|
||||
spdif_div 42
|
||||
clk32k 43
|
||||
pwm 44
|
||||
uart 45
|
||||
ssp0 46
|
||||
ssp1 47
|
||||
ssp2 48
|
||||
ssp3 49
|
||||
gpmi 50
|
||||
spdif 51
|
||||
emi 52
|
||||
saif0 53
|
||||
saif1 54
|
||||
lcdif 55
|
||||
etm 56
|
||||
fec 57
|
||||
can0 58
|
||||
can1 59
|
||||
usb0 60
|
||||
usb1 61
|
||||
usb0_phy 62
|
||||
usb1_phy 63
|
||||
enet_out 64
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx28-clkctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@80040000 {
|
||||
compatible = "fsl,imx28-clkctrl";
|
||||
reg = <0x80040000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@8006a000 {
|
||||
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
|
||||
reg = <0x8006a000 0x2000>;
|
||||
interrupts = <112 70 71>;
|
||||
clocks = <&clks 45>;
|
||||
};
|
||||
@ -1,90 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX31
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx31-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX31
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
-----------------------
|
||||
dummy 0
|
||||
ckih 1
|
||||
ckil 2
|
||||
mpll 3
|
||||
spll 4
|
||||
upll 5
|
||||
mcu_main 6
|
||||
hsp 7
|
||||
ahb 8
|
||||
nfc 9
|
||||
ipg 10
|
||||
per_div 11
|
||||
per 12
|
||||
csi_sel 13
|
||||
fir_sel 14
|
||||
csi_div 15
|
||||
usb_div_pre 16
|
||||
usb_div_post 17
|
||||
fir_div_pre 18
|
||||
fir_div_post 19
|
||||
sdhc1_gate 20
|
||||
sdhc2_gate 21
|
||||
gpt_gate 22
|
||||
epit1_gate 23
|
||||
epit2_gate 24
|
||||
iim_gate 25
|
||||
ata_gate 26
|
||||
sdma_gate 27
|
||||
cspi3_gate 28
|
||||
rng_gate 29
|
||||
uart1_gate 30
|
||||
uart2_gate 31
|
||||
ssi1_gate 32
|
||||
i2c1_gate 33
|
||||
i2c2_gate 34
|
||||
i2c3_gate 35
|
||||
hantro_gate 36
|
||||
mstick1_gate 37
|
||||
mstick2_gate 38
|
||||
csi_gate 39
|
||||
rtc_gate 40
|
||||
wdog_gate 41
|
||||
pwm_gate 42
|
||||
sim_gate 43
|
||||
ect_gate 44
|
||||
usb_gate 45
|
||||
kpp_gate 46
|
||||
ipu_gate 47
|
||||
uart3_gate 48
|
||||
uart4_gate 49
|
||||
uart5_gate 50
|
||||
owire_gate 51
|
||||
ssi2_gate 52
|
||||
cspi1_gate 53
|
||||
cspi2_gate 54
|
||||
gacc_gate 55
|
||||
emi_gate 56
|
||||
rtic_gate 57
|
||||
firi_gate 58
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@53f80000{
|
||||
compatible = "fsl,imx31-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>, <53>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@43f90000 {
|
||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 10>, <&clks 30>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
120
Bindings/clock/imx31-clock.yaml
Normal file
120
Bindings/clock/imx31-clock.yaml
Normal file
@ -0,0 +1,120 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx31-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX31
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX31
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
-----------------------
|
||||
dummy 0
|
||||
ckih 1
|
||||
ckil 2
|
||||
mpll 3
|
||||
spll 4
|
||||
upll 5
|
||||
mcu_main 6
|
||||
hsp 7
|
||||
ahb 8
|
||||
nfc 9
|
||||
ipg 10
|
||||
per_div 11
|
||||
per 12
|
||||
csi_sel 13
|
||||
fir_sel 14
|
||||
csi_div 15
|
||||
usb_div_pre 16
|
||||
usb_div_post 17
|
||||
fir_div_pre 18
|
||||
fir_div_post 19
|
||||
sdhc1_gate 20
|
||||
sdhc2_gate 21
|
||||
gpt_gate 22
|
||||
epit1_gate 23
|
||||
epit2_gate 24
|
||||
iim_gate 25
|
||||
ata_gate 26
|
||||
sdma_gate 27
|
||||
cspi3_gate 28
|
||||
rng_gate 29
|
||||
uart1_gate 30
|
||||
uart2_gate 31
|
||||
ssi1_gate 32
|
||||
i2c1_gate 33
|
||||
i2c2_gate 34
|
||||
i2c3_gate 35
|
||||
hantro_gate 36
|
||||
mstick1_gate 37
|
||||
mstick2_gate 38
|
||||
csi_gate 39
|
||||
rtc_gate 40
|
||||
wdog_gate 41
|
||||
pwm_gate 42
|
||||
sim_gate 43
|
||||
ect_gate 44
|
||||
usb_gate 45
|
||||
kpp_gate 46
|
||||
ipu_gate 47
|
||||
uart3_gate 48
|
||||
uart4_gate 49
|
||||
uart5_gate 50
|
||||
owire_gate 51
|
||||
ssi2_gate 52
|
||||
cspi1_gate 53
|
||||
cspi2_gate 54
|
||||
gacc_gate 55
|
||||
emi_gate 56
|
||||
rtic_gate 57
|
||||
firi_gate 58
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx31-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for DVFS when a frequency change is requested, request 2 is
|
||||
to generate interrupt for DPTC when a voltage change is requested.
|
||||
items:
|
||||
- description: CCM DVFS interrupt request 1
|
||||
- description: CCM DPTC interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@53f80000 {
|
||||
compatible = "fsl,imx31-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>, <53>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
serial@43f90000 {
|
||||
compatible = "fsl,imx31-uart", "fsl,imx21-uart";
|
||||
reg = <0x43f90000 0x4000>;
|
||||
interrupts = <45>;
|
||||
clocks = <&clks 10>, <&clks 30>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,114 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX35
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx35-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX35
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
ckih 0
|
||||
mpll 1
|
||||
ppll 2
|
||||
mpll_075 3
|
||||
arm 4
|
||||
hsp 5
|
||||
hsp_div 6
|
||||
hsp_sel 7
|
||||
ahb 8
|
||||
ipg 9
|
||||
arm_per_div 10
|
||||
ahb_per_div 11
|
||||
ipg_per 12
|
||||
uart_sel 13
|
||||
uart_div 14
|
||||
esdhc_sel 15
|
||||
esdhc1_div 16
|
||||
esdhc2_div 17
|
||||
esdhc3_div 18
|
||||
spdif_sel 19
|
||||
spdif_div_pre 20
|
||||
spdif_div_post 21
|
||||
ssi_sel 22
|
||||
ssi1_div_pre 23
|
||||
ssi1_div_post 24
|
||||
ssi2_div_pre 25
|
||||
ssi2_div_post 26
|
||||
usb_sel 27
|
||||
usb_div 28
|
||||
nfc_div 29
|
||||
asrc_gate 30
|
||||
pata_gate 31
|
||||
audmux_gate 32
|
||||
can1_gate 33
|
||||
can2_gate 34
|
||||
cspi1_gate 35
|
||||
cspi2_gate 36
|
||||
ect_gate 37
|
||||
edio_gate 38
|
||||
emi_gate 39
|
||||
epit1_gate 40
|
||||
epit2_gate 41
|
||||
esai_gate 42
|
||||
esdhc1_gate 43
|
||||
esdhc2_gate 44
|
||||
esdhc3_gate 45
|
||||
fec_gate 46
|
||||
gpio1_gate 47
|
||||
gpio2_gate 48
|
||||
gpio3_gate 49
|
||||
gpt_gate 50
|
||||
i2c1_gate 51
|
||||
i2c2_gate 52
|
||||
i2c3_gate 53
|
||||
iomuxc_gate 54
|
||||
ipu_gate 55
|
||||
kpp_gate 56
|
||||
mlb_gate 57
|
||||
mshc_gate 58
|
||||
owire_gate 59
|
||||
pwm_gate 60
|
||||
rngc_gate 61
|
||||
rtc_gate 62
|
||||
rtic_gate 63
|
||||
scc_gate 64
|
||||
sdma_gate 65
|
||||
spba_gate 66
|
||||
spdif_gate 67
|
||||
ssi1_gate 68
|
||||
ssi2_gate 69
|
||||
uart1_gate 70
|
||||
uart2_gate 71
|
||||
uart3_gate 72
|
||||
usbotg_gate 73
|
||||
wdog_gate 74
|
||||
max_gate 75
|
||||
admux_gate 76
|
||||
csi_gate 77
|
||||
csi_div 78
|
||||
csi_sel 79
|
||||
iim_gate 80
|
||||
gpu2d_gate 81
|
||||
ckli_gate 82
|
||||
|
||||
Examples:
|
||||
|
||||
clks: ccm@53f80000 {
|
||||
compatible = "fsl,imx35-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
esdhc1: esdhc@53fb4000 {
|
||||
compatible = "fsl,imx35-esdhc";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
};
|
||||
139
Bindings/clock/imx35-clock.yaml
Normal file
139
Bindings/clock/imx35-clock.yaml
Normal file
@ -0,0 +1,139 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX35
|
||||
|
||||
maintainers:
|
||||
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX35
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
ckih 0
|
||||
mpll 1
|
||||
ppll 2
|
||||
mpll_075 3
|
||||
arm 4
|
||||
hsp 5
|
||||
hsp_div 6
|
||||
hsp_sel 7
|
||||
ahb 8
|
||||
ipg 9
|
||||
arm_per_div 10
|
||||
ahb_per_div 11
|
||||
ipg_per 12
|
||||
uart_sel 13
|
||||
uart_div 14
|
||||
esdhc_sel 15
|
||||
esdhc1_div 16
|
||||
esdhc2_div 17
|
||||
esdhc3_div 18
|
||||
spdif_sel 19
|
||||
spdif_div_pre 20
|
||||
spdif_div_post 21
|
||||
ssi_sel 22
|
||||
ssi1_div_pre 23
|
||||
ssi1_div_post 24
|
||||
ssi2_div_pre 25
|
||||
ssi2_div_post 26
|
||||
usb_sel 27
|
||||
usb_div 28
|
||||
nfc_div 29
|
||||
asrc_gate 30
|
||||
pata_gate 31
|
||||
audmux_gate 32
|
||||
can1_gate 33
|
||||
can2_gate 34
|
||||
cspi1_gate 35
|
||||
cspi2_gate 36
|
||||
ect_gate 37
|
||||
edio_gate 38
|
||||
emi_gate 39
|
||||
epit1_gate 40
|
||||
epit2_gate 41
|
||||
esai_gate 42
|
||||
esdhc1_gate 43
|
||||
esdhc2_gate 44
|
||||
esdhc3_gate 45
|
||||
fec_gate 46
|
||||
gpio1_gate 47
|
||||
gpio2_gate 48
|
||||
gpio3_gate 49
|
||||
gpt_gate 50
|
||||
i2c1_gate 51
|
||||
i2c2_gate 52
|
||||
i2c3_gate 53
|
||||
iomuxc_gate 54
|
||||
ipu_gate 55
|
||||
kpp_gate 56
|
||||
mlb_gate 57
|
||||
mshc_gate 58
|
||||
owire_gate 59
|
||||
pwm_gate 60
|
||||
rngc_gate 61
|
||||
rtc_gate 62
|
||||
rtic_gate 63
|
||||
scc_gate 64
|
||||
sdma_gate 65
|
||||
spba_gate 66
|
||||
spdif_gate 67
|
||||
ssi1_gate 68
|
||||
ssi2_gate 69
|
||||
uart1_gate 70
|
||||
uart2_gate 71
|
||||
uart3_gate 72
|
||||
usbotg_gate 73
|
||||
wdog_gate 74
|
||||
max_gate 75
|
||||
admux_gate 76
|
||||
csi_gate 77
|
||||
csi_div 78
|
||||
csi_sel 79
|
||||
iim_gate 80
|
||||
gpu2d_gate 81
|
||||
ckli_gate 82
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx35-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@53f80000 {
|
||||
compatible = "fsl,imx35-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
interrupts = <31>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
esdhc@53fb4000 {
|
||||
compatible = "fsl,imx35-esdhc";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&clks 9>, <&clks 8>, <&clks 43>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
};
|
||||
@ -1,28 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX5
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
|
||||
for the full list of i.MX5 clock IDs.
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
65
Bindings/clock/imx5-clock.yaml
Normal file
65
Bindings/clock/imx5-clock.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx5-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX5
|
||||
|
||||
maintainers:
|
||||
- Fabio Estevam <fabio.estevam@nxp.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h
|
||||
for the full list of i.MX5 clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx53-ccm
|
||||
- fsl,imx51-ccm
|
||||
- fsl,imx50-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,41 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX6 Quad
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6q-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain CCM interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
Optional properties:
|
||||
- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal
|
||||
on power off.
|
||||
Use this property if the SoC should be powered off by external power
|
||||
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
|
||||
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
|
||||
be using "syscon-poweroff" driver instead.
|
||||
- clocks: list of clock specifiers, must contain an entry for each entry
|
||||
in clock-names
|
||||
- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
for the full list of i.MX6 Quad and DualLite clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
clks: ccm@20c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 0x04 0 88 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@2020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
71
Bindings/clock/imx6q-clock.yaml
Normal file
71
Bindings/clock/imx6q-clock.yaml
Normal file
@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 Quad
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6q-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 24m osc
|
||||
- description: 32k osc
|
||||
- description: ckih1 clock input
|
||||
- description: anaclk1 clock input
|
||||
- description: anaclk2 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc
|
||||
- const: ckil
|
||||
- const: ckih1
|
||||
- const: anaclk1
|
||||
- const: anaclk2
|
||||
|
||||
fsl,pmic-stby-poweroff:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
Use this property if the SoC should be powered off by external power
|
||||
management IC (PMIC) triggered via PMIC_STBY_REQ signal.
|
||||
Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should
|
||||
be using "syscon-poweroff" driver instead.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,10 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX6 SoloLite
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sl-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
|
||||
for the full list of i.MX6 SoloLite clock IDs.
|
||||
47
Bindings/clock/imx6sl-clock.yaml
Normal file
47
Bindings/clock/imx6sl-clock.yaml
Normal file
@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SoloLite
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6sl-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sl-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -1,36 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX6 SLL
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sll-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
|
||||
for the full list of i.MX6 SLL clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6sll-clock.h>
|
||||
|
||||
clks: clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sll-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
||||
};
|
||||
|
||||
uart1: serial@2020000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
|
||||
<&clks IMX6SLL_CLK_UART1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
65
Bindings/clock/imx6sll-clock.yaml
Normal file
65
Bindings/clock/imx6sll-clock.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SLL
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6sll-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ipp_di0 clock input
|
||||
- description: ipp_di1 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc
|
||||
- const: ipp_di0
|
||||
- const: ipp_di1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sll-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
||||
};
|
||||
@ -1,13 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX6 SoloX
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6sx-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
|
||||
for the full list of i.MX6 SoloX clock IDs.
|
||||
69
Bindings/clock/imx6sx-clock.yaml
Normal file
69
Bindings/clock/imx6sx-clock.yaml
Normal file
@ -0,0 +1,69 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 SoloX
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6sx-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ipp_di0 clock input
|
||||
- description: ipp_di1 clock input
|
||||
- description: anaclk1 clock input
|
||||
- description: anaclk2 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc
|
||||
- const: ipp_di0
|
||||
- const: ipp_di1
|
||||
- const: anaclk1
|
||||
- const: anaclk2
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6sx-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
|
||||
};
|
||||
@ -1,13 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX6 UltraLite
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx6ul-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
|
||||
for the full list of i.MX6 UltraLite clock IDs.
|
||||
65
Bindings/clock/imx6ul-clock.yaml
Normal file
65
Bindings/clock/imx6ul-clock.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX6 UltraLite
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx6ul-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
description: CCM provides 2 interrupt requests, request 1 is to generate
|
||||
interrupt for frequency or mux change, request 2 is to generate
|
||||
interrupt for oscillator read or PLL lock.
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
- description: ipp_di0 clock input
|
||||
- description: ipp_di1 clock input
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc
|
||||
- const: ipp_di0
|
||||
- const: ipp_di1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@20c4000 {
|
||||
compatible = "fsl,imx6ul-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
||||
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
||||
};
|
||||
@ -1,13 +0,0 @@
|
||||
* Clock bindings for Freescale i.MX7 Dual
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7d-ccm"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
- clocks: list of clock specifiers, must contain an entry for each required
|
||||
entry in clock-names
|
||||
- clock-names: should include entries "ckil", "osc"
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
|
||||
for the full list of i.MX7 Dual clock IDs.
|
||||
65
Bindings/clock/imx7d-clock.yaml
Normal file
65
Bindings/clock/imx7d-clock.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for Freescale i.MX7 Dual
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h
|
||||
for the full list of i.MX7 Dual clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx7d-ccm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: CCM interrupt request 1
|
||||
- description: CCM interrupt request 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 32k osc
|
||||
- description: 24m osc
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ckil
|
||||
- const: osc
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@30380000 {
|
||||
compatible = "fsl,imx7d-ccm";
|
||||
reg = <0x30380000 0x10000>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ckil>, <&osc>;
|
||||
clock-names = "ckil", "osc";
|
||||
};
|
||||
@ -1,51 +0,0 @@
|
||||
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
|
||||
|
||||
The Low-Power Clock Gate (LPCG) modules contain a local programming
|
||||
model to control the clock gates for the peripherals. An LPCG module
|
||||
is used to locally gate the clocks for the associated peripheral.
|
||||
|
||||
Note:
|
||||
This level of clock gating is provided after the clocks are generated
|
||||
by the SCU resources and clock controls. Thus even if the clock is
|
||||
enabled by these control bits, it might still not be running based
|
||||
on the base resource.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"fsl,imx8qxp-lpcg-adma",
|
||||
"fsl,imx8qxp-lpcg-conn",
|
||||
"fsl,imx8qxp-lpcg-dc",
|
||||
"fsl,imx8qxp-lpcg-dsp",
|
||||
"fsl,imx8qxp-lpcg-gpu",
|
||||
"fsl,imx8qxp-lpcg-hsio",
|
||||
"fsl,imx8qxp-lpcg-img",
|
||||
"fsl,imx8qxp-lpcg-lsio",
|
||||
"fsl,imx8qxp-lpcg-vpu"
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell.
|
||||
See the full list of clock IDs from:
|
||||
include/dt-bindings/clock/imx8qxp-clock.h
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx8qxp-clock.h>
|
||||
|
||||
conn_lpcg: clock-controller@5b200000 {
|
||||
compatible = "fsl,imx8qxp-lpcg-conn";
|
||||
reg = <0x5b200000 0xb0000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usdhc1: mmc@5b010000 {
|
||||
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x5b010000 0x10000>;
|
||||
clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
|
||||
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
|
||||
<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
|
||||
clock-names = "ipg", "per", "ahb";
|
||||
};
|
||||
73
Bindings/clock/imx8qxp-lpcg.yaml
Normal file
73
Bindings/clock/imx8qxp-lpcg.yaml
Normal file
@ -0,0 +1,73 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
|
||||
|
||||
maintainers:
|
||||
- Aisheng Dong <aisheng.dong@nxp.com>
|
||||
|
||||
description: |
|
||||
The Low-Power Clock Gate (LPCG) modules contain a local programming
|
||||
model to control the clock gates for the peripherals. An LPCG module
|
||||
is used to locally gate the clocks for the associated peripheral.
|
||||
|
||||
This level of clock gating is provided after the clocks are generated
|
||||
by the SCU resources and clock controls. Thus even if the clock is
|
||||
enabled by these control bits, it might still not be running based
|
||||
on the base resource.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See the full list of clock IDs from:
|
||||
include/dt-bindings/clock/imx8-clock.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx8qxp-lpcg-adma
|
||||
- fsl,imx8qxp-lpcg-conn
|
||||
- fsl,imx8qxp-lpcg-dc
|
||||
- fsl,imx8qxp-lpcg-dsp
|
||||
- fsl,imx8qxp-lpcg-gpu
|
||||
- fsl,imx8qxp-lpcg-hsio
|
||||
- fsl,imx8qxp-lpcg-img
|
||||
- fsl,imx8qxp-lpcg-lsio
|
||||
- fsl,imx8qxp-lpcg-vpu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8-clock.h>
|
||||
#include <dt-bindings/firmware/imx/rsrc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
clock-controller@5b200000 {
|
||||
compatible = "fsl,imx8qxp-lpcg-conn";
|
||||
reg = <0x5b200000 0xb0000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mmc@5b010000 {
|
||||
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x5b010000 0x10000>;
|
||||
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
|
||||
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
|
||||
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
|
||||
clock-names = "ipg", "per", "ahb";
|
||||
power-domains = <&pd IMX_SC_R_SDHC_0>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user