Add support for the Atmel AT91SAM9G45 CPU.
Reviewed by: imp
This commit is contained in:
Andrew Turner
parent
045da1cf0e
commit
25d95ee2cc
@ -94,6 +94,7 @@ __FBSDID("$FreeBSD$");
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#include <arm/at91/at91_usartreg.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91sam9g20reg.h>
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#include <arm/at91/at91sam9g45reg.h>
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/* Page table for mapping proc0 zero page */
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#define KERNEL_PT_SYS 0
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@ -201,6 +202,17 @@ const struct pmap_devmap at91_devmap[] = {
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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/*
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* The next should be good for the 9G45.
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*/
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{
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/* Internal Memory 1MB */
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AT91SAM9G45_OHCI_BASE,
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AT91SAM9G45_OHCI_PA_BASE,
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0x00100000,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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@ -213,7 +225,7 @@ extern int memsize[];
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long
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at91_ramsize(void)
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{
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uint32_t cr, mr, *SDRAMC;
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uint32_t cr, mdr, mr, *SDRAMC;
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int banks, rows, cols, bw;
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#ifdef LINUX_BOOT_ABI
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/*
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@ -231,6 +243,24 @@ at91_ramsize(void)
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rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
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bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
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} else if (at91_cpu_is(AT91_T_SAM9G45)) {
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SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G45_DDRSDRC0_BASE);
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cr = SDRAMC[AT91SAM9G45_DDRSDRC_CR / 4];
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mdr = SDRAMC[AT91SAM9G45_DDRSDRC_MDR / 4];
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banks = 0;
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rows = ((cr & AT91SAM9G45_DDRSDRC_CR_NR_MASK) >> 2) + 11;
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cols = (cr & AT91SAM9G45_DDRSDRC_CR_NC_MASK) + 8;
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bw = (mdr & AT91SAM9G45_DDRSDRC_MDR_DBW_16) ? 1 : 2;
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/* Fix the calculation for DDR memory */
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mdr &= AT91SAM9G45_DDRSDRC_MDR_MASK;
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if (mdr & AT91SAM9G45_DDRSDRC_MDR_LPDDR1 ||
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mdr & AT91SAM9G45_DDRSDRC_MDR_DDR2) {
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/* The cols value is 1 higher for DDR */
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cols += 1;
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/* DDR has 4 internal banks. */
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banks = 2;
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}
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} else {
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/*
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* This should be good for the 9260, 9261, 9G20, 9G35 and 9X25
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272
sys/arm/at91/at91_pio_sam9g45.h
Normal file
272
sys/arm/at91/at91_pio_sam9g45.h
Normal file
@ -0,0 +1,272 @@
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/*-
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* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support - ROUSSET -
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* ----------------------------------------------------------------------------
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* Copyright (c) 2009, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*
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* From AT91LIB version 1.9 boards/at91sam9g45-ek/at91sam9g45/AT91SAM9G45.h
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PIO_SAM9G45_H
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#define ARM_AT91_AT91_PIO_SAM9G45_H
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#include <arm/at91/at91_pioreg.h>
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// *****************************************************************************
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// PIO DEFINITIONS FOR AT91SAM9G45
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// *****************************************************************************
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#define AT91C_PA0_MCI0_CK (AT91C_PIO_PA0) //
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#define AT91C_PA0_TCLK3 (AT91C_PIO_PA0) //
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#define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) //
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#define AT91C_PA1_TIOA3 (AT91C_PIO_PA1) //
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#define AT91C_PA10_ETX0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 0
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#define AT91C_PA11_ETX1 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 1
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#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0
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#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1
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#define AT91C_PA14_ETXEN (AT91C_PIO_PA14) // Ethernet MAC Transmit Enable
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#define AT91C_PA15_ERXDV (AT91C_PIO_PA15) // Ethernet MAC Receive Data Valid
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#define AT91C_PA16_ERXER (AT91C_PIO_PA16) // Ethernet MAC Receive Error
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#define AT91C_PA17_ETXCK_EREFCK (AT91C_PIO_PA17) // Ethernet MAC Transmit Clock/Reference Clock
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#define AT91C_PA18_EMDC (AT91C_PIO_PA18) // Ethernet MAC Management Data Clock
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#define AT91C_PA19_EMDIO (AT91C_PIO_PA19) // Ethernet MAC Management Data Input/Output
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#define AT91C_PA2_MCI0_DA0 (AT91C_PIO_PA2) //
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#define AT91C_PA2_TIOB3 (AT91C_PIO_PA2) //
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#define AT91C_PA20_TWD0 (AT91C_PIO_PA20) // TWI Two-wire Serial Data
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#define AT91C_PA21_TWCK0 (AT91C_PIO_PA21) // TWI Two-wire Serial Clock
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#define AT91C_PA22_MCI1_CDA (AT91C_PIO_PA22) //
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#define AT91C_PA22_SCK3 (AT91C_PIO_PA22) //
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#define AT91C_PA23_MCI1_DA0 (AT91C_PIO_PA23) //
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#define AT91C_PA23_RTS3 (AT91C_PIO_PA23) //
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#define AT91C_PA24_MCI1_DA1 (AT91C_PIO_PA24) //
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#define AT91C_PA24_CTS3 (AT91C_PIO_PA24) //
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#define AT91C_PA25_MCI1_DA2 (AT91C_PIO_PA25) //
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#define AT91C_PA25_PWM3 (AT91C_PIO_PA25) //
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#define AT91C_PA26_MCI1_DA3 (AT91C_PIO_PA26) //
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#define AT91C_PA26_TIOB2 (AT91C_PIO_PA26) //
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#define AT91C_PA27_MCI1_DA4 (AT91C_PIO_PA27) //
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#define AT91C_PA27_ETXER (AT91C_PIO_PA27) // Ethernet MAC Transmikt Coding Error
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#define AT91C_PA28_MCI1_DA5 (AT91C_PIO_PA28) //
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#define AT91C_PA28_ERXCK (AT91C_PIO_PA28) // Ethernet MAC Receive Clock
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#define AT91C_PA29_MCI1_DA6 (AT91C_PIO_PA29) //
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#define AT91C_PA29_ECRS (AT91C_PIO_PA29) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
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#define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) //
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#define AT91C_PA3_TCLK4 (AT91C_PIO_PA3) //
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#define AT91C_PA30_MCI1_DA7 (AT91C_PIO_PA30) //
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#define AT91C_PA30_ECOL (AT91C_PIO_PA30) // Ethernet MAC Collision Detected
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#define AT91C_PA31_MCI1_CK (AT91C_PIO_PA31) //
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#define AT91C_PA31_PCK0 (AT91C_PIO_PA31) //
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#define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) //
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#define AT91C_PA4_TIOA4 (AT91C_PIO_PA4) //
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#define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) //
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#define AT91C_PA5_TIOB4 (AT91C_PIO_PA5) //
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#define AT91C_PA6_MCI0_DA4 (AT91C_PIO_PA6) //
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#define AT91C_PA6_ETX2 (AT91C_PIO_PA6) // Ethernet MAC Transmit Data 2
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#define AT91C_PA7_MCI0_DA5 (AT91C_PIO_PA7) //
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#define AT91C_PA7_ETX3 (AT91C_PIO_PA7) // Ethernet MAC Transmit Data 3
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#define AT91C_PA8_MCI0_DA6 (AT91C_PIO_PA8) //
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#define AT91C_PA8_ERX2 (AT91C_PIO_PA8) // Ethernet MAC Receive Data 2
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#define AT91C_PA9_MCI0_DA7 (AT91C_PIO_PA9) //
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#define AT91C_PA9_ERX3 (AT91C_PIO_PA9) // Ethernet MAC Receive Data 3
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#define AT91C_PB0_SPI0_MISO (AT91C_PIO_PB0) // SPI 0 Master In Slave
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#define AT91C_PB1_SPI0_MOSI (AT91C_PIO_PB1) // SPI 0 Master Out Slave
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#define AT91C_PB10_TWD1 (AT91C_PIO_PB10) //
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#define AT91C_PB10_ISI_D10 (AT91C_PIO_PB10) //
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#define AT91C_PB11_TWCK1 (AT91C_PIO_PB11) //
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#define AT91C_PB11_ISI_D11 (AT91C_PIO_PB11) //
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#define AT91C_PB12_DRXD (AT91C_PIO_PB12) //
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#define AT91C_PB13_DTXD (AT91C_PIO_PB13) //
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#define AT91C_PB14_SPI1_MISO (AT91C_PIO_PB14) //
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#define AT91C_PB15_SPI1_MOSI (AT91C_PIO_PB15) //
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#define AT91C_PB15_CTS0 (AT91C_PIO_PB15) //
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#define AT91C_PB16_SPI1_SPCK (AT91C_PIO_PB16) //
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#define AT91C_PB16_SCK0 (AT91C_PIO_PB16) //
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#define AT91C_PB17_SPI1_NPCS0 (AT91C_PIO_PB17) //
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#define AT91C_PB17_RTS0 (AT91C_PIO_PB17) //
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#define AT91C_PB18_RXD0 (AT91C_PIO_PB18) //
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#define AT91C_PB18_SPI0_NPCS1 (AT91C_PIO_PB18) //
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#define AT91C_PB19_TXD0 (AT91C_PIO_PB19) //
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#define AT91C_PB19_SPI0_NPCS2 (AT91C_PIO_PB19) //
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#define AT91C_PB2_SPI0_SPCK (AT91C_PIO_PB2) // SPI 0 Serial Clock
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#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) //
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#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) //
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#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) //
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#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) //
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#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) //
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#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) //
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#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) //
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#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) //
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#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) //
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#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) //
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#define AT91C_PB3_SPI0_NPCS0 (AT91C_PIO_PB3) // SPI 0 Peripheral Chip Select 0
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#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) //
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#define AT91C_PB31_ (AT91C_PIO_PB31) //
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#define AT91C_PB31_PCK1 (AT91C_PIO_PB31) //
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#define AT91C_PB4_TXD1 (AT91C_PIO_PB4) // USART 1 Transmit Data
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#define AT91C_PB5_RXD1 (AT91C_PIO_PB5) // USART 1 Receive Data
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#define AT91C_PB6_TXD2 (AT91C_PIO_PB6) // USART 2 Transmit Data
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#define AT91C_PB7_RXD2 (AT91C_PIO_PB7) // USART 2 Receive Data
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#define AT91C_PB8_TXD3 (AT91C_PIO_PB8) // USART 3 Transmit Data
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#define AT91C_PB8_ISI_D8 (AT91C_PIO_PB8) //
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#define AT91C_PB9_RXD3 (AT91C_PIO_PB9) // USART 3 Receive Data
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#define AT91C_PB9_ISI_D9 (AT91C_PIO_PB9) //
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#define AT91C_PC0_DQM2 (AT91C_PIO_PC0) // DQM2
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#define AT91C_PC1_DQM3 (AT91C_PIO_PC1) // DQM3
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#define AT91C_PC10_NCS4_CFCS0 (AT91C_PIO_PC10) //
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#define AT91C_PC10_TCLK2 (AT91C_PIO_PC10) //
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#define AT91C_PC11_NCS5_CFCS1 (AT91C_PIO_PC11) //
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#define AT91C_PC11_CTS2 (AT91C_PIO_PC11) //
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#define AT91C_PC12_A25_CFRNW (AT91C_PIO_PC12) //
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#define AT91C_PC13_NCS2 (AT91C_PIO_PC13) //
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#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) //
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#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) //
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#define AT91C_PC16_D16 (AT91C_PIO_PC16) //
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#define AT91C_PC17_D17 (AT91C_PIO_PC17) //
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#define AT91C_PC18_D18 (AT91C_PIO_PC18) //
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#define AT91C_PC19_D19 (AT91C_PIO_PC19) //
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#define AT91C_PC2_A19 (AT91C_PIO_PC2) //
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#define AT91C_PC20_D20 (AT91C_PIO_PC20) //
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#define AT91C_PC21_D21 (AT91C_PIO_PC21) //
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#define AT91C_PC22_D22 (AT91C_PIO_PC22) //
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#define AT91C_PC23_D23 (AT91C_PIO_PC23) //
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#define AT91C_PC24_D24 (AT91C_PIO_PC24) //
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#define AT91C_PC25_D25 (AT91C_PIO_PC25) //
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#define AT91C_PC26_D26 (AT91C_PIO_PC26) //
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#define AT91C_PC27_D27 (AT91C_PIO_PC27) //
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#define AT91C_PC28_D28 (AT91C_PIO_PC28) //
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#define AT91C_PC29_D29 (AT91C_PIO_PC29) //
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#define AT91C_PC3_A20 (AT91C_PIO_PC3) //
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#define AT91C_PC30_D30 (AT91C_PIO_PC30) //
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#define AT91C_PC31_D31 (AT91C_PIO_PC31) //
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#define AT91C_PC4_A21_NANDALE (AT91C_PIO_PC4) //
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#define AT91C_PC5_A22_NANDCLE (AT91C_PIO_PC5) //
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#define AT91C_PC6_A23 (AT91C_PIO_PC6) //
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#define AT91C_PC7_A24 (AT91C_PIO_PC7) //
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#define AT91C_PC8_CFCE1 (AT91C_PIO_PC8) //
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#define AT91C_PC9_CFCE2 (AT91C_PIO_PC9) //
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#define AT91C_PC9_RTS2 (AT91C_PIO_PC9) //
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#define AT91C_PD0_TK0 (AT91C_PIO_PD0) //
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#define AT91C_PD0_PWM3 (AT91C_PIO_PD0) //
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#define AT91C_PD1_TF0 (AT91C_PIO_PD1) //
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#define AT91C_PD10_TD1 (AT91C_PIO_PD10) //
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#define AT91C_PD11_RD1 (AT91C_PIO_PD11) //
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#define AT91C_PD12_TK1 (AT91C_PIO_PD12) //
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#define AT91C_PD12_PCK0 (AT91C_PIO_PD12) //
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#define AT91C_PD13_RK1 (AT91C_PIO_PD13) //
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#define AT91C_PD14_TF1 (AT91C_PIO_PD14) //
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#define AT91C_PD15_RF1 (AT91C_PIO_PD15) //
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#define AT91C_PD16_RTS1 (AT91C_PIO_PD16) //
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#define AT91C_PD17_CTS1 (AT91C_PIO_PD17) //
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#define AT91C_PD18_SPI1_NPCS2 (AT91C_PIO_PD18) //
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#define AT91C_PD18_IRQ (AT91C_PIO_PD18) //
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#define AT91C_PD19_SPI1_NPCS3 (AT91C_PIO_PD19) //
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#define AT91C_PD19_FIQ (AT91C_PIO_PD19) //
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#define AT91C_PD2_TD0 (AT91C_PIO_PD2) //
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#define AT91C_PD20_TIOA0 (AT91C_PIO_PD20) //
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#define AT91C_PD21_TIOA1 (AT91C_PIO_PD21) //
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#define AT91C_PD22_TIOA2 (AT91C_PIO_PD22) //
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#define AT91C_PD23_TCLK0 (AT91C_PIO_PD23) //
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#define AT91C_PD24_SPI0_NPCS1 (AT91C_PIO_PD24) //
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#define AT91C_PD24_PWM0 (AT91C_PIO_PD24) //
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#define AT91C_PD25_SPI0_NPCS2 (AT91C_PIO_PD25) //
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#define AT91C_PD25_PWM1 (AT91C_PIO_PD25) //
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#define AT91C_PD26_PCK0 (AT91C_PIO_PD26) //
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#define AT91C_PD26_PWM2 (AT91C_PIO_PD26) //
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#define AT91C_PD27_PCK1 (AT91C_PIO_PD27) //
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#define AT91C_PD27_SPI0_NPCS3 (AT91C_PIO_PD27) //
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#define AT91C_PD28_TSADTRG (AT91C_PIO_PD28) //
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#define AT91C_PD28_SPI1_NPCS1 (AT91C_PIO_PD28) //
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#define AT91C_PD29_TCLK1 (AT91C_PIO_PD29) //
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#define AT91C_PD29_SCK1 (AT91C_PIO_PD29) //
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#define AT91C_PD3_RD0 (AT91C_PIO_PD3) //
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#define AT91C_PD30_TIOB0 (AT91C_PIO_PD30) //
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#define AT91C_PD30_SCK2 (AT91C_PIO_PD30) //
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#define AT91C_PD31_TIOB1 (AT91C_PIO_PD31) //
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#define AT91C_PD31_PWM1 (AT91C_PIO_PD31) //
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#define AT91C_PD4_RK0 (AT91C_PIO_PD4) //
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#define AT91C_PD5_RF0 (AT91C_PIO_PD5) //
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#define AT91C_PD6_AC97RX (AT91C_PIO_PD6) //
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#define AT91C_PD7_AC97TX (AT91C_PIO_PD7) //
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#define AT91C_PD7_TIOA5 (AT91C_PIO_PD7) //
|
||||
#define AT91C_PD8_AC97FS (AT91C_PIO_PD8) //
|
||||
#define AT91C_PD8_TIOB5 (AT91C_PIO_PD8) //
|
||||
#define AT91C_PD9_AC97CK (AT91C_PIO_PD9) //
|
||||
#define AT91C_PD9_TCLK5 (AT91C_PIO_PD9) //
|
||||
#define AT91C_PE0_LCDPWR (AT91C_PIO_PE0) //
|
||||
#define AT91C_PE0_PCK0 (AT91C_PIO_PE0) //
|
||||
#define AT91C_PE1_LCDMOD (AT91C_PIO_PE1) //
|
||||
#define AT91C_PE10_LCDD3 (AT91C_PIO_PE10) //
|
||||
#define AT91C_PE10_LCDD5 (AT91C_PIO_PE10) //
|
||||
#define AT91C_PE11_LCDD4 (AT91C_PIO_PE11) //
|
||||
#define AT91C_PE11_LCDD6 (AT91C_PIO_PE11) //
|
||||
#define AT91C_PE12_LCDD5 (AT91C_PIO_PE12) //
|
||||
#define AT91C_PE12_LCDD7 (AT91C_PIO_PE12) //
|
||||
#define AT91C_PE13_LCDD6 (AT91C_PIO_PE13) //
|
||||
#define AT91C_PE13_LCDD10 (AT91C_PIO_PE13) //
|
||||
#define AT91C_PE14_LCDD7 (AT91C_PIO_PE14) //
|
||||
#define AT91C_PE14_LCDD11 (AT91C_PIO_PE14) //
|
||||
#define AT91C_PE15_LCDD8 (AT91C_PIO_PE15) //
|
||||
#define AT91C_PE15_LCDD12 (AT91C_PIO_PE15) //
|
||||
#define AT91C_PE16_LCDD9 (AT91C_PIO_PE16) //
|
||||
#define AT91C_PE16_LCDD13 (AT91C_PIO_PE16) //
|
||||
#define AT91C_PE17_LCDD10 (AT91C_PIO_PE17) //
|
||||
#define AT91C_PE17_LCDD14 (AT91C_PIO_PE17) //
|
||||
#define AT91C_PE18_LCDD11 (AT91C_PIO_PE18) //
|
||||
#define AT91C_PE18_LCDD15 (AT91C_PIO_PE18) //
|
||||
#define AT91C_PE19_LCDD12 (AT91C_PIO_PE19) //
|
||||
#define AT91C_PE19_LCDD18 (AT91C_PIO_PE19) //
|
||||
#define AT91C_PE2_LCDCC (AT91C_PIO_PE2) //
|
||||
#define AT91C_PE20_LCDD13 (AT91C_PIO_PE20) //
|
||||
#define AT91C_PE20_LCDD19 (AT91C_PIO_PE20) //
|
||||
#define AT91C_PE21_LCDD14 (AT91C_PIO_PE21) //
|
||||
#define AT91C_PE21_LCDD20 (AT91C_PIO_PE21) //
|
||||
#define AT91C_PE22_LCDD15 (AT91C_PIO_PE22) //
|
||||
#define AT91C_PE22_LCDD21 (AT91C_PIO_PE22) //
|
||||
#define AT91C_PE23_LCDD16 (AT91C_PIO_PE23) //
|
||||
#define AT91C_PE23_LCDD22 (AT91C_PIO_PE23) //
|
||||
#define AT91C_PE24_LCDD17 (AT91C_PIO_PE24) //
|
||||
#define AT91C_PE24_LCDD23 (AT91C_PIO_PE24) //
|
||||
#define AT91C_PE25_LCDD18 (AT91C_PIO_PE25) //
|
||||
#define AT91C_PE26_LCDD19 (AT91C_PIO_PE26) //
|
||||
#define AT91C_PE27_LCDD20 (AT91C_PIO_PE27) //
|
||||
#define AT91C_PE28_LCDD21 (AT91C_PIO_PE28) //
|
||||
#define AT91C_PE29_LCDD22 (AT91C_PIO_PE29) //
|
||||
#define AT91C_PE3_LCDVSYNC (AT91C_PIO_PE3) //
|
||||
#define AT91C_PE30_LCDD23 (AT91C_PIO_PE30) //
|
||||
#define AT91C_PE31_PWM2 (AT91C_PIO_PE31) //
|
||||
#define AT91C_PE31_PCK1 (AT91C_PIO_PE31) //
|
||||
#define AT91C_PE4_LCDHSYNC (AT91C_PIO_PE4) //
|
||||
#define AT91C_PE5_LCDDOTCK (AT91C_PIO_PE5) //
|
||||
#define AT91C_PE6_LCDDEN (AT91C_PIO_PE6) //
|
||||
#define AT91C_PE7_LCDD0 (AT91C_PIO_PE7) //
|
||||
#define AT91C_PE7_LCDD2 (AT91C_PIO_PE7) //
|
||||
#define AT91C_PE8_LCDD1 (AT91C_PIO_PE8) //
|
||||
#define AT91C_PE8_LCDD3 (AT91C_PIO_PE8) //
|
||||
#define AT91C_PE9_LCDD2 (AT91C_PIO_PE9) //
|
||||
#define AT91C_PE9_LCDD4 (AT91C_PIO_PE9) //
|
||||
|
||||
#endif /* ARM_AT91_AT91_PIO_SAM9G45_H */
|
||||
@ -65,6 +65,7 @@ MALLOC_DEFINE(M_PMC, "at91_pmc_clocks", "AT91 PMC Clock descriptors");
|
||||
#define AT91_PMC_BASE 0xffffc00
|
||||
|
||||
static void at91_pmc_set_pllb_mode(struct at91_pmc_clock *, int);
|
||||
static void at91_pmc_set_upll_mode(struct at91_pmc_clock *, int);
|
||||
static void at91_pmc_set_sys_mode(struct at91_pmc_clock *, int);
|
||||
static void at91_pmc_set_periph_mode(struct at91_pmc_clock *, int);
|
||||
static void at91_pmc_clock_alias(const char *name, const char *alias);
|
||||
@ -110,6 +111,18 @@ static struct at91_pmc_clock pllb = {
|
||||
.set_mode = &at91_pmc_set_pllb_mode,
|
||||
};
|
||||
|
||||
/* Used by USB on at91sam9g45 */
|
||||
static struct at91_pmc_clock upll = {
|
||||
.name = "upll", // UTMI PLL, used for USB functions on 9G45
|
||||
.parent = &main_ck,
|
||||
.refcnt = 0,
|
||||
.id = 0,
|
||||
.primary = 1,
|
||||
.pll = 1,
|
||||
.pmc_mask = (1 << 6),
|
||||
.set_mode = &at91_pmc_set_upll_mode,
|
||||
};
|
||||
|
||||
static struct at91_pmc_clock udpck = {
|
||||
.name = "udpck",
|
||||
.parent = &pllb,
|
||||
@ -143,6 +156,7 @@ static struct at91_pmc_clock *clock_list[16+32] = {
|
||||
&main_ck,
|
||||
&plla,
|
||||
&pllb,
|
||||
&upll,
|
||||
&udpck,
|
||||
&uhpck,
|
||||
&mck,
|
||||
@ -198,6 +212,26 @@ at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
|
||||
continue;
|
||||
}
|
||||
|
||||
static void
|
||||
at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
|
||||
{
|
||||
struct at91_pmc_softc *sc = pmc_softc;
|
||||
uint32_t value;
|
||||
|
||||
if (on) {
|
||||
on = PMC_IER_LOCKU;
|
||||
value = CKGR_UCKR_UPLLEN | CKGR_UCKR_BIASEN;
|
||||
} else
|
||||
value = 0;
|
||||
|
||||
WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value);
|
||||
while ((RD4(sc, PMC_SR) & PMC_IER_LOCKU) != on)
|
||||
continue;
|
||||
|
||||
WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS);
|
||||
WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9);
|
||||
}
|
||||
|
||||
static void
|
||||
at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
|
||||
{
|
||||
@ -466,6 +500,12 @@ at91_pmc_init_clock(void)
|
||||
uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
|
||||
udpck.pmc_mask = PMC_SCER_UDP_SAM9;
|
||||
}
|
||||
/* There is no pllb on AT91SAM9G45 */
|
||||
if (at91_cpu_is(AT91_T_SAM9G45)) {
|
||||
uhpck.parent = &upll;
|
||||
uhpck.pmc_mask = PMC_SCER_UHP_SAM9;
|
||||
}
|
||||
|
||||
mckr = RD4(sc, PMC_MCKR);
|
||||
main_ck.hz = main_clock;
|
||||
|
||||
@ -506,8 +546,14 @@ at91_pmc_init_clock(void)
|
||||
|
||||
mdiv = (mckr & PMC_MCKR_MDIV_MASK) >> 8;
|
||||
if (at91_is_sam9() || at91_is_sam9xe()) {
|
||||
/*
|
||||
* On AT91SAM9G45 when mdiv == 3 we need to divide
|
||||
* MCK by 3 but not, for example, on 9g20.
|
||||
*/
|
||||
if (!at91_cpu_is(AT91_T_SAM9G45) || mdiv <= 2)
|
||||
mdiv *= 2;
|
||||
if (mdiv > 0)
|
||||
mck.hz /= mdiv * 2;
|
||||
mck.hz /= mdiv;
|
||||
} else
|
||||
mck.hz /= (1 + mdiv);
|
||||
|
||||
|
||||
@ -36,14 +36,14 @@
|
||||
#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
|
||||
#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
|
||||
#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
|
||||
/* 0x1c reserved */
|
||||
#define CKGR_UCKR 0x1c /* UTMI Clock Configuration Register */
|
||||
#define CKGR_MOR 0x20 /* Main Oscillator Register */
|
||||
#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */
|
||||
#define CKGR_PLLAR 0x28 /* PLL A Register */
|
||||
#define CKGR_PLLBR 0x2c /* PLL B Register */
|
||||
#define PMC_MCKR 0x30 /* Master Clock Register */
|
||||
/* 0x34 reserved */
|
||||
/* 0x38 reserved */
|
||||
#define PMC_USB 0x38 /* USB Clock Register */
|
||||
/* 0x3c reserved */
|
||||
#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */
|
||||
#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */
|
||||
@ -77,6 +77,10 @@
|
||||
/* PMC Peripheral Clock Status Register */
|
||||
/* Each bit here is 1 << peripheral number to enable/disable/status */
|
||||
|
||||
/* PMC UTMI Clock Configuration Register */
|
||||
#define CKGR_UCKR_BIASEN (1UL << 24)
|
||||
#define CKGR_UCKR_UPLLEN (1UL << 16)
|
||||
|
||||
/* PMC Clock Generator Main Oscillator Register */
|
||||
#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */
|
||||
#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */
|
||||
@ -93,6 +97,10 @@
|
||||
#define PMC_MCKR_MDIV_MASK (3 << 8)
|
||||
#define PMC_MCKR_PRES_MASK (7 << 2)
|
||||
|
||||
/* PMC USB Clock Register */
|
||||
#define PMC_USB_USBDIV(n) (((n) & 0x0F) << 8)
|
||||
#define PMC_USB_USBS (1 << 0)
|
||||
|
||||
/* PMC Interrupt Enable Register */
|
||||
/* PMC Interrupt Disable Register */
|
||||
/* PMC Status Register */
|
||||
@ -101,6 +109,7 @@
|
||||
#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */
|
||||
#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */
|
||||
#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */
|
||||
#define PMC_IER_LOCKU (1UL << 6) /* UPLL Locked */
|
||||
#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */
|
||||
#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */
|
||||
#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */
|
||||
|
||||
177
sys/arm/at91/at91sam9g45.c
Normal file
177
sys/arm/at91/at91sam9g45.c
Normal file
@ -0,0 +1,177 @@
|
||||
/*-
|
||||
* Copyright (c) 2005 Olivier Houchard. All rights reserved.
|
||||
* Copyright (c) 2010 Greg Ansley. All rights reserved.
|
||||
* Copyright (c) 2012 Andrew Turner. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
|
||||
#define _ARM32_BUS_DMA_PRIVATE
|
||||
#include <machine/bus.h>
|
||||
|
||||
#include <arm/at91/at91var.h>
|
||||
#include <arm/at91/at91reg.h>
|
||||
#include <arm/at91/at91soc.h>
|
||||
#include <arm/at91/at91_aicreg.h>
|
||||
#include <arm/at91/at91sam9g45reg.h>
|
||||
#include <arm/at91/at91_pitreg.h>
|
||||
#include <arm/at91/at91_pmcreg.h>
|
||||
#include <arm/at91/at91_pmcvar.h>
|
||||
#include <arm/at91/at91_rstreg.h>
|
||||
|
||||
/*
|
||||
* Standard priority levels for the system. 0 is lowest and 7 is highest.
|
||||
* These values are the ones Atmel uses for its Linux port
|
||||
*/
|
||||
static const int at91_irq_prio[32] =
|
||||
{
|
||||
7, /* Advanced Interrupt Controller */
|
||||
7, /* System Peripherals */
|
||||
1, /* Parallel IO Controller A */
|
||||
1, /* Parallel IO Controller B */
|
||||
1, /* Parallel IO Controller C */
|
||||
1, /* Parallel IO Controller D and E */
|
||||
0,
|
||||
5, /* USART 0 */
|
||||
5, /* USART 1 */
|
||||
5, /* USART 2 */
|
||||
5, /* USART 3 */
|
||||
0, /* Multimedia Card Interface 0 */
|
||||
6, /* Two-Wire Interface 0 */
|
||||
6, /* Two-Wire Interface 1 */
|
||||
5, /* Serial Peripheral Interface 0 */
|
||||
5, /* Serial Peripheral Interface 1 */
|
||||
4, /* Serial Synchronous Controller 0 */
|
||||
4, /* Serial Synchronous Controller 1 */
|
||||
0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
|
||||
0, /* Pulse Width Modulation Controller */
|
||||
0, /* Touch Screen Controller */
|
||||
0, /* DMA Controller */
|
||||
2, /* USB Host High Speed port */
|
||||
3, /* LCD Controller */
|
||||
5, /* AC97 Controller */
|
||||
3, /* Ethernet */
|
||||
0, /* Image Sensor Interface */
|
||||
2, /* USB Device High Speed port */
|
||||
0, /* (reserved) */
|
||||
0, /* Multimedia Card Interface 1 */
|
||||
0, /* (reserved) */
|
||||
0, /* Advanced Interrupt Controller IRQ0 */
|
||||
};
|
||||
|
||||
#define DEVICE(_name, _id, _unit) \
|
||||
{ \
|
||||
_name, _unit, \
|
||||
AT91SAM9G45_ ## _id ##_BASE, \
|
||||
AT91SAM9G45_ ## _id ## _SIZE, \
|
||||
AT91SAM9G45_IRQ_ ## _id \
|
||||
}
|
||||
|
||||
static const struct cpu_devs at91_devs[] =
|
||||
{
|
||||
DEVICE("at91_pmc", PMC, 0),
|
||||
DEVICE("at91_wdt", WDT, 0),
|
||||
DEVICE("at91_rst", RSTC, 0),
|
||||
DEVICE("at91_pit", PIT, 0),
|
||||
DEVICE("at91_pio", PIOA, 0),
|
||||
DEVICE("at91_pio", PIOB, 1),
|
||||
DEVICE("at91_pio", PIOC, 2),
|
||||
DEVICE("at91_pio", PIOD, 3),
|
||||
DEVICE("at91_pio", PIOE, 4),
|
||||
DEVICE("at91_twi", TWI0, 0),
|
||||
DEVICE("at91_twi", TWI1, 1),
|
||||
DEVICE("at91_mci", HSMCI0, 0),
|
||||
DEVICE("at91_mci", HSMCI1, 1),
|
||||
DEVICE("uart", DBGU, 0),
|
||||
DEVICE("uart", USART0, 1),
|
||||
DEVICE("uart", USART1, 2),
|
||||
DEVICE("uart", USART2, 3),
|
||||
DEVICE("uart", USART3, 4),
|
||||
DEVICE("spi", SPI0, 0),
|
||||
DEVICE("spi", SPI1, 1),
|
||||
DEVICE("ate", EMAC, 0),
|
||||
DEVICE("macb", EMAC, 0),
|
||||
DEVICE("nand", NAND, 0),
|
||||
DEVICE("ohci", OHCI, 0),
|
||||
{ 0, 0, 0, 0, 0 }
|
||||
};
|
||||
|
||||
static uint32_t
|
||||
at91_pll_outa(int freq)
|
||||
{
|
||||
|
||||
switch (freq / 10000000) {
|
||||
case 747 ... 801: return ((1 << 29) | (0 << 14));
|
||||
case 697 ... 746: return ((1 << 29) | (1 << 14));
|
||||
case 647 ... 696: return ((1 << 29) | (2 << 14));
|
||||
case 597 ... 646: return ((1 << 29) | (3 << 14));
|
||||
case 547 ... 596: return ((1 << 29) | (4 << 14));
|
||||
case 497 ... 546: return ((1 << 29) | (5 << 14));
|
||||
case 447 ... 496: return ((1 << 29) | (6 << 14));
|
||||
case 397 ... 446: return ((1 << 29) | (7 << 14));
|
||||
default: return (1 << 29);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
at91_clock_init(void)
|
||||
{
|
||||
struct at91_pmc_clock *clk;
|
||||
|
||||
/* Update USB host port clock info */
|
||||
clk = at91_pmc_clock_ref("uhpck");
|
||||
clk->pmc_mask = PMC_SCER_UHP_SAM9;
|
||||
at91_pmc_clock_deref(clk);
|
||||
|
||||
/* Each SOC has different PLL contraints */
|
||||
clk = at91_pmc_clock_ref("plla");
|
||||
clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */
|
||||
clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */
|
||||
clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
|
||||
clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
|
||||
clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT;
|
||||
clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK;
|
||||
clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT;
|
||||
clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK;
|
||||
clk->set_outb = at91_pll_outa;
|
||||
at91_pmc_clock_deref(clk);
|
||||
}
|
||||
|
||||
static struct at91_soc_data soc_data = {
|
||||
.soc_delay = at91_pit_delay,
|
||||
.soc_reset = at91_rst_cpu_reset,
|
||||
.soc_clock_init = at91_clock_init,
|
||||
.soc_irq_prio = at91_irq_prio,
|
||||
.soc_children = at91_devs,
|
||||
};
|
||||
|
||||
AT91_SOC(AT91_T_SAM9G45, &soc_data);
|
||||
294
sys/arm/at91/at91sam9g45reg.h
Normal file
294
sys/arm/at91/at91sam9g45reg.h
Normal file
@ -0,0 +1,294 @@
|
||||
/*-
|
||||
* Copyright (c) 2009 Sylvestre Gallon. All rights reserved.
|
||||
* Copyright (c) 2010 Greg Ansley. All rights reserved.
|
||||
* Copyright (c) 2012 Andrew Turner. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
#ifndef AT91SAM9G45REG_H_
|
||||
#define AT91SAM9G45REG_H_
|
||||
|
||||
/* Chip Specific limits */
|
||||
#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */
|
||||
#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */
|
||||
#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */
|
||||
#define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */
|
||||
#define SAM9G45_PLL_A_MUL_SHIFT 16
|
||||
#define SAM9G45_PLL_A_MUL_MASK 0xFF
|
||||
#define SAM9G45_PLL_A_DIV_SHIFT 0
|
||||
#define SAM9G45_PLL_A_DIV_MASK 0xFF
|
||||
|
||||
/*
|
||||
* Memory map, from datasheet :
|
||||
* 0x00000000 - 0x0ffffffff : Internal Memories
|
||||
* 0x10000000 - 0x1ffffffff : Chip Select 0
|
||||
* 0x20000000 - 0x2ffffffff : Chip Select 1
|
||||
* 0x30000000 - 0x3ffffffff : Chip Select 2
|
||||
* 0x40000000 - 0x4ffffffff : Chip Select 3
|
||||
* 0x50000000 - 0x5ffffffff : Chip Select 4
|
||||
* 0x60000000 - 0x6ffffffff : Chip Select 5
|
||||
* 0x70000000 - 0x7ffffffff : DDR SDRC 0
|
||||
* 0x80000000 - 0xeffffffff : Undefined (Abort)
|
||||
* 0xf0000000 - 0xfffffffff : Peripherals
|
||||
*/
|
||||
|
||||
#define AT91_CHIPSELECT_0 0x10000000
|
||||
#define AT91_CHIPSELECT_1 0x20000000
|
||||
#define AT91_CHIPSELECT_2 0x30000000
|
||||
#define AT91_CHIPSELECT_3 0x40000000
|
||||
#define AT91_CHIPSELECT_4 0x50000000
|
||||
#define AT91_CHIPSELECT_5 0x60000000
|
||||
|
||||
|
||||
#define AT91SAM9G45_EMAC_BASE 0xffbc000
|
||||
#define AT91SAM9G45_EMAC_SIZE 0x4000
|
||||
|
||||
#define AT91SAM9G45_RSTC_BASE 0xffffd00
|
||||
#define AT91SAM9G45_RSTC_SIZE 0x10
|
||||
|
||||
/* USART*/
|
||||
|
||||
#define AT91SAM9G45_USART_SIZE 0x4000
|
||||
#define AT91SAM9G45_USART0_BASE 0xff8c000
|
||||
#define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE
|
||||
#define AT91SAM9G45_USART1_BASE 0xff90000
|
||||
#define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE
|
||||
#define AT91SAM9G45_USART2_BASE 0xff94000
|
||||
#define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE
|
||||
#define AT91SAM9G45_USART3_BASE 0xff98000
|
||||
#define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE
|
||||
|
||||
/*TC*/
|
||||
#define AT91SAM9G45_TC0_BASE 0xff7c000
|
||||
#define AT91SAM9G45_TC0_SIZE 0x4000
|
||||
#define AT91SAM9G45_TC0C0_BASE 0xff7c000
|
||||
#define AT91SAM9G45_TC0C1_BASE 0xff7c040
|
||||
#define AT91SAM9G45_TC0C2_BASE 0xff7c080
|
||||
|
||||
#define AT91SAM9G45_TC1_BASE 0xffd4000
|
||||
#define AT91SAM9G45_TC1_SIZE 0x4000
|
||||
#define AT91SAM9G45_TC1C0_BASE 0xffd4000
|
||||
#define AT91SAM9G45_TC1C1_BASE 0xffd4040
|
||||
#define AT91SAM9G45_TC1C2_BASE 0xffd4080
|
||||
|
||||
/*SPI*/
|
||||
|
||||
#define AT91SAM9G45_SPI0_BASE 0xffa48000
|
||||
#define AT91SAM9G45_SPI0_SIZE 0x4000
|
||||
|
||||
#define AT91SAM9G45_SPI1_BASE 0xffa8000
|
||||
#define AT91SAM9G45_SPI1_SIZE 0x4000
|
||||
|
||||
/* System Registers */
|
||||
#define AT91SAM9G45_SYS_BASE 0xffff000
|
||||
#define AT91SAM9G45_SYS_SIZE 0x1000
|
||||
|
||||
#define AT91SAM9G45_MATRIX_BASE 0xfffea00
|
||||
#define AT91SAM9G45_MATRIX_SIZE 0x200
|
||||
|
||||
#define AT91SAM9G45_DBGU_BASE 0xfffee00
|
||||
#define AT91SAM9G45_DBGU_SIZE 0x200
|
||||
|
||||
/*
|
||||
* PIO
|
||||
*/
|
||||
#define AT91SAM9G45_PIOA_BASE 0xffff200
|
||||
#define AT91SAM9G45_PIOA_SIZE 0x200
|
||||
#define AT91SAM9G45_PIOB_BASE 0xffff400
|
||||
#define AT91SAM9G45_PIOB_SIZE 0x200
|
||||
#define AT91SAM9G45_PIOC_BASE 0xffff600
|
||||
#define AT91SAM9G45_PIOC_SIZE 0x200
|
||||
#define AT91SAM9G45_PIOD_BASE 0xffff800
|
||||
#define AT91SAM9G45_PIOD_SIZE 0x200
|
||||
#define AT91SAM9G45_PIOE_BASE 0xffffa00
|
||||
#define AT91SAM9G45_PIOE_SIZE 0x200
|
||||
|
||||
#define AT91SAM9G45_PMC_BASE 0xffffc00
|
||||
#define AT91SAM9G45_PMC_SIZE 0x100
|
||||
|
||||
/* IRQs : */
|
||||
/*
|
||||
* 0: AIC
|
||||
* 1: System peripheral (System timer, RTC, DBGU)
|
||||
* 2: PIO Controller A
|
||||
* 3: PIO Controller B
|
||||
* 4: PIO Controller C
|
||||
* 5: PIO Controller D/E
|
||||
* 6: TRNG
|
||||
* 7: USART 0
|
||||
* 8: USART 1
|
||||
* 9: USART 2
|
||||
* 10: USART 3
|
||||
* 11: Multimedia Card interface 0
|
||||
* 12: Two-wirte interface 0
|
||||
* 13: Two-wirte interface 1
|
||||
* 14: SPI 0
|
||||
* 15: SPI 1
|
||||
* 16: SSC 0
|
||||
* 17: SSC 0
|
||||
* 18: Timer Counter 0, 2, 3, 4, 5
|
||||
* 19: PWM
|
||||
* 20: Touch Screen ADC
|
||||
* 21: DMA
|
||||
* 22: USB Host port
|
||||
* 23: LCD
|
||||
* 24: AC97
|
||||
* 25: EMAC
|
||||
* 26: Image Sensor Interface
|
||||
* 27: USB Device High Speed
|
||||
* 28: -
|
||||
* 29: Multimedia Card interface 1
|
||||
* 30: Reserved
|
||||
* 31: AIC
|
||||
*/
|
||||
|
||||
#define AT91SAM9G45_IRQ_SYSTEM 1
|
||||
#define AT91SAM9G45_IRQ_PIOA 2
|
||||
#define AT91SAM9G45_IRQ_PIOB 3
|
||||
#define AT91SAM9G45_IRQ_PIOC 4
|
||||
#define AT91SAM9G45_IRQ_PIOD 5
|
||||
#define AT91SAM9G45_IRQ_PIOE 6
|
||||
#define AT91SAM9G45_IRQ_USART0 7
|
||||
#define AT91SAM9G45_IRQ_USART1 8
|
||||
#define AT91SAM9G45_IRQ_USART2 9
|
||||
#define AT91SAM9G45_IRQ_USART3 10
|
||||
#define AT91SAM9G45_IRQ_HSMCI0 11
|
||||
#define AT91SAM9G45_IRQ_TWI0 12
|
||||
#define AT91SAM9G45_IRQ_TWI1 13
|
||||
#define AT91SAM9G45_IRQ_SPI0 14
|
||||
#define AT91SAM9G45_IRQ_SPI1 15
|
||||
#define AT91SAM9G45_IRQ_SSC0 16
|
||||
#define AT91SAM9G45_IRQ_SSC1 17
|
||||
#define AT91SAM9G45_IRQ_TC0_TC5 18
|
||||
#define AT91SAM9G45_IRQ_PWM 19
|
||||
#define AT91SAM9G45_IRQ_TSADCC 20
|
||||
#define AT91SAM9G45_IRQ_DMA 21
|
||||
#define AT91SAM9G45_IRQ_UHP 22
|
||||
#define AT91SAM9G45_IRQ_LCDC 23
|
||||
#define AT91SAM9G45_IRQ_AC97C 24
|
||||
#define AT91SAM9G45_IRQ_EMAC 25
|
||||
#define AT91SAM9G45_IRQ_ISI 26
|
||||
#define AT91SAM9G45_IRQ_UDPHS 27
|
||||
/* Reserved 28 */
|
||||
#define AT91SAM9G45_IRQ_HSMCI1 29
|
||||
/* Reserved 30 */
|
||||
#define AT91SAM9G45_IRQ_AICBASE 31
|
||||
|
||||
/* Alias */
|
||||
#define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM
|
||||
#define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM
|
||||
#define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM
|
||||
#define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM
|
||||
#define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM
|
||||
#define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP
|
||||
#define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5
|
||||
#define AT91SAM9G45_IRQ_NAND (-1)
|
||||
|
||||
#define AT91SAM9G45_AIC_BASE 0xffff000
|
||||
#define AT91SAM9G45_AIC_SIZE 0x200
|
||||
|
||||
/* Timer */
|
||||
|
||||
#define AT91SAM9G45_WDT_BASE 0xffffd40
|
||||
#define AT91SAM9G45_WDT_SIZE 0x10
|
||||
|
||||
#define AT91SAM9G45_PIT_BASE 0xffffd30
|
||||
#define AT91SAM9G45_PIT_SIZE 0x10
|
||||
|
||||
#define AT91SAM9G45_SMC_BASE 0xfffe800
|
||||
#define AT91SAM9G45_SMC_SIZE 0x200
|
||||
|
||||
#define AT91SAM9G45_PMC_BASE 0xffffc00
|
||||
#define AT91SAM9G45_PMC_SIZE 0x100
|
||||
|
||||
#define AT91SAM9G45_HSMCI0_BASE 0xff80000
|
||||
#define AT91SAM9G45_HSMCI0_SIZE 0x4000
|
||||
|
||||
#define AT91SAM9G45_HSMCI1_BASE 0xffd0000
|
||||
#define AT91SAM9G45_HSMCI1_SIZE 0x4000
|
||||
|
||||
#define AT91SAM9G45_TWI0_BASE 0xff84000
|
||||
#define AT91SAM9G45_TWI0_SIZE 0x4000
|
||||
#define AT91SAM9G45_TWI1_BASE 0xff88000
|
||||
#define AT91SAM9G45_TWI1_SIZE 0x4000
|
||||
|
||||
/* XXX Needs to be carfully coordinated with
|
||||
* other * soc's so phyical and vm address
|
||||
* mapping are unique. XXX
|
||||
*/
|
||||
#define AT91SAM9G45_OHCI_BASE 0xdfb00000
|
||||
#define AT91SAM9G45_OHCI_PA_BASE 0x00700000
|
||||
#define AT91SAM9G45_OHCI_SIZE 0x00100000
|
||||
|
||||
#define AT91SAM9G45_NAND_BASE 0xe0000000
|
||||
#define AT91SAM9G45_NAND_PA_BASE 0x40000000
|
||||
#define AT91SAM9G45_NAND_SIZE 0x10000000
|
||||
|
||||
|
||||
/* DDRSDRC */
|
||||
#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00
|
||||
#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600
|
||||
#define AT91SAM9G45_DDRSDRC_MR 0x00
|
||||
#define AT91SAM9G45_DDRSDRC_TR 0x04
|
||||
#define AT91SAM9G45_DDRSDRC_CR 0x08
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc
|
||||
#define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c
|
||||
#define AT91SAM9G45_DDRSDRC_TPR0 0x0c
|
||||
#define AT91SAM9G45_DDRSDRC_TPR1 0x10
|
||||
#define AT91SAM9G45_DDRSDRC_TPR2 0x14
|
||||
/* Reserved 0x18 */
|
||||
#define AT91SAM9G45_DDRSDRC_LPR 0x1c
|
||||
#define AT91SAM9G45_DDRSDRC_MDR 0x20
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007
|
||||
#define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10
|
||||
#define AT91SAM9G45_DDRSDRC_DLL 0x24
|
||||
#define AT91SAM9G45_DDRSDRC_HSR 0x2c
|
||||
#define AT91SAM9G45_DDRSDRC_DELAY1R 0x40
|
||||
#define AT91SAM9G45_DDRSDRC_DELAY2R 0x44
|
||||
#define AT91SAM9G45_DDRSDRC_DELAY3R 0x48
|
||||
#define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c
|
||||
/* Reserved 0x50 - 0xe0 */
|
||||
#define AT91SAM9G45_DDRSDRC_WPMR 0xe4
|
||||
#define AT91SAM9G45_DDRSDRC_WPSR 0xe8
|
||||
|
||||
#endif /* AT91SAM9G45REG_H_*/
|
||||
|
||||
@ -32,6 +32,7 @@ arm/at91/at91rm9200.c optional at91rm9200
|
||||
arm/at91/at91rm9200_devices.c optional at91rm9200
|
||||
arm/at91/at91sam9260.c optional at91sam9260
|
||||
arm/at91/at91sam9g20.c optional at91sam9g20
|
||||
arm/at91/at91sam9g45.c optional at91sam9g45
|
||||
arm/at91/at91sam9x25.c optional at91sam9x25
|
||||
#
|
||||
# All the boards we support
|
||||
|
||||
11
sys/arm/at91/std.at91sam9g45
Normal file
11
sys/arm/at91/std.at91sam9g45
Normal file
@ -0,0 +1,11 @@
|
||||
# $FreeBSD$
|
||||
#
|
||||
# PHYSADDR is different on at91sam9g45 than the other at91sam SoCs
|
||||
|
||||
files "../at91/files.at91"
|
||||
cpu CPU_ARM9
|
||||
makeoptions CONF_CFLAGS=-mcpu=arm9
|
||||
options PHYSADDR=0x70000000
|
||||
|
||||
# bring in the sam specific timers and such
|
||||
device at91sam9
|
||||
Loading…
Reference in New Issue
Block a user