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Don't advertise the Instruction Based Sampling feature because it requires

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emulating a large number of MSRs.

Ignore writes to a couple more AMD-specific MSRs and return 0 on read.

This further reduces the unimplemented MSRs accessed by a Linux guest on boot.
This commit is contained in:
Neel Natu 2014-10-17 06:23:04 +00:00
parent 02904c45ab
commit 2688a818a3
3 changed files with 20 additions and 0 deletions
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5
sys/amd64/vmm/x86.c
View File

@ -166,6 +166,11 @@ x86_emulate_cpuid(struct vm *vm, int vcpu_id,
regs[2] &= ~AMDID2_PNXC;
regs[2] &= ~AMDID2_PTSCEL2I;
/*
* Don't advertise Instruction Based Sampling feature.
*/
regs[2] &= ~AMDID2_IBS;
/*
* Hide rdtscp/ia32_tsc_aux until we know how
* to deal with them.

2
sys/x86/include/specialreg.h
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@ -784,6 +784,8 @@
#define MSR_IORRMASK1 0xc0010019
#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
#define MSR_MC0_CTL_MASK 0xc0010044
#define MSR_VM_CR 0xc0010114 /* SVM: feature control */

13
usr.sbin/bhyve/xmsr.c
View File

@ -69,6 +69,10 @@ emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t val)
*/
return (0);
case MSR_NB_CFG1:
case MSR_IC_CFG:
return (0); /* Ignore writes */
case MSR_PERFEVSEL0:
case MSR_PERFEVSEL1:
case MSR_PERFEVSEL2:
@ -127,6 +131,15 @@ emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val)
*val |= 1 << 9; /* MONITOR/MWAIT disable */
break;
case MSR_NB_CFG1:
case MSR_IC_CFG:
/*
* The reset value is processor family dependent so
* just return 0.
*/
*val = 0;
break;
case MSR_PERFEVSEL0:
case MSR_PERFEVSEL1:
case MSR_PERFEVSEL2: