Allow using the embedded EHCI host controller in Freescale SoCs
by adding the missing bits. See ehci_fsl.c for their use.
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05bf457ab4
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@ -332,14 +332,18 @@ ehci_init(ehci_softc_t *sc)
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sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
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sc->sc_bus.usbrev = USB_REV_2_0;
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/* Reset the controller */
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DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
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if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) {
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/* Reset the controller */
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DPRINTF("%s: resetting\n",
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device_get_nameunit(sc->sc_bus.bdev));
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err = ehci_hcreset(sc);
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if (err) {
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device_printf(sc->sc_bus.bdev, "reset timeout\n");
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return (err);
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err = ehci_hcreset(sc);
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if (err) {
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device_printf(sc->sc_bus.bdev, "reset timeout\n");
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return (err);
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}
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}
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/*
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* use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
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* bytes 2: 256*4 bytes 3: unknown
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@ -345,6 +345,8 @@ typedef struct ehci_softc {
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#define EHCI_SCFLG_TT 0x0020 /* transaction translator present */
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#define EHCI_SCFLG_LOSTINTRBUG 0x0040 /* workaround for VIA / ATI chipsets */
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#define EHCI_SCFLG_IAADBUG 0x0080 /* workaround for nVidia chipsets */
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#define EHCI_SCFLG_DONTRESET 0x0100 /* don't reset ctrl. in ehci_init() */
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#define EHCI_SCFLG_DONEINIT 0x1000 /* ehci_init() has been called. */
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uint8_t sc_offs; /* offset to operational registers */
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uint8_t sc_doorbell_disable; /* set on doorbell failure */
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