Switch some PCI register reads from using magic numbers to using the names
defined in pcireg.h MFC after: 1 week
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199045d17c
commit
274e5948cc
@ -543,7 +543,7 @@ ahci_ctlr_reset(device_t dev)
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struct ahci_controller *ctlr = device_get_softc(dev);
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int timeout;
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if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
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if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
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(pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
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pci_write_config(dev, 0x92, 0x01, 1);
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/* Enable AHCI mode */
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@ -694,10 +694,10 @@ alc_aspm(struct alc_softc *sc, int media)
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if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
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/* Disable extended sync except AR8152 B v1.0 */
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linkcfg &= ~0x80;
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linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
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if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
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sc->alc_rev == ATHEROS_AR8152_B_V10)
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linkcfg |= 0x80;
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linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
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CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
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linkcfg);
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pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
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@ -834,15 +834,15 @@ alc_attach(device_t dev)
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cap = CSR_READ_2(sc, base + PCIER_LINK_CAP);
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if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
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ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL);
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if ((ctl & 0x08) != 0)
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if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
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sc->alc_rcb = DMA_CFG_RCB_128;
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if (bootverbose)
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device_printf(dev, "RCB %u bytes\n",
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sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
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state = ctl & 0x03;
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if (state & 0x01)
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state = ctl & PCIEM_LINK_CTL_ASPMC;
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if (state & PCIEM_LINK_CTL_ASPMC_L0S)
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sc->alc_flags |= ALC_FLAG_L0S;
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if (state & 0x02)
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if (state & PCIEM_LINK_CTL_ASPMC_L1)
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sc->alc_flags |= ALC_FLAG_L1S;
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if (bootverbose)
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device_printf(sc->alc_dev, "ASPM %s %s\n",
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@ -125,7 +125,7 @@ typedef boolean_t bool;
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#define PCI_EXP_LNKSTA PCIER_LINK_STA
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#define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED
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#define PCI_EXP_LNKSTA_NLW PCIEM_LINK_STA_WIDTH
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#define PCI_EXP_DEVCTL2 0x28
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#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2
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static inline int
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ilog2(long x)
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@ -5119,7 +5119,7 @@ em_disable_aspm(struct adapter *adapter)
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return;
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reg = base + PCIER_LINK_CTL;
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link_ctrl = pci_read_config(dev, reg, 2);
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link_ctrl &= 0xFFFC; /* turn off bit 1 and 2 */
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link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
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pci_write_config(dev, reg, link_ctrl, 2);
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return;
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}
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@ -1347,8 +1347,8 @@ re_attach(device_t dev)
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if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
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ctl = pci_read_config(dev, sc->rl_expcap +
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PCIER_LINK_CTL, 2);
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if ((ctl & 0x0003) != 0) {
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ctl &= ~0x0003;
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if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
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ctl &= ~PCIEM_LINK_CTL_ASPMC;
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pci_write_config(dev, sc->rl_expcap +
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PCIER_LINK_CTL, ctl, 2);
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device_printf(dev, "ASPM disabled\n");
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