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Use the new serial port definitions for modemsignals.

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This commit is contained in:
Poul-Henning Kamp 2004-06-24 10:07:28 +00:00
parent 98de21b633
commit 28710806cb
6 changed files with 92 additions and 105 deletions
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33
sys/dev/uart/uart_bus.h
View File

@ -33,6 +33,7 @@
#include "opt_uart.h"
#endif
#include <sys/serial.h>
#include <sys/timepps.h>
/* Drain and flush targets. */
@ -45,7 +46,7 @@
* Interrupt sources (in priority order). See also uart_core.c
* Note that the low order 16 bits are used to pass modem signals
* from the hardware interrupt handler to the software interrupt
* handler. See UART_SIG_* and UART_SIGMASK_* below.
* handler.
*/
#define UART_IPEND_OVERRUN 0x010000
#define UART_IPEND_BREAK 0x020000
@ -62,31 +63,17 @@
#define UART_STAT_OVERRUN 0x0400
#define UART_STAT_PARERR 0x0800
/* Modem and line signals. */
#define UART_SIG_DTR 0x0001
#define UART_SIG_RTS 0x0002
#define UART_SIG_DSR 0x0004
#define UART_SIG_CTS 0x0008
#define UART_SIG_DCD 0x0010
#define UART_SIG_RI 0x0020
#define UART_SIG_DDTR 0x0100
#define UART_SIG_DRTS 0x0200
#define UART_SIG_DDSR 0x0400
#define UART_SIG_DCTS 0x0800
#define UART_SIG_DDCD 0x1000
#define UART_SIG_DRI 0x2000
#define UART_SIGMASK_DTE 0x0003
#define UART_SIGMASK_DCE 0x003c
#define UART_SIGMASK_STATE 0x003f
#define UART_SIGMASK_DELTA 0x3f00
#define UART_SIGMASK_DTE (SER_DTR | SER_RTS)
#define UART_SIGMASK_DCE (SER_DSR | SER_CTS | SER_DCD | SER_RI)
#define UART_SIGMASK_STATE (UART_SIGMASK_DTE | UART_SIGMASK_DCE)
#define UART_SIGMASK_DELTA (UART_SIGMASK_STATE << 8)
#ifdef UART_PPS_ON_CTS
#define UART_SIG_DPPS UART_SIG_DCTS
#define UART_SIG_PPS UART_SIG_CTS
#define UART_SIG_DPPS SER_DCTS
#define UART_SIG_PPS SER_CTS
#else
#define UART_SIG_DPPS UART_SIG_DDCD
#define UART_SIG_PPS UART_SIG_DCD
#define UART_SIG_DPPS SER_DDCD
#define UART_SIG_PPS SER_DCD
#endif
/* UART_IOCTL() requests */

28
sys/dev/uart/uart_dev_i8251.c
View File

@ -398,9 +398,9 @@ i8251_bus_attach(struct uart_softc *sc)
i8251_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
if (i8251->mcr & MCR_DTR)
sc->sc_hwsig |= UART_SIG_DTR;
sc->sc_hwsig |= SER_DTR;
if (i8251->mcr & MCR_RTS)
sc->sc_hwsig |= UART_SIG_RTS;
sc->sc_hwsig |= SER_RTS;
i8251_bus_getsig(sc);
i8251_clrint(bas);
@ -454,10 +454,10 @@ i8251_bus_getsig(struct uart_softc *sc)
mtx_lock_spin(&sc->sc_hwmtx);
msr = uart_getreg(&sc->sc_bas, REG_MSR);
mtx_unlock_spin(&sc->sc_hwmtx);
SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
SIGCHG(msr & MSR_RI, sig, UART_SIG_RI, UART_SIG_DRI);
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
new = sig & ~UART_SIGMASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
return (sig);
@ -715,20 +715,20 @@ i8251_bus_setsig(struct uart_softc *sc, int sig)
do {
old = sc->sc_hwsig;
new = old;
if (sig & UART_SIG_DDTR) {
SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
UART_SIG_DDTR);
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
}
if (sig & UART_SIG_DRTS) {
SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
UART_SIG_DRTS);
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
mtx_lock_spin(&sc->sc_hwmtx);
i8251->mcr &= ~(MCR_DTR|MCR_RTS);
if (new & UART_SIG_DTR)
if (new & SER_DTR)
i8251->mcr |= MCR_DTR;
if (new & UART_SIG_RTS)
if (new & SER_RTS)
i8251->mcr |= MCR_RTS;
uart_setreg(bas, REG_MCR, i8251->mcr);
uart_barrier(bas);

28
sys/dev/uart/uart_dev_ns8250.c
View File

@ -399,9 +399,9 @@ ns8250_bus_attach(struct uart_softc *sc)
ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
if (ns8250->mcr & MCR_DTR)
sc->sc_hwsig |= UART_SIG_DTR;
sc->sc_hwsig |= SER_DTR;
if (ns8250->mcr & MCR_RTS)
sc->sc_hwsig |= UART_SIG_RTS;
sc->sc_hwsig |= SER_RTS;
ns8250_bus_getsig(sc);
ns8250_clrint(bas);
@ -455,10 +455,10 @@ ns8250_bus_getsig(struct uart_softc *sc)
mtx_lock_spin(&sc->sc_hwmtx);
msr = uart_getreg(&sc->sc_bas, REG_MSR);
mtx_unlock_spin(&sc->sc_hwmtx);
SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
SIGCHG(msr & MSR_RI, sig, UART_SIG_RI, UART_SIG_DRI);
SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
new = sig & ~UART_SIGMASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
return (sig);
@ -753,20 +753,20 @@ ns8250_bus_setsig(struct uart_softc *sc, int sig)
do {
old = sc->sc_hwsig;
new = old;
if (sig & UART_SIG_DDTR) {
SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
UART_SIG_DDTR);
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
}
if (sig & UART_SIG_DRTS) {
SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
UART_SIG_DRTS);
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
mtx_lock_spin(&sc->sc_hwmtx);
ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
if (new & UART_SIG_DTR)
if (new & SER_DTR)
ns8250->mcr |= MCR_DTR;
if (new & UART_SIG_RTS)
if (new & SER_RTS)
ns8250->mcr |= MCR_RTS;
uart_setreg(bas, REG_MCR, ns8250->mcr);
uart_barrier(bas);

26
sys/dev/uart/uart_dev_sab82532.c
View File

@ -410,7 +410,7 @@ sab82532_bus_attach(struct uart_softc *sc)
uart_barrier(bas);
if (sc->sc_sysdev == NULL)
sab82532_bus_setsig(sc, UART_SIG_DDTR|UART_SIG_DRTS);
sab82532_bus_setsig(sc, SER_DDTR|SER_DRTS);
(void)sab82532_bus_getsig(sc);
return (0);
}
@ -455,9 +455,9 @@ sab82532_bus_getsig(struct uart_softc *sc)
sig = old;
mtx_lock_spin(&sc->sc_hwmtx);
star = uart_getreg(bas, SAB_STAR);
SIGCHG(star & SAB_STAR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(star & SAB_STAR_CTS, sig, SER_CTS, SER_DCTS);
vstr = uart_getreg(bas, SAB_VSTR);
SIGCHG(vstr & SAB_VSTR_CD, sig, UART_SIG_DCD, UART_SIG_DDCD);
SIGCHG(vstr & SAB_VSTR_CD, sig, SER_DCD, SER_DDCD);
pvr = uart_getreg(bas, SAB_PVR);
switch (bas->chan) {
case 1:
@ -467,7 +467,7 @@ sab82532_bus_getsig(struct uart_softc *sc)
pvr &= SAB_PVR_DSR_B;
break;
}
SIGCHG(~pvr, sig, UART_SIG_DSR, UART_SIG_DDSR);
SIGCHG(~pvr, sig, SER_DSR, SER_DDSR);
mtx_unlock_spin(&sc->sc_hwmtx);
new = sig & ~UART_SIGMASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
@ -655,13 +655,13 @@ sab82532_bus_setsig(struct uart_softc *sc, int sig)
do {
old = sc->sc_hwsig;
new = old;
if (sig & UART_SIG_DDTR) {
SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
UART_SIG_DDTR);
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
}
if (sig & UART_SIG_DRTS) {
SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
UART_SIG_DRTS);
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
@ -670,13 +670,13 @@ sab82532_bus_setsig(struct uart_softc *sc, int sig)
pvr = uart_getreg(bas, SAB_PVR);
switch (bas->chan) {
case 1:
if (new & UART_SIG_DTR)
if (new & SER_DTR)
pvr &= ~SAB_PVR_DTR_A;
else
pvr |= SAB_PVR_DTR_A;
break;
case 2:
if (new & UART_SIG_DTR)
if (new & SER_DTR)
pvr &= ~SAB_PVR_DTR_B;
else
pvr |= SAB_PVR_DTR_B;
@ -686,7 +686,7 @@ sab82532_bus_setsig(struct uart_softc *sc, int sig)
/* Set RTS pin. */
mode = uart_getreg(bas, SAB_MODE);
if (new & UART_SIG_RTS)
if (new & SER_RTS)
mode &= ~SAB_MODE_FRTS;
else
mode |= SAB_MODE_FRTS;

24
sys/dev/uart/uart_dev_z8530.c
View File

@ -350,8 +350,8 @@ z8530_bus_getsig(struct uart_softc *sc)
mtx_lock_spin(&sc->sc_hwmtx);
bes = uart_getmreg(&sc->sc_bas, RR_BES);
mtx_unlock_spin(&sc->sc_hwmtx);
SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
new = sig & ~UART_SIGMASK_DELTA;
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
return (sig);
@ -411,8 +411,8 @@ z8530_bus_ipend(struct uart_softc *sc)
if (bes & BES_RXA)
ipend |= UART_IPEND_RXREADY;
sig = sc->sc_hwsig;
SIGCHG(bes & BES_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(bes & BES_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS);
SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD);
if (sig & UART_SIGMASK_DELTA)
ipend |= UART_IPEND_SIGCHG;
src = uart_getmreg(bas, RR_SRC);
@ -509,22 +509,22 @@ z8530_bus_setsig(struct uart_softc *sc, int sig)
do {
old = sc->sc_hwsig;
new = old;
if (sig & UART_SIG_DDTR) {
SIGCHG(sig & UART_SIG_DTR, new, UART_SIG_DTR,
UART_SIG_DDTR);
if (sig & SER_DDTR) {
SIGCHG(sig & SER_DTR, new, SER_DTR,
SER_DDTR);
}
if (sig & UART_SIG_DRTS) {
SIGCHG(sig & UART_SIG_RTS, new, UART_SIG_RTS,
UART_SIG_DRTS);
if (sig & SER_DRTS) {
SIGCHG(sig & SER_RTS, new, SER_RTS,
SER_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
mtx_lock_spin(&sc->sc_hwmtx);
if (new & UART_SIG_DTR)
if (new & SER_DTR)
z8530->tpc |= TPC_DTR;
else
z8530->tpc &= ~TPC_DTR;
if (new & UART_SIG_RTS)
if (new & SER_RTS)
z8530->tpc |= TPC_RTS;
else
z8530->tpc &= ~TPC_RTS;

58
sys/dev/uart/uart_tty.c
View File

@ -164,11 +164,11 @@ uart_tty_oproc(struct tty *tp)
*/
if ((tp->t_cflag & CRTS_IFLOW) && !sc->sc_hwiflow) {
if ((tp->t_state & TS_TBLOCK) &&
(sc->sc_hwsig & UART_SIG_RTS))
UART_SETSIG(sc, UART_SIG_DRTS);
(sc->sc_hwsig & SER_RTS))
UART_SETSIG(sc, SER_DRTS);
else if (!(tp->t_state & TS_TBLOCK) &&
!(sc->sc_hwsig & UART_SIG_RTS))
UART_SETSIG(sc, UART_SIG_DRTS|UART_SIG_RTS);
!(sc->sc_hwsig & SER_RTS))
UART_SETSIG(sc, SER_DRTS|SER_RTS);
}
if (tp->t_state & TS_TTSTOP)
@ -207,7 +207,7 @@ uart_tty_param(struct tty *tp, struct termios *t)
t->c_cflag &= ~HUPCL;
}
if (t->c_ospeed == 0) {
UART_SETSIG(sc, UART_SIG_DDTR | UART_SIG_DRTS);
UART_SETSIG(sc, SER_DDTR | SER_DRTS);
return (0);
}
switch (t->c_cflag & CSIZE) {
@ -224,13 +224,13 @@ uart_tty_param(struct tty *tp, struct termios *t)
parity = UART_PARITY_NONE;
if (UART_PARAM(sc, t->c_ospeed, databits, stopbits, parity) != 0)
return (EINVAL);
UART_SETSIG(sc, UART_SIG_DDTR | UART_SIG_DTR);
UART_SETSIG(sc, SER_DDTR | SER_DTR);
/* Set input flow control state. */
if (!sc->sc_hwiflow) {
if ((t->c_cflag & CRTS_IFLOW) && (tp->t_state & TS_TBLOCK))
UART_SETSIG(sc, UART_SIG_DRTS);
UART_SETSIG(sc, SER_DRTS);
else
UART_SETSIG(sc, UART_SIG_DRTS | UART_SIG_RTS);
UART_SETSIG(sc, SER_DRTS | SER_RTS);
} else
UART_IOCTL(sc, UART_IOCTL_IFLOW, (t->c_cflag & CRTS_IFLOW));
/* Set output flow control state. */
@ -297,11 +297,11 @@ uart_tty_intr(void *arg)
if (pend & UART_IPEND_SIGCHG) {
sig = pend & UART_IPEND_SIGMASK;
if (sig & UART_SIG_DDCD)
ttyld_modem(tp, sig & UART_SIG_DCD);
if ((sig & UART_SIG_DCTS) && (tp->t_cflag & CCTS_OFLOW) &&
if (sig & SER_DDCD)
ttyld_modem(tp, sig & SER_DCD);
if ((sig & SER_DCTS) && (tp->t_cflag & CCTS_OFLOW) &&
!sc->sc_hwoflow) {
if (sig & UART_SIG_CTS) {
if (sig & SER_CTS) {
tp->t_state &= ~TS_TTSTOP;
ttyld_start(tp);
} else
@ -418,7 +418,7 @@ uart_tty_open(struct cdev *dev, int flags, int mode, struct thread *td)
/*
* Handle initial DCD.
*/
if ((sc->sc_hwsig & UART_SIG_DCD) || sc->sc_callout)
if ((sc->sc_hwsig & SER_DCD) || sc->sc_callout)
ttyld_modem(tp, 1);
}
/*
@ -464,7 +464,7 @@ uart_tty_close(struct cdev *dev, int flags, int mode, struct thread *td)
if (sc->sc_hwoflow)
UART_IOCTL(sc, UART_IOCTL_OFLOW, 0);
if (sc->sc_sysdev == NULL)
UART_SETSIG(sc, UART_SIG_DDTR | UART_SIG_DRTS);
UART_SETSIG(sc, SER_DDTR | SER_DRTS);
/* Disable pulse capturing. */
sc->sc_pps.ppsparam.mode = 0;
@ -504,52 +504,52 @@ uart_tty_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags,
UART_IOCTL(sc, UART_IOCTL_BREAK, 0);
break;
case TIOCSDTR:
UART_SETSIG(sc, UART_SIG_DDTR | UART_SIG_DTR);
UART_SETSIG(sc, SER_DDTR | SER_DTR);
break;
case TIOCCDTR:
UART_SETSIG(sc, UART_SIG_DDTR);
UART_SETSIG(sc, SER_DDTR);
break;
case TIOCMSET:
bits = *(int*)data;
sig = UART_SIG_DDTR | UART_SIG_DRTS;
sig = SER_DDTR | SER_DRTS;
if (bits & TIOCM_DTR)
sig |= UART_SIG_DTR;
sig |= SER_DTR;
if (bits & TIOCM_RTS)
sig |= UART_SIG_RTS;
sig |= SER_RTS;
UART_SETSIG(sc, sig);
break;
case TIOCMBIS:
bits = *(int*)data;
sig = 0;
if (bits & TIOCM_DTR)
sig |= UART_SIG_DDTR | UART_SIG_DTR;
sig |= SER_DDTR | SER_DTR;
if (bits & TIOCM_RTS)
sig |= UART_SIG_DRTS | UART_SIG_RTS;
sig |= SER_DRTS | SER_RTS;
UART_SETSIG(sc, sig);
break;
case TIOCMBIC:
bits = *(int*)data;
sig = 0;
if (bits & TIOCM_DTR)
sig |= UART_SIG_DDTR;
sig |= SER_DDTR;
if (bits & TIOCM_RTS)
sig |= UART_SIG_DRTS;
sig |= SER_DRTS;
UART_SETSIG(sc, sig);
break;
case TIOCMGET:
sig = sc->sc_hwsig;
bits = TIOCM_LE;
if (sig & UART_SIG_DTR)
if (sig & SER_DTR)
bits |= TIOCM_DTR;
if (sig & UART_SIG_RTS)
if (sig & SER_RTS)
bits |= TIOCM_RTS;
if (sig & UART_SIG_DSR)
if (sig & SER_DSR)
bits |= TIOCM_DSR;
if (sig & UART_SIG_CTS)
if (sig & SER_CTS)
bits |= TIOCM_CTS;
if (sig & UART_SIG_DCD)
if (sig & SER_DCD)
bits |= TIOCM_CD;
if (sig & (UART_SIG_DRI | UART_SIG_RI))
if (sig & (SER_DRI | SER_RI))
bits |= TIOCM_RI;
*(int*)data = bits;
break;