d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

qlxgb: clean up empty lines in .c and .h files

Browse Source
This commit is contained in:
Mateusz Guzik 2020-09-01 21:57:15 +00:00
parent 2c4a3d0a2c
commit 29c3bcd9d0
12 changed files with 42 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sys/dev/qlxgb/qla_dbg.c
View File

@ -43,7 +43,6 @@ __FBSDID("$FreeBSD$");
#include "qla_glbl.h"
#include "qla_dbg.h"
uint32_t dbg_level = 0 ;
/*
* Name: qla_dump_buf32
@ -157,7 +156,7 @@ void qla_dump_buf8(qla_host_t *ha, char *msg, void *dbuf, uint32_t len)
buf = dbuf;
device_printf(dev, "%s: %s 0x%x dump start\n", __func__, msg, len);
while (len >= 16) {
device_printf(dev,"0x%08x:"
" %02x %02x %02x %02x %02x %02x %02x %02x"
@ -260,6 +259,6 @@ void qla_dump_buf8(qla_host_t *ha, char *msg, void *dbuf, uint32_t len)
default:
break;
}
device_printf(dev, "%s: %s dump end\n", __func__, msg);
}

1
sys/dev/qlxgb/qla_dbg.h
View File

@ -46,7 +46,6 @@ extern void qla_dump_buf16(qla_host_t *ha, char *str, void *dbuf,
extern void qla_dump_buf32(qla_host_t *ha, char *str, void *dbuf,
uint32_t len32);
#define DBG 1
#if DBG

2
sys/dev/qlxgb/qla_def.h
View File

@ -141,7 +141,7 @@ struct qla_host {
int msix_count;
void *intr_handle;
qla_ivec_t irq_vec[Q8_MSI_COUNT];
/* parent dma tag */
bus_dma_tag_t parent_tag;

45
sys/dev/qlxgb/qla_hw.c
View File

@ -155,7 +155,7 @@ qla_alloc_dma(qla_host_t *ha)
ha->hw.dma_buf.tx_ring.alignment = 8;
ha->hw.dma_buf.tx_ring.size =
(sizeof(q80_tx_cmd_t)) * NUM_TX_DESCRIPTORS;
if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.tx_ring)) {
device_printf(dev, "%s: tx ring alloc failed\n", __func__);
goto qla_alloc_dma_exit;
@ -181,7 +181,7 @@ qla_alloc_dma(qla_host_t *ha)
NUM_RX_JUMBO_DESCRIPTORS;
} else
break;
if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i])) {
QL_DPRINT4((dev, "%s: rds ring alloc failed\n",
__func__));
@ -239,10 +239,10 @@ qla_alloc_dma(qla_host_t *ha)
size += sizeof (uint32_t); /* for tx consumer index */
size = QL_ALIGN(size, PAGE_SIZE);
ha->hw.dma_buf.context.alignment = 8;
ha->hw.dma_buf.context.size = size;
if (qla_alloc_dmabuf(ha, &ha->hw.dma_buf.context)) {
device_printf(dev, "%s: context alloc failed\n", __func__);
goto qla_alloc_dma_exit;
@ -281,12 +281,11 @@ qla_init_cntxt_regions(qla_host_t *ha)
hw = &ha->hw;
hw->tx_ring_base = hw->dma_buf.tx_ring.dma_b;
for (i = 0; i < ha->hw.num_sds_rings; i++)
hw->sds[i].sds_ring_base =
(q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
phys_addr = hw->dma_buf.context.dma_addr;
memset((void *)hw->dma_buf.context.dma_b, 0,
@ -331,7 +330,7 @@ qla_init_cntxt_regions(qla_host_t *ha)
tx_cntxt_req->caps[0] = qla_host_to_le32((CNTXT_CAP0_BASEFW |
CNTXT_CAP0_LEGACY_MN | CNTXT_CAP0_LSO));
tx_cntxt_req->intr_mode = qla_host_to_le32(CNTXT_INTR_MODE_SHARED);
tx_cntxt_req->phys_addr =
@ -423,7 +422,7 @@ qla_issue_cmd(qla_host_t *ha, qla_cdrp_t *cdrp)
signature = 0xcafe0000 | 0x0100 | ha->pci_func;
ret = qla_sem_lock(ha, Q8_SEM5_LOCK, 0, (uint32_t)ha->pci_func);
if (ret) {
device_printf(dev, "%s: SEM5_LOCK lock failed\n", __func__);
return (ret);
@ -556,7 +555,7 @@ qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
rss_config.flags = Q8_FWCD_RSS_FLAGS_ENABLE_RSS;
rss_config.ind_tbl_mask = 0x7;
for (i = 0; i < 5; i++)
rss_config.rss_key[i] = rss_key[i];
@ -580,7 +579,7 @@ qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable)
intr_coalesce.hdr.cmd = Q8_FWCD_CNTRL_REQ;
intr_coalesce.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_INTR_COALESCING;
intr_coalesce.hdr.cntxt_id = cntxt_id;
intr_coalesce.flags = 0x04;
intr_coalesce.max_rcv_pkts = 256;
intr_coalesce.max_rcv_usecs = 3;
@ -600,7 +599,6 @@ qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable)
return ret;
}
/*
* Name: qla_config_mac_addr
* Function: binds a MAC address to the context/interface.
@ -623,7 +621,7 @@ qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint16_t cntxt_id,
mac_config.hdr.cmd = Q8_FWCD_CNTRL_REQ;
mac_config.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_MAC_ADDR;
mac_config.hdr.cntxt_id = cntxt_id;
if (add_multi)
mac_config.cmd = Q8_FWCD_ADD_MAC_ADDR;
else
@ -635,7 +633,6 @@ qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint16_t cntxt_id,
return ret;
}
/*
* Name: qla_set_mac_rcv_mode
* Function: Enable/Disable AllMulticast and Promiscuous Modes.
@ -651,7 +648,7 @@ qla_set_mac_rcv_mode(qla_host_t *ha, uint16_t cntxt_id, uint32_t mode)
rcv_mode.hdr.cmd = Q8_FWCD_CNTRL_REQ;
rcv_mode.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_MAC_RCV_MODE;
rcv_mode.hdr.cntxt_id = cntxt_id;
rcv_mode.mode = mode;
ret = qla_fw_cmd(ha, &rcv_mode, sizeof(qla_set_mac_rcv_mode_t));
@ -697,7 +694,7 @@ qla_config_ipv4_addr(qla_host_t *ha, uint32_t ipv4_addr)
ip_conf.hdr.cmd = Q8_FWCD_CNTRL_REQ;
ip_conf.hdr.opcode = Q8_FWCD_OPCODE_CONFIG_IPADDR;
ip_conf.hdr.cntxt_id = (ha->hw.rx_cntxt_rsp)->rx_rsp.cntxt_id;
ip_conf.cmd = (uint64_t)Q8_CONFIG_CMD_IP_ENABLE;
ip_conf.ipv4_addr = (uint64_t)ipv4_addr;
@ -770,7 +767,6 @@ qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
tcp_hlen = th->th_off << 2;
hdrlen = ehdrlen + ip_hlen + tcp_hlen;
if (mp->m_len < hdrlen) {
@ -786,12 +782,10 @@ qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
}
if ((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
/* If TCP options are preset only time stamp option is supported */
if ((tcp_hlen - sizeof(struct tcphdr)) != 10)
return -1;
else {
if (mp->m_len < hdrlen) {
tcp_opt = &hdr[tcp_opt_off];
} else {
@ -955,7 +949,6 @@ qla_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
eh = mtod(mp, struct ether_vlan_header *);
if ((mp->m_pkthdr.len > ha->max_frame_size)||(nsegs > Q8_TX_MAX_SEGMENTS)) {
bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
src = ha->hw.frame_hdr;
@ -968,7 +961,7 @@ qla_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
bytes = QL_MIN(bytes, hdr_len);
num_tx_cmds++;
hdr_len -= bytes;
@ -1024,7 +1017,6 @@ qla_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
}
tx_cmd->n_bufs = (uint8_t)nsegs;
tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
@ -1034,7 +1026,6 @@ qla_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
while (1) {
for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
switch (i) {
case 0:
tx_cmd->buf1_addr = c_seg->ds_addr;
@ -1143,10 +1134,10 @@ qla_del_hw_if(qla_host_t *ha)
for (i = 0; i < ha->hw.num_sds_rings; i++)
QL_DISABLE_INTERRUPTS(ha, i);
qla_del_rcv_cntxt(ha);
qla_del_xmt_cntxt(ha);
ha->hw.flags.lro = 0;
}
@ -1249,7 +1240,7 @@ qla_init_rcv_cntxt(qla_host_t *ha)
cdrp.cmd_arg1 = (uint32_t)(phys_addr >> 32);
cdrp.cmd_arg2 = (uint32_t)(phys_addr);
cdrp.cmd_arg3 = (uint32_t)(sizeof (q80_rcv_cntxt_req_t));
if (qla_issue_cmd(ha, &cdrp)) {
device_printf(dev, "%s: Q8_CMD_CREATE_RX_CNTXT failed\n",
__func__);
@ -1350,7 +1341,7 @@ qla_init_xmt_cntxt(qla_host_t *ha)
cdrp.cmd_arg1 = (uint32_t)(phys_addr >> 32);
cdrp.cmd_arg2 = (uint32_t)(phys_addr);
cdrp.cmd_arg3 = (uint32_t)(sizeof (q80_tx_cntxt_req_t));
if (qla_issue_cmd(ha, &cdrp)) {
device_printf(dev, "%s: Q8_CMD_CREATE_TX_CNTXT failed\n",
__func__);
@ -1705,7 +1696,6 @@ qla_hw_tx_done_locked(qla_host_t *ha)
comp_idx = qla_le32_to_host(*(hw->tx_cons));
while (comp_idx != hw->txr_comp) {
txb = &ha->tx_buf[hw->txr_comp];
hw->txr_comp++;
@ -1839,4 +1829,3 @@ qla_hw_stop_rcv(qla_host_t *ha)
qla_mdelay(__func__, 10);
}
}

13
sys/dev/qlxgb/qla_hw.h
View File

@ -55,7 +55,7 @@ typedef struct qla_cdrp {
uint32_t rsp_arg2;
uint32_t rsp_arg3;
} qla_cdrp_t;
#define Q8_CMD_RD_MAX_RDS_PER_CNTXT 0x80000002
#define Q8_CMD_RD_MAX_SDS_PER_CNTXT 0x80000003
#define Q8_CMD_RD_MAX_RULES_PER_CNTXT 0x80000004
@ -97,7 +97,6 @@ typedef struct qla_cdrp {
#define Q8_RSP_CMD_INVALID 0x00000010
#define Q8_RSP_TIMEOUT 0x00000011
/*
* Transmit Related Definitions
*/
@ -128,7 +127,6 @@ typedef struct _q80_tx_cntxt_req {
uint32_t num_entries; /* number of entries in transmit ring */
uint8_t rsrvd3[128];
} __packed q80_tx_cntxt_req_t; /* 188 bytes total */
/*
* Transmit Context - Response from Firmware to Q8_CMD_CREATE_TX_CNTXT
@ -208,7 +206,6 @@ typedef struct _q80_tx_cmd {
#define Q8_TX_CMD_TSO_ALIGN 2
#define Q8_TX_MAX_SEGMENTS 14
/*
* Receive Related Definitions
*/
@ -282,7 +279,6 @@ typedef struct _q80_rsp_rcv_cntxt {
uint8_t data[0];
} __packed q80_rsp_rcv_cntxt_t; /* 152 bytes header + rds + sds ring rspncs */
/*
* Note:
* Transmit Context
@ -583,7 +579,6 @@ typedef struct _qla_link_event_req {
uint8_t pad[6];
} __packed qla_link_event_req_t;
/*
* Set MAC Receive Mode
*/
@ -621,7 +616,6 @@ typedef struct _qla_config_lro {
#define Q8_CONFIG_LRO_ENABLE 0x08
} __packed qla_config_lro_t;
/*
* Control Messages Received on SDS Ring
*/
@ -762,7 +756,7 @@ typedef struct _qla_hw {
uint16_t num_sds_rings;
qla_dmabuf_t dma_buf;
/* Transmit Side */
q80_tx_cmd_t *tx_ring_base;
@ -793,7 +787,7 @@ typedef struct _qla_hw {
bus_addr_t rx_cntxt_req_paddr;
q80_rcv_cntxt_rsp_t *rx_cntxt_rsp; /* Rcv Context Response */
bus_addr_t rx_cntxt_rsp_paddr;
qla_sds_t sds[MAX_SDS_RINGS];
uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
@ -831,7 +825,6 @@ typedef struct _qla_hw {
WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
}
#define QL_BUFFER_ALIGN 16
#endif /* #ifndef _QLA_HW_H_ */

1
sys/dev/qlxgb/qla_inline.h
View File

@ -45,7 +45,6 @@ static __inline void qla_hw_reset(qla_host_t *ha)
#define QL8_SEMLOCK_TIMEOUT 1000/* QLA8020 Semaphore Lock Timeout 10ms */
/*
* Inline functions for hardware semaphores
*/

3
sys/dev/qlxgb/qla_ioctl.c
View File

@ -94,7 +94,6 @@ qla_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
pci_dev= ha->pci_dev;
switch(cmd) {
case QLA_RDWR_REG:
rv = (qla_reg_val_t *)data;
@ -125,7 +124,6 @@ qla_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
rval = ENXIO;
break;
case QLA_ERASE_FLASH:
if (qla_erase_flash(ha, ((qla_erase_flash_t *)data)->off,
((qla_erase_flash_t *)data)->size))
@ -147,4 +145,3 @@ qla_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
return rval;
}

12
sys/dev/qlxgb/qla_isr.c
View File

@ -61,9 +61,9 @@ qla_rx_intr(qla_host_t *ha, uint64_t data, uint32_t sds_idx,
struct ifnet *ifp = ha->ifp;
qla_sds_t *sdsp;
struct ether_vlan_header *eh;
sdsp = &ha->hw.sds[sds_idx];
ring = (uint32_t)Q8_STAT_DESC_TYPE(data);
idx = (uint32_t)Q8_STAT_DESC_HANDLE(data);
length = (uint32_t)Q8_STAT_DESC_TOTAL_LENGTH(data);
@ -113,11 +113,11 @@ qla_rx_intr(qla_host_t *ha, uint64_t data, uint32_t sds_idx,
sdsp->rxjb_free = rxb;
sdsp->rxj_free++;
}
mp->m_len = length;
mp->m_pkthdr.len = length;
mp->m_pkthdr.rcvif = ifp;
eh = mtod(mp, struct ether_vlan_header *);
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
@ -175,7 +175,6 @@ qla_replenish_jumbo_rx(qla_host_t *ha, qla_sds_t *sdsp)
sdsp->rxjb_free = rxb->next;
sdsp->rxj_free--;
if (qla_get_mbuf(ha, rxb, NULL, RDS_RING_INDEX_JUMBO) == 0) {
qla_set_hw_rcv_desc(ha, RDS_RING_INDEX_JUMBO,
ha->hw.rxj_in, rxb->handle, rxb->paddr,
@ -289,7 +288,6 @@ qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
lro = &hw->sds[sds_idx].lro;
while (count--) {
sdesc = (q80_stat_desc_t *)
&hw->sds[sds_idx].sds_ring_base[comp_idx];
@ -303,7 +301,6 @@ qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
desc_count = Q8_STAT_DESC_COUNT((sdesc->data[0]));
switch (Q8_STAT_DESC_OPCODE((sdesc->data[0]))) {
case Q8_STAT_DESC_OPCODE_RCV_PKT:
case Q8_STAT_DESC_OPCODE_SYN_OFFLOAD:
qla_rx_intr(ha, (sdesc->data[0]), sds_idx, lro);
@ -410,4 +407,3 @@ qla_rcv(void *context, int pending)
QL_ENABLE_INTERRUPTS(ha, sds_idx);
}

29
sys/dev/qlxgb/qla_misc.c
View File

@ -187,7 +187,7 @@ static crb_to_pci_t crbinit_to_pciaddr[] = {
{(0x759 << 20), (0x027 << 20)},
{(0x773 << 20), (0x001 << 20)}
};
#define Q8_INVALID_ADDRESS (-1)
#define Q8_ADDR_MASK (0xFFF << 20)
@ -293,7 +293,7 @@ qla_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, offchip_mem_val_t *val,
} else
qla_mdelay(__func__, 1);
}
device_printf(ha->pci_dev, "%s: failed[0x%08x]\n", __func__, data);
return (-1);
}
@ -501,7 +501,6 @@ qla_load_fw_from_flash(qla_host_t *ha)
uint32_t count;
offchip_mem_val_t val;
/* only bootloader needs to be loaded into memory */
for (count = 0; count < 0x20000 ; ) {
qla_rd_flash32(ha, flash_off, &val.data_lo);
@ -553,7 +552,7 @@ qla_init_from_flash(qla_host_t *ha)
qla_mdelay(__func__, 10);
qla_load_fw_from_flash(ha);
WRITE_OFFSET32(ha, Q8_CMDPEG_STATE, 0x00000000);
WRITE_OFFSET32(ha, Q8_PEG_0_RESET, 0x00001020);
WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0x0080001E);
@ -582,7 +581,7 @@ qla_init_from_flash(qla_host_t *ha)
(READ_OFFSET32(ha, Q8_PEG_HALT_STATUS2)),
(READ_OFFSET32(ha, Q8_FIRMWARE_HEARTBEAT)),
(READ_OFFSET32(ha, Q8_RCVPEG_STATE)), data);
return (-1);
}
@ -630,11 +629,9 @@ qla_init_hw(qla_host_t *ha)
ha->fw_ver_sub = READ_OFFSET32(ha, Q8_FW_VER_SUB);
if (qla_rd_flash32(ha, 0x100004, &val) == 0) {
if (((val & 0xFF) != ha->fw_ver_major) ||
(((val >> 8) & 0xFF) != ha->fw_ver_minor) ||
(((val >> 16) & 0xFF) != ha->fw_ver_sub)) {
ret = qla_init_from_flash(ha);
qla_mdelay(__func__, 100);
}
@ -700,7 +697,7 @@ qla_flash_unprotect(qla_host_t *ha)
val = ROM_OPCODE_WR_STATUS_REG;
qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
rval = qla_wait_for_flash_busy(ha);
if (rval) {
@ -716,7 +713,7 @@ qla_flash_unprotect(qla_host_t *ha)
val = ROM_OPCODE_WR_STATUS_REG;
qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
rval = qla_wait_for_flash_busy(ha);
if (rval)
@ -738,7 +735,7 @@ qla_flash_protect(qla_host_t *ha)
val = ROM_OPCODE_WR_STATUS_REG;
qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
rval = qla_wait_for_flash_busy(ha);
if (rval)
@ -759,7 +756,7 @@ qla_flash_get_status(qla_host_t *ha)
val = ROM_OPCODE_RD_STATUS_REG;
qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);
rval = qla_wait_for_flash_busy(ha);
if (rval == 0) {
@ -779,7 +776,6 @@ qla_wait_for_flash_unprotect(qla_host_t *ha)
uint32_t delay = 1000;
while (delay--) {
if (qla_flash_get_status(ha) == 0)
return 0;
@ -795,7 +791,6 @@ qla_wait_for_flash_protect(qla_host_t *ha)
uint32_t delay = 1000;
while (delay--) {
if (qla_flash_get_status(ha) == 0x9C)
return 0;
@ -898,7 +893,6 @@ qla_flash_wait_for_write_complete(qla_host_t *ha)
int rval = 0;
while (count--) {
val = 0;
qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);
@ -934,7 +928,6 @@ qla_flash_write(qla_host_t *ha, uint32_t off, uint32_t data)
return 0;
}
static int
qla_flash_write_pattern(qla_host_t *ha, uint32_t off, uint32_t size,
uint32_t pattern)
@ -942,7 +935,6 @@ qla_flash_write_pattern(qla_host_t *ha, uint32_t off, uint32_t size,
int rval = 0;
uint32_t start;
if ((rval = qla_p3p_sem_lock2(ha)))
goto qla_wr_pattern_exit;
@ -979,7 +971,6 @@ qla_flash_write_data(qla_host_t *ha, uint32_t off, uint32_t size,
uint32_t start;
uint32_t *data32 = data;
if ((rval = qla_p3p_sem_lock2(ha)))
goto qla_wr_pattern_exit;
@ -1011,7 +1002,7 @@ qla_flash_write_data(qla_host_t *ha, uint32_t off, uint32_t size,
qla_wr_pattern_exit:
return (rval);
}
int
qla_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size, void *buf,
uint32_t pattern)
@ -1019,7 +1010,6 @@ qla_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size, void *buf,
int rval = 0;
void *data;
if (size == 0)
return 0;
@ -1049,4 +1039,3 @@ qla_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size, void *buf,
qla_wr_flash_buffer_exit:
return (rval);
}

18
sys/dev/qlxgb/qla_os.c
View File

@ -378,7 +378,7 @@ qla_pci_attach(device_t dev)
ha->flags.qla_watchdog_active = 1;
ha->flags.qla_watchdog_pause = 1;
callout_init(&ha->tx_callout, 1);
/* create ioctl device interface */
@ -463,7 +463,6 @@ qla_sysctl_get_stats(SYSCTL_HANDLER_ARGS)
return (err);
}
/*
* Name: qla_release
* Function: Releases the resources allocated for the device
@ -639,7 +638,7 @@ qla_alloc_parent_dma_tag(qla_host_t *ha)
}
ha->flags.parent_tag = 1;
return (0);
}
@ -969,7 +968,7 @@ qla_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
qla_update_link_state(ha);
if (ha->hw.flags.link_up) {
ifmr->ifm_status |= IFM_ACTIVE;
@ -1061,7 +1060,6 @@ qla_send(qla_host_t *ha, struct mbuf **m_headp)
BUS_DMA_NOWAIT);
if (ret == EFBIG) {
struct mbuf *m;
QL_DPRINT8((ha->pci_dev, "%s: EFBIG [%d]\n", __func__,
@ -1081,7 +1079,6 @@ qla_send(qla_host_t *ha, struct mbuf **m_headp)
if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head,
segs, &nsegs, BUS_DMA_NOWAIT))) {
ha->err_tx_dmamap_load++;
device_printf(ha->pci_dev,
@ -1191,7 +1188,6 @@ qla_clear_tx_buf(qla_host_t *ha, qla_tx_buf_t *txb)
QL_DPRINT2((ha->pci_dev, "%s: enter\n", __func__));
if (txb->m_head) {
bus_dmamap_unload(ha->tx_tag, txb->map);
bus_dmamap_destroy(ha->tx_tag, txb->map);
@ -1219,7 +1215,6 @@ qla_free_xmt_bufs(qla_host_t *ha)
return;
}
static int
qla_alloc_rcv_bufs(qla_host_t *ha)
{
@ -1238,7 +1233,6 @@ qla_alloc_rcv_bufs(qla_host_t *ha)
NULL, /* lockfunc */
NULL, /* lockfuncarg */
&ha->rx_tag)) {
device_printf(ha->pci_dev, "%s: rx_tag alloc failed\n",
__func__);
@ -1258,7 +1252,6 @@ qla_alloc_rcv_bufs(qla_host_t *ha)
}
for (i = 0; i < NUM_RX_DESCRIPTORS; i++) {
rxb = &ha->rx_buf[i];
ret = bus_dmamap_create(ha->rx_tag, BUS_DMA_NOWAIT, &rxb->map);
@ -1298,9 +1291,7 @@ qla_alloc_rcv_bufs(qla_host_t *ha)
}
}
for (i = 0; i < NUM_RX_JUMBO_DESCRIPTORS; i++) {
rxb = &ha->rx_jbuf[i];
ret = bus_dmamap_create(ha->rx_tag, BUS_DMA_NOWAIT, &rxb->map);
@ -1407,7 +1398,6 @@ qla_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp,
ifp = ha->ifp;
if (mp == NULL) {
if (!jumbo) {
mp = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
@ -1441,7 +1431,6 @@ qla_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp,
mp->m_next = NULL;
}
offset = (uint32_t)((unsigned long long)mp->m_data & 0x7ULL);
if (offset) {
offset = 8 - offset;
@ -1480,4 +1469,3 @@ qla_tx_done(void *context, int pending)
qla_hw_tx_done(ha);
qla_start(ha->ifp);
}

5
sys/dev/qlxgb/qla_os.h
View File

@ -121,7 +121,6 @@ static __inline int qla_sec_to_hz(int sec)
return (tvtohz(&t));
}
#define qla_host_to_le16(x) htole16(x)
#define qla_host_to_le32(x) htole32(x)
#define qla_host_to_le64(x) htole64(x)
@ -145,13 +144,13 @@ MALLOC_DECLARE(M_QLA8XXXBUF);
else \
pause(fn, qla_ms_to_hz(msecs)); \
}
/*
* Locks
*/
#define QLA_LOCK(ha, str) qla_lock(ha, str);
#define QLA_UNLOCK(ha, str) qla_unlock(ha, str)
#define QLA_TX_LOCK(ha) mtx_lock(&ha->tx_lock);
#define QLA_TX_UNLOCK(ha) mtx_unlock(&ha->tx_lock);

5
sys/dev/qlxgb/qla_reg.h
View File

@ -81,7 +81,6 @@
/* Valid bit for a SEM<N>_LOCK registers */
#define SEM_LOCK_BIT 0x00000001
#define Q8_ROM_LOCKID 0x1B2100
/*******************************
@ -127,7 +126,6 @@
*/
#define COLD_BOOT_VALUE 0x12345678
#define Q8_MIU_TEST_AGT_CTRL 0x180090
#define Q8_MIU_TEST_AGT_ADDR_LO 0x180094
#define Q8_MIU_TEST_AGT_ADDR_HI 0x180098
@ -194,7 +192,7 @@
* 31:2 Reserved;
* 1:0 max address bytes for ROM Interface
*/
#define Q8_ROM_DUMMY_BYTE_COUNT 0x03310014
/*
* bit definitions for Q8_ROM_DUMMY_BYTE_COUNT
@ -207,7 +205,6 @@
#define Q8_ROM_DIRECT_WINDOW 0x03310030
#define Q8_ROM_DIRECT_DATA_OFFSET 0x03310000
#define Q8_NX_CDRP_CMD_RSP 0x1B2218
#define Q8_NX_CDRP_ARG1 0x1B221C
#define Q8_NX_CDRP_ARG2 0x1B2220