Do not pre-map the I/O port space. On the Intel Tiger 4 this conflicts

with a memory mapped I/O range that's immediately before it and is
not 256MB aligned. As a result, when an address is accessed in the
memory mapped range and a direct mapping is added for it, it overlaps
with the pre-mapped I/O port space and causes a machine check.

Based on a patch from: arun@
This commit is contained in:
marcel 2004-02-22 02:10:48 +00:00
parent 9576df9a82
commit 2a9068ac03
3 changed files with 0 additions and 35 deletions

View File

@ -399,37 +399,6 @@ map_pal_code(void)
__asm __volatile("srlz.i");
}
void
map_port_space(void)
{
struct ia64_pte pte;
u_int64_t psr;
/* XXX we should fail hard if there's no I/O port space. */
if (ia64_port_base == 0)
return;
bzero(&pte, sizeof(pte));
pte.pte_p = 1;
pte.pte_ma = PTE_MA_UC;
pte.pte_a = 1;
pte.pte_d = 1;
pte.pte_pl = PTE_PL_KERN;
pte.pte_ar = PTE_AR_RW;
pte.pte_ppn = ia64_port_base >> 12;
__asm __volatile("ptr.d %0,%1" :: "r"(ia64_port_base), "r"(24 << 2));
__asm __volatile("mov %0=psr" : "=r" (psr));
__asm __volatile("rsm psr.ic|psr.i");
__asm __volatile("srlz.d");
__asm __volatile("mov cr.ifa=%0" :: "r"(ia64_port_base));
__asm __volatile("mov cr.itir=%0" :: "r"(IA64_ID_PAGE_SHIFT << 2));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(*(u_int64_t*)&pte));
__asm __volatile("mov psr.l=%0" :: "r" (psr));
__asm __volatile("srlz.d");
}
void
map_gateway_page(void)
{
@ -546,8 +515,6 @@ ia64_init(void)
ia64_pal_base = mdp->PhysicalStart;
}
map_port_space();
metadata_missing = 0;
if (bootinfo.bi_modulep)
preload_metadata = (caddr_t)bootinfo.bi_modulep;

View File

@ -94,7 +94,6 @@ ia64_ap_startup(void)
ia64_set_k4((intptr_t)pcpup);
map_pal_code();
map_port_space();
map_gateway_page();
ia64_set_fpsr(IA64_FPSR_DEFAULT);

View File

@ -63,7 +63,6 @@ void ia64_probe_sapics(void);
int interrupt(uint64_t, struct trapframe *);
void map_gateway_page(void);
void map_pal_code(void);
void map_port_space(void);
void os_boot_rendez(void);
void os_mca(void);
void spillfd(void *src, void *dst);