Do not pre-map the I/O port space. On the Intel Tiger 4 this conflicts
with a memory mapped I/O range that's immediately before it and is not 256MB aligned. As a result, when an address is accessed in the memory mapped range and a direct mapping is added for it, it overlaps with the pre-mapped I/O port space and causes a machine check. Based on a patch from: arun@
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@ -399,37 +399,6 @@ map_pal_code(void)
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__asm __volatile("srlz.i");
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}
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void
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map_port_space(void)
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{
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struct ia64_pte pte;
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u_int64_t psr;
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/* XXX we should fail hard if there's no I/O port space. */
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if (ia64_port_base == 0)
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return;
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bzero(&pte, sizeof(pte));
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pte.pte_p = 1;
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pte.pte_ma = PTE_MA_UC;
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pte.pte_a = 1;
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pte.pte_d = 1;
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pte.pte_pl = PTE_PL_KERN;
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pte.pte_ar = PTE_AR_RW;
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pte.pte_ppn = ia64_port_base >> 12;
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__asm __volatile("ptr.d %0,%1" :: "r"(ia64_port_base), "r"(24 << 2));
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__asm __volatile("mov %0=psr" : "=r" (psr));
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__asm __volatile("rsm psr.ic|psr.i");
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__asm __volatile("srlz.d");
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__asm __volatile("mov cr.ifa=%0" :: "r"(ia64_port_base));
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__asm __volatile("mov cr.itir=%0" :: "r"(IA64_ID_PAGE_SHIFT << 2));
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__asm __volatile("itr.d dtr[%0]=%1" :: "r"(2), "r"(*(u_int64_t*)&pte));
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__asm __volatile("mov psr.l=%0" :: "r" (psr));
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__asm __volatile("srlz.d");
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}
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void
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map_gateway_page(void)
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{
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@ -546,8 +515,6 @@ ia64_init(void)
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ia64_pal_base = mdp->PhysicalStart;
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}
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map_port_space();
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metadata_missing = 0;
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if (bootinfo.bi_modulep)
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preload_metadata = (caddr_t)bootinfo.bi_modulep;
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@ -94,7 +94,6 @@ ia64_ap_startup(void)
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ia64_set_k4((intptr_t)pcpup);
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map_pal_code();
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map_port_space();
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map_gateway_page();
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ia64_set_fpsr(IA64_FPSR_DEFAULT);
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@ -63,7 +63,6 @@ void ia64_probe_sapics(void);
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int interrupt(uint64_t, struct trapframe *);
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void map_gateway_page(void);
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void map_pal_code(void);
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void map_port_space(void);
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void os_boot_rendez(void);
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void os_mca(void);
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void spillfd(void *src, void *dst);
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