Updates for the Mellanox ethernet driver
> List of fixes: * use correct format for GID printouts * double array indexing * spelling in printouts * void pointer arithmetic * allow more receive rings * correct maximum number of transmit rings * use "const" instead of "static" for constants * check for invalid VLAN tags * check for lack of IRQ resources > Added more hardware specific defines > Added more verbose printouts of firmware status codes Sponsored by: Mellanox Technologies MFC after: 3 days
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@ -757,6 +757,19 @@ static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
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"in_mod=0x%x, op_mod=0x%x, fw status = 0x%x\n",
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cmd_to_str(op), op, (unsigned long long) in_param, in_modifier,
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op_modifier, context->fw_status);
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switch(context->fw_status) {
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case CMD_STAT_BAD_PARAM:
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mlx4_err(dev, "Parameter is not supported, "
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"parameter is out of range\n");
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break;
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case CMD_STAT_EXCEED_LIM:
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mlx4_err(dev, "Required capability exceeded "
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"device limits\n");
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break;
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default:
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break;
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}
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goto out;
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}
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@ -241,8 +241,8 @@ static void *mlx4_en_add(struct mlx4_dev *dev)
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DEF_RX_RINGS)));
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} else {
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mdev->profile.prof[i].rx_ring_num = rounddown_pow_of_two(
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min_t(int, dev->caps.comp_pool/
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dev->caps.num_ports - 1 , MAX_MSIX_P_PORT - 1));
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min_t(int, dev->caps.comp_pool /
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dev->caps.num_ports, MAX_MSIX_P_PORT));
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}
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}
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@ -1305,7 +1305,7 @@ int mlx4_en_start_port(struct net_device *dev)
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cq = priv->tx_cq[i];
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err = mlx4_en_activate_cq(priv, cq, i);
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if (err) {
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en_err(priv, "Failed allocating Tx CQ\n");
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en_err(priv, "Failed activating Tx CQ\n");
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goto tx_err;
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}
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err = mlx4_en_set_cq_moder(priv, cq);
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@ -1323,7 +1323,7 @@ int mlx4_en_start_port(struct net_device *dev)
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err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
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i / priv->num_tx_rings_p_up);
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if (err) {
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en_err(priv, "Failed allocating Tx ring\n");
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en_err(priv, "Failed activating Tx ring %d\n", i);
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mlx4_en_deactivate_cq(priv, cq);
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goto tx_err;
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}
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@ -2189,6 +2189,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
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mlx4_en_destroy_netdev(dev);
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return err;
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}
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static int mlx4_en_set_ring_size(struct net_device *dev,
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int rx_size, int tx_size)
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{
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@ -2409,7 +2410,6 @@ static void mlx4_en_sysctl_conf(struct mlx4_en_priv *priv)
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"Enable adaptive rx coalescing");
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}
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static void mlx4_en_sysctl_stat(struct mlx4_en_priv *priv)
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{
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struct net_device *dev;
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@ -500,7 +500,7 @@ static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
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goto fail;
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/* Unmap buffer */
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pci_unmap_single(mdev->pdev, dma, frag_info[nr].frag_size,
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pci_unmap_single(mdev->pdev, dma, frag_info->frag_size,
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PCI_DMA_FROMDEVICE);
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}
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/* Adjust size of last fragment to match actual length */
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@ -710,16 +710,16 @@ u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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u32 rings_p_up = priv->num_tx_rings_p_up;
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u32 vlan_tag = 0;
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u32 up = 0;
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u32 queue_index;
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#if (MLX4_EN_NUM_UP > 1)
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/* Obtain VLAN information if present */
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if (mb->m_flags & M_VLANTAG) {
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vlan_tag = mb->m_pkthdr.ether_vtag;
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up = (vlan_tag >> 13);
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u32 vlan_tag = mb->m_pkthdr.ether_vtag;
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up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
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}
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#endif
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/* check if flowid is set */
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if (M_HASHTYPE_GET(mb) != M_HASHTYPE_NONE)
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queue_index = mb->m_pkthdr.flowid;
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@ -1303,8 +1303,9 @@ static ssize_t show_port_ib_mtu(struct device *dev,
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port_mtu_attr);
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struct mlx4_dev *mdev = info->dev;
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/* When port type is eth, port mtu value isn't used. */
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if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
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mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
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return -EINVAL;
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sprintf(buf, "%d\n",
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ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
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@ -2899,6 +2900,12 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
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goto retry;
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}
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kfree(entries);
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/* if error, or can't alloc even 1 IRQ */
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if (err < 0) {
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mlx4_err(dev, "No IRQs left, device can't "
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"be started.\n");
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goto no_irq;
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}
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goto no_msi;
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}
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@ -2926,6 +2933,10 @@ static void mlx4_enable_msi_x(struct mlx4_dev *dev)
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for (i = 0; i < 2; ++i)
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priv->eq_table.eq[i].irq = dev->pdev->irq;
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return;
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no_irq:
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dev->caps.num_comp_vectors = 0;
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dev->caps.comp_pool = 0;
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}
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static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
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@ -3301,6 +3312,13 @@ static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
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mutex_init(&priv->msix_ctl.pool_lock);
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mlx4_enable_msi_x(dev);
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/* no MSIX and no shared IRQ */
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if (!dev->caps.num_comp_vectors && !dev->caps.comp_pool) {
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err = -ENOSPC;
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goto err_free_eq;
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}
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if ((mlx4_is_mfunc(dev)) &&
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!(dev->flags & MLX4_FLAG_MSI_X)) {
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err = -ENOSYS;
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@ -36,6 +36,7 @@
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#include <linux/mlx4/cmd.h>
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#include <linux/module.h>
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#include <linux/printk.h>
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#include "mlx4.h"
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@ -690,8 +691,10 @@ static int find_entry(struct mlx4_dev *dev, u8 port,
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if (err)
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return err;
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if (0)
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mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
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if (0) {
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mlx4_dbg(dev, "Hash for "GID_PRINT_FMT" is %04x\n",
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GID_PRINT_ARGS(gid), hash);
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}
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*index = hash;
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*prev = -1;
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@ -912,10 +915,11 @@ static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
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case MLX4_NET_TRANS_RULE_ID_IB:
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len += snprintf(buf + len, BUF_SIZE - len,
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"dst-gid = %pI6\n", cur->ib.dst_gid);
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"dst-gid = "GID_PRINT_FMT"\n",
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GID_PRINT_ARGS(cur->ib.dst_gid));
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len += snprintf(buf + len, BUF_SIZE - len,
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"dst-gid-mask = %pI6\n",
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cur->ib.dst_gid_msk);
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"dst-gid-mask = "GID_PRINT_FMT"\n",
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GID_PRINT_ARGS(cur->ib.dst_gid_msk));
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break;
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case MLX4_NET_TRANS_RULE_ID_IPV6:
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@ -1135,7 +1139,8 @@ int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
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goto out;
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if (index == -1) {
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mlx4_err(dev, "MGID %pI6 not found\n", gid);
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mlx4_err(dev, "MGID "GID_PRINT_FMT" not found\n",
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GID_PRINT_ARGS(gid));
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err = -EINVAL;
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goto out;
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}
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@ -154,7 +154,7 @@ enum {
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#define MLX4_EN_NUM_UP 1
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#define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
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(MLX4_EN_NUM_UP + 1))
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MLX4_EN_NUM_UP)
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#define MLX4_EN_DEF_TX_RING_SIZE 1024
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#define MLX4_EN_DEF_RX_RING_SIZE 1024
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@ -358,11 +358,7 @@ struct mlx4_en_rx_ring {
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static inline int mlx4_en_can_lro(__be16 status)
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{
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static __be16 status_all;
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static __be16 status_ipv4_ipok_tcp;
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static __be16 status_ipv6_ipok_tcp;
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status_all = cpu_to_be16(
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const __be16 status_all = cpu_to_be16(
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MLX4_CQE_STATUS_IPV4 |
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MLX4_CQE_STATUS_IPV4F |
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MLX4_CQE_STATUS_IPV6 |
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@ -370,11 +366,11 @@ static inline int mlx4_en_can_lro(__be16 status)
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MLX4_CQE_STATUS_TCP |
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MLX4_CQE_STATUS_UDP |
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MLX4_CQE_STATUS_IPOK);
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status_ipv4_ipok_tcp = cpu_to_be16(
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const __be16 status_ipv4_ipok_tcp = cpu_to_be16(
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MLX4_CQE_STATUS_IPV4 |
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MLX4_CQE_STATUS_IPOK |
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MLX4_CQE_STATUS_TCP);
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status_ipv6_ipok_tcp = cpu_to_be16(
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const __be16 status_ipv6_ipok_tcp = cpu_to_be16(
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MLX4_CQE_STATUS_IPV6 |
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MLX4_CQE_STATUS_IPOK |
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MLX4_CQE_STATUS_TCP);
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@ -384,7 +380,6 @@ static inline int mlx4_en_can_lro(__be16 status)
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status == status_ipv6_ipok_tcp);
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}
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struct mlx4_en_cq {
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struct mlx4_cq mcq;
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struct mlx4_hwq_resources wqres;
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@ -186,8 +186,19 @@ enum {
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MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10,
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MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11,
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MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12,
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MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
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MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14
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MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
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MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14,
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MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15,
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MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16,
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MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17,
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MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
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MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19,
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MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20,
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MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21,
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MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22,
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MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23,
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MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24,
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MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25,
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};
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/* bit enums for an 8-bit flags field indicating special use
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@ -948,9 +959,9 @@ void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
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static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
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{
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if (BITS_PER_LONG == 64 || buf->nbufs == 1)
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return buf->direct.buf + offset;
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return (u8 *)buf->direct.buf + offset;
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else
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return buf->page_list[offset >> PAGE_SHIFT].buf +
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return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
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(offset & (PAGE_SIZE - 1));
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}
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@ -253,6 +253,8 @@ enum {
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MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
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MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
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MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32,
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MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32,
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};
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enum { /* param3 */
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