Fix a couple of bad races that can occur when a cxgbe interface is taken
down. The ingress queue lock was unused and has been removed as part of these changes. - An in-flight egress update from the SGE must be handled before the queue that requested it is destroyed. Wait for the update to arrive. - Interrupt handlers must stop processing rx events for a queue before the queue is destroyed. Events that have not yet been processed should be ignored once the queue disappears. MFC after: 1 week
This commit is contained in:
Navdeep Parhar
parent
a09001a82b
commit
2be67d2948
@ -227,6 +227,11 @@ enum {
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/* iq flags */
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IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */
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IQ_STARTED = (1 << 2), /* started */
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/* iq state */
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IQS_DISABLED = 0,
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IQS_BUSY = 1,
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IQS_IDLE = 2,
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};
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/*
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@ -244,7 +249,7 @@ struct sge_iq {
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iq_intr_handler_t *handler;
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__be64 *desc; /* KVA of descriptor ring */
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struct mtx iq_lock;
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volatile uint32_t state;
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struct adapter *adapter;
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const __be64 *cdesc; /* current descriptor */
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uint8_t gen; /* generation bit */
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@ -445,22 +450,12 @@ struct adapter {
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#define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
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#define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
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#define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock)
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#define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock)
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#define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED)
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#define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED)
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#define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
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#define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
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#define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
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#define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
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#define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
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#define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
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#define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
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#define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
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#define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
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#define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
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#define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
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#define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
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@ -586,6 +581,8 @@ void t4_intr_fwd(void *);
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void t4_intr_err(void *);
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void t4_intr_evt(void *);
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void t4_intr_data(void *);
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void t4_evt_rx(void *);
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void t4_eth_rx(void *);
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int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
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void t4_update_fl_bufsize(struct ifnet *);
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@ -32,6 +32,8 @@ __FBSDID("$FreeBSD$");
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#include "t4_regs_values.h"
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#include "t4fw_interface.h"
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#undef msleep
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#define msleep(x) DELAY((x) * 1000)
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/**
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* t4_wait_op_done_val - wait until an operation is completed
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@ -74,8 +74,6 @@ typedef boolean_t bool;
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#define false FALSE
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#define true TRUE
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#undef msleep
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#define msleep(x) DELAY((x) * 1000)
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#define mdelay(x) DELAY((x) * 1000)
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#define udelay(x) DELAY(x)
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@ -1038,8 +1038,21 @@ static void
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cxgbe_qflush(struct ifnet *ifp)
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{
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struct port_info *pi = ifp->if_softc;
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struct sge_txq *txq;
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int i;
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struct mbuf *m;
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device_printf(pi->dev, "%s unimplemented.\n", __func__);
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/* queues do not exist if !IFF_DRV_RUNNING. */
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if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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for_each_txq(pi, i, txq) {
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TXQ_LOCK(txq);
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m_freem(txq->m);
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while ((m = buf_ring_dequeue_sc(txq->eq.br)) != NULL)
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m_freem(m);
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TXQ_UNLOCK(txq);
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}
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}
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if_qflush(ifp);
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}
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static int
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@ -2673,8 +2686,11 @@ cxgbe_txq_start(void *arg, int count)
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struct sge_txq *txq = arg;
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TXQ_LOCK(txq);
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txq->eq.flags &= ~EQ_CRFLUSHED;
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txq_start(txq->ifp, txq);
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if (txq->eq.flags & EQ_CRFLUSHED) {
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txq->eq.flags &= ~EQ_CRFLUSHED;
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txq_start(txq->ifp, txq);
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} else
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wakeup_one(txq); /* txq is going away, wakeup free_txq */
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TXQ_UNLOCK(txq);
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}
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@ -279,7 +279,7 @@ t4_setup_adapter_iqs(struct adapter *sc)
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}
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}
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handler = t4_intr_evt;
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handler = t4_evt_rx;
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i = 0; /* forward fwq's interrupt to the first fiq */
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} else {
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handler = NULL;
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@ -345,7 +345,7 @@ t4_setup_eth_queues(struct port_info *pi)
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device_get_nameunit(pi->dev), i);
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init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
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pi->qsize_rxq, RX_IQ_ESIZE,
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sc->flags & INTR_FWD ? t4_intr_data: NULL, name);
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sc->flags & INTR_FWD ? t4_eth_rx : NULL, name);
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snprintf(name, sizeof(name), "%s rxq%d-fl",
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device_get_nameunit(pi->dev), i);
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@ -428,6 +428,9 @@ t4_intr_fwd(void *arg)
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int ndesc_pending = 0, ndesc_total = 0;
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int qid;
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if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY))
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return;
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while (is_new_response(iq, &ctrl)) {
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rmb();
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@ -460,6 +463,8 @@ t4_intr_fwd(void *arg)
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V_CIDXINC(ndesc_pending) | V_INGRESSQID((u32)iq->cntxt_id) |
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V_SEINTARM(iq->intr_params));
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}
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atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE);
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}
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/* Deals with error interrupts */
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@ -477,6 +482,32 @@ t4_intr_err(void *arg)
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/* Deals with the firmware event queue */
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void
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t4_intr_evt(void *arg)
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{
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struct sge_iq *iq = arg;
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if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY))
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return;
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t4_evt_rx(arg);
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atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE);
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}
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void
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t4_intr_data(void *arg)
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{
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struct sge_iq *iq = arg;
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if (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_BUSY))
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return;
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t4_eth_rx(arg);
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atomic_cmpset_32(&iq->state, IQS_BUSY, IQS_IDLE);
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}
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void
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t4_evt_rx(void *arg)
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{
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struct sge_iq *iq = arg;
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struct adapter *sc = iq->adapter;
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@ -537,7 +568,7 @@ t4_intr_evt(void *arg)
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}
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void
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t4_intr_data(void *arg)
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t4_eth_rx(void *arg)
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{
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struct sge_rxq *rxq = arg;
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struct sge_iq *iq = arg;
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@ -1017,8 +1048,6 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
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if (pi == NULL)
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pi = sc->port[0];
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mtx_init(&iq->iq_lock, iq->lockname, NULL, MTX_DEF);
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len = iq->qsize * iq->esize;
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rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
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(void **)&iq->desc);
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@ -1148,6 +1177,7 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
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}
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/* Enable IQ interrupts */
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atomic_store_rel_32(&iq->state, IQS_IDLE);
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t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
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V_INGRESSQID(iq->cntxt_id));
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@ -1179,6 +1209,10 @@ free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
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return (rc);
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}
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iq->flags &= ~IQ_STARTED;
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/* Synchronize with the interrupt handler */
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while (!atomic_cmpset_32(&iq->state, IQS_IDLE, IQS_DISABLED))
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pause("iqfree", hz / 1000);
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}
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if (iq->flags & IQ_ALLOCATED) {
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@ -1196,9 +1230,6 @@ free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
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free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
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if (mtx_initialized(&iq->iq_lock))
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mtx_destroy(&iq->iq_lock);
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bzero(iq, sizeof(*iq));
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if (fl) {
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@ -1425,6 +1456,27 @@ free_txq(struct port_info *pi, struct sge_txq *txq)
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struct sge_eq *eq = &txq->eq;
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if (eq->flags & (EQ_ALLOCATED | EQ_STARTED)) {
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/*
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* Wait for the response to a credit flush if there's one
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* pending. Clearing the flag tells handle_sge_egr_update or
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* cxgbe_txq_start (depending on how far the response has made
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* it) that they should ignore the response and wake up free_txq
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* instead.
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*
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* The interface has been marked down by the time we get here
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* (both IFF_UP and IFF_DRV_RUNNING cleared). qflush has
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* emptied the tx buf_rings and we know nothing new is being
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* queued for tx so we don't have to worry about a new credit
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* flush request.
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*/
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TXQ_LOCK(txq);
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if (eq->flags & EQ_CRFLUSHED) {
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eq->flags &= ~EQ_CRFLUSHED;
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msleep(txq, &eq->eq_lock, 0, "crflush", 0);
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}
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TXQ_UNLOCK(txq);
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rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
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if (rc != 0) {
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device_printf(pi->dev,
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@ -2444,13 +2496,14 @@ handle_sge_egr_update(struct adapter *sc, const struct cpl_sge_egr_update *cpl)
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struct port_info *pi;
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txq = (void *)s->eqmap[qid - s->eq_start];
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KASSERT(txq->eq.flags & EQ_CRFLUSHED,
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("%s: tx queue %p not expecting an update.", __func__, txq));
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pi = txq->ifp->if_softc;
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taskqueue_enqueue(pi->tq, &txq->resume_tx);
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txq->egr_update++;
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TXQ_LOCK(txq);
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if (txq->eq.flags & EQ_CRFLUSHED) {
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pi = txq->ifp->if_softc;
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taskqueue_enqueue(pi->tq, &txq->resume_tx);
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txq->egr_update++;
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} else
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wakeup_one(txq); /* txq is going away, wakeup free_txq */
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TXQ_UNLOCK(txq);
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return (0);
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}
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