Add in the last random assortment of missing bits for the AR9380 HAL.
Obtained from: Qualcomm Atheros
This commit is contained in:
adrian
parent
2ffb4155ab
commit
2bfda3c82e
@ -119,7 +119,6 @@ typedef enum {
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HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */
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HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */
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HAL_CAP_RIFS_RX = 39,
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HAL_CAP_RIFS_TX = 40,
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HAL_CAP_FORCE_PPM = 41,
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@ -156,7 +155,6 @@ typedef enum {
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HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */
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HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */
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HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */
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HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */
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HAL_CAP_BB_PANIC_WATCHDOG = 92,
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@ -229,6 +227,11 @@ typedef enum {
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#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
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/*
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* Receive queue types. These are used to tag
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* each transmit queue in the hardware and to identify a set
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* of transmit queues for operations such as start/stop dma.
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*/
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typedef enum {
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HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
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HAL_RX_QUEUE_LP = 1, /* low priority recv queue */
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@ -416,6 +419,23 @@ typedef enum {
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HAL_PM_UNDEFINED = 3
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} HAL_POWER_MODE;
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/*
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* Enterprise mode flags
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*/
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#define AH_ENT_DUAL_BAND_DISABLE 0x00000001
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#define AH_ENT_CHAIN2_DISABLE 0x00000002
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#define AH_ENT_5MHZ_DISABLE 0x00000004
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#define AH_ENT_10MHZ_DISABLE 0x00000008
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#define AH_ENT_49GHZ_DISABLE 0x00000010
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#define AH_ENT_LOOPBACK_DISABLE 0x00000020
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#define AH_ENT_TPC_PERF_DISABLE 0x00000040
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#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080
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#define AH_ENT_SPECTRAL_PRECISION 0x00000300
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#define AH_ENT_SPECTRAL_PRECISION_S 8
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#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000
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#define AH_FIRST_DESC_NDELIMS 60
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/*
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* NOTE WELL:
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* These are mapped to take advantage of the common locations for many of
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@ -455,7 +475,7 @@ typedef enum {
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HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
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HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
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/* Atheros ref driver has a generic timer interrupt now..*/
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HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
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HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
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HAL_INT_CST = 0x10000000, /* Non-common mapping */
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HAL_INT_GTT = 0x20000000, /* Non-common mapping */
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HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
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@ -507,6 +527,33 @@ typedef enum {
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HAL_INT_THRESHOLD
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} HAL_INT_MITIGATION;
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/* XXX this is duplicate information! */
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typedef struct {
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u_int32_t cyclecnt_diff; /* delta cycle count */
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u_int32_t rxclr_cnt; /* rx clear count */
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u_int32_t txframecnt_diff; /* delta tx frame count */
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u_int32_t rxframecnt_diff; /* delta rx frame count */
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u_int32_t listen_time; /* listen time in msec - time for which ch is free */
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u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */
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u_int32_t cckphyerr_cnt; /* CCK err count since last reset */
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u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */
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HAL_BOOL valid; /* if the stats are valid*/
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} HAL_ANISTATS;
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typedef struct {
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u_int8_t txctl_offset;
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u_int8_t txctl_numwords;
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u_int8_t txstatus_offset;
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u_int8_t txstatus_numwords;
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u_int8_t rxctl_offset;
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u_int8_t rxctl_numwords;
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u_int8_t rxstatus_offset;
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u_int8_t rxstatus_numwords;
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u_int8_t macRevision;
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} HAL_DESC_INFO;
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typedef enum {
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HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
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HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1,
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@ -545,6 +592,17 @@ typedef struct {
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uint32_t beacons;
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} HAL_MIB_STATS;
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/*
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* These bits represent what's in ah_currentRDext.
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*/
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typedef enum {
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REG_EXT_FCC_MIDBAND = 0,
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REG_EXT_JAPAN_MIDBAND = 1,
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REG_EXT_FCC_DFS_HT40 = 2,
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REG_EXT_JAPAN_NONDFS_HT40 = 3,
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REG_EXT_JAPAN_DFS_HT40 = 4
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} REG_EXT_BITMAP;
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enum {
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HAL_MODE_11A = 0x001, /* 11a channels */
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HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
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@ -613,7 +671,7 @@ typedef struct {
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#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
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#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
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#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
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u_int tx_power_cap;
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u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */
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} HAL_11N_RATE_SERIES;
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typedef enum {
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@ -637,6 +695,11 @@ typedef enum {
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HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
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} HAL_HT_RXCLEAR;
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typedef enum {
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HAL_FREQ_BAND_5GHZ = 0,
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HAL_FREQ_BAND_2GHZ = 1,
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} HAL_FREQ_BAND;
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/*
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* Antenna switch control. By default antenna selection
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* enables multiple (2) antenna use. To force use of the
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@ -665,6 +728,18 @@ typedef struct {
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uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
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} HAL_KEYVAL;
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/*
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* This is the TX descriptor field which marks the key padding requirement.
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* The naming is unfortunately unclear.
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*/
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#define AH_KEYTYPE_MASK 0x0F
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typedef enum {
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HAL_KEY_TYPE_CLEAR,
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HAL_KEY_TYPE_WEP,
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HAL_KEY_TYPE_AES,
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HAL_KEY_TYPE_TKIP,
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} HAL_KEY_TYPE;
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typedef enum {
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HAL_CIPHER_WEP = 0,
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HAL_CIPHER_AES_OCB = 1,
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@ -694,8 +769,10 @@ typedef struct {
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uint32_t bs_nextdtim; /* next DTIM in TU */
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uint32_t bs_intval; /* beacon interval+flags */
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#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
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#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */
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#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
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#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
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#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */
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uint32_t bs_dtimperiod;
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uint16_t bs_cfpperiod; /* CFP period in TU */
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uint16_t bs_cfpmaxduration; /* max CFP duration in TU */
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@ -703,6 +780,7 @@ typedef struct {
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uint16_t bs_timoffset; /* byte offset to TIM bitmap */
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uint16_t bs_bmissthreshold; /* beacon miss threshold */
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uint32_t bs_sleepduration; /* max sleep duration */
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uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */
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} HAL_BEACON_STATE;
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/*
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@ -733,6 +811,7 @@ typedef struct {
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#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
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struct ath_desc;
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struct ath_tx_status;
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struct ath_rx_status;
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@ -790,6 +869,8 @@ typedef enum {
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HAL_ANI_MRC_CCK = 8,
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} HAL_ANI_CMD;
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#define HAL_ANI_ALL 0xffffffff
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/*
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* This is the layout of the ANI INTMIT capability.
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*
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@ -805,7 +886,6 @@ typedef enum {
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HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
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} HAL_CAP_INTMIT_CMD;
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/* DFS defines */
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typedef struct {
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int32_t pe_firpwr; /* FIR pwr out threshold */
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int32_t pe_rrssi; /* Radar rssi thresh */
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@ -845,10 +925,10 @@ typedef enum {
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HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */
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} HAL_DFS_DOMAIN;
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/*
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* MFP decryption options for initializing the MAC.
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*/
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typedef enum {
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HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
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HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */
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@ -902,6 +982,20 @@ struct hal_dfs_event {
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};
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typedef struct hal_dfs_event HAL_DFS_EVENT;
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/*
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* Generic Timer domain
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*/
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typedef enum {
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HAL_GEN_TIMER_TSF = 0,
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HAL_GEN_TIMER_TSF2,
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HAL_GEN_TIMER_TSF_ANY
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} HAL_GEN_TIMER_DOMAIN;
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typedef enum {
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HAL_RESET_NONE = 0x0,
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HAL_RESET_BBPANIC = 0x1,
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} HAL_RESET_TYPE;
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/*
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* BT Co-existence definitions
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*/
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@ -1035,6 +1129,34 @@ typedef struct {
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HAL_BOOL bt_hold_rxclear;
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} HAL_BT_COEX_CONFIG;
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struct hal_bb_panic_info {
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u_int32_t status;
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u_int32_t tsf;
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u_int32_t phy_panic_wd_ctl1;
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u_int32_t phy_panic_wd_ctl2;
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u_int32_t phy_gen_ctrl;
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u_int32_t rxc_pcnt;
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u_int32_t rxf_pcnt;
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u_int32_t txf_pcnt;
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u_int32_t cycles;
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u_int32_t wd;
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u_int32_t det;
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u_int32_t rdar;
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u_int32_t r_odfm;
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u_int32_t r_cck;
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u_int32_t t_odfm;
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u_int32_t t_cck;
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u_int32_t agc;
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u_int32_t src;
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};
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/* Serialize Register Access Mode */
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typedef enum {
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SER_REG_MODE_OFF = 0,
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SER_REG_MODE_ON = 1,
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SER_REG_MODE_AUTO = 2,
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} SER_REG_MODE;
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typedef struct
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{
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int ah_debug; /* only used if AH_DEBUG is defined */
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@ -1046,6 +1168,44 @@ typedef struct
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int ah_additional_swba_backoff; /* in TU's */
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int ah_force_full_reset; /* force full chip reset rather then warm reset */
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int ah_serialise_reg_war; /* force serialisation of register IO */
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/* XXX these don't belong here, they're just for the ar9300 HAL port effort */
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int ath_hal_desc_tpc; /* Per-packet TPC */
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int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */
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int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */
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int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */
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int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */
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/* I'm not sure what the default values for these should be */
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int ath_hal_pll_pwr_save;
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int ath_hal_pcie_power_save_enable;
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int ath_hal_intr_mitigation_rx;
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int ath_hal_intr_mitigation_tx;
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int ath_hal_pcie_clock_req;
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#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0)
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#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1)
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#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2)
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int ath_hal_pcie_waen;
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int ath_hal_pcie_ser_des_write;
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/* these are important for correct AR9300 behaviour */
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int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */
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int ath_hal_diversity_control;
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int ath_hal_antenna_switch_swap;
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int ath_hal_ext_lna_ctl_gpio;
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int ath_hal_spur_mode;
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int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */
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int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */
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int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */
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/* For now, set this to 0 - net80211 needs to know about hardware MFP support */
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int ath_hal_mfp_support;
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int ath_hal_enable_ani; /* should set this.. */
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int ath_hal_cwm_ignore_ext_cca;
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int ath_hal_show_bb_panic;
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} HAL_OPS_CONFIG;
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/*
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@ -1298,12 +1458,23 @@ struct ath_hal {
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void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *,
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struct ath_desc *, u_int, u_int,
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HAL_11N_RATE_SERIES [], u_int, u_int);
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/*
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* The next 4 (set11ntxdesc -> set11naggrlast) are specific
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* to the EDMA HAL. Descriptors are chained together by
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* using filltxdesc (not ChainTxDesc) and then setting the
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* aggregate flags appropriately using first/middle/last.
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*/
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void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *,
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void *, u_int, HAL_PKT_TYPE, u_int, u_int,
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u_int);
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void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *,
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struct ath_desc *, u_int);
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void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *,
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struct ath_desc *, u_int);
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void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *,
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struct ath_desc *);
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void __ahdecl(*ah_clr11nAggr)(struct ath_hal *,
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struct ath_desc *);
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void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *,
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@ -136,6 +136,41 @@ struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
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#define AH_MAXCHAN 96
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#endif
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#define HAL_NF_CAL_HIST_LEN_FULL 5
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#define HAL_NF_CAL_HIST_LEN_SMALL 1
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#define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */
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#define HAL_NF_LOAD_DELAY 1000
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/*
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* PER_CHAN doesn't work for now, as it looks like the device layer
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* has to pre-populate the per-channel list with nominal values.
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*/
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//#define ATH_NF_PER_CHAN 1
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typedef struct {
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u_int8_t curr_index;
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int8_t invalidNFcount; /* TO DO: REMOVE THIS! */
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int16_t priv_nf[HAL_NUM_NF_READINGS];
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} HAL_NFCAL_BASE;
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typedef struct {
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HAL_NFCAL_BASE base;
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int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
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} HAL_NFCAL_HIST_FULL;
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typedef struct {
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HAL_NFCAL_BASE base;
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int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
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} HAL_NFCAL_HIST_SMALL;
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#ifdef ATH_NF_PER_CHAN
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typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
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#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
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#else
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typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
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#define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
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#endif /* ATH_NF_PER_CHAN */
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/*
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* Internal per-channel state. These are found
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* using ic_devdata in the ieee80211_channel.
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@ -157,6 +192,12 @@ typedef struct {
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int16_t noiseFloorExt[AH_MAX_CHAINS];
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#endif /* AH_SUPPORT_AR5416 */
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uint16_t mainSpur; /* cached spur value for this channel */
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/*XXX TODO: make these part of privFlags */
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uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */
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paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
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int one_time_cals_done;
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HAL_CHAN_NFCAL_HIST nf_cal_hist;
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} HAL_CHANNEL_INTERNAL;
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/* channel requires noise floor check */
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@ -253,13 +294,21 @@ typedef struct {
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uint8_t halTxStreams;
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uint8_t halRxStreams;
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HAL_MFP_OPT_T halMfpSupport;
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/* AR9300 HAL porting capabilities */
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int hal_paprd_enabled;
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int hal_pcie_lcr_offset;
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int hal_pcie_lcr_extsync_en;
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int halNumTxMaps;
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int halTxDescLen;
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int halTxStatusLen;
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int halRxStatusLen;
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int halRxHpFifoDepth;
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int halRxLpFifoDepth;
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uint32_t halRegCap; /* XXX needed? */
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int halNumMRRetries;
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int hal_ani_poll_interval;
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int hal_channel_switch_time_usec;
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} HAL_CAPABILITIES;
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struct regDomain;
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@ -364,6 +413,10 @@ struct ath_hal_private {
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*/
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uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
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int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
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#ifndef ATH_NF_PER_CHAN
|
||||
HAL_NFCAL_HIST_FULL nf_cal_hist;
|
||||
#endif /* ! ATH_NF_PER_CHAN */
|
||||
};
|
||||
|
||||
#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
|
||||
@ -524,6 +577,14 @@ isBigEndian(void)
|
||||
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
|
||||
#define OS_REG_IS_BIT_SET(_a, _r, _f) \
|
||||
((OS_REG_READ(_a, _r) & (_f)) != 0)
|
||||
#define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
|
||||
OS_REG_WRITE(_a, _r, \
|
||||
(OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
|
||||
(((_v) << _f##_S) & (_f<<_f##_S)))
|
||||
#define OS_REG_READ_FIELD(_a, _r, _f) \
|
||||
(((OS_REG_READ(_a, _r) & _f) >> _f##_S))
|
||||
#define OS_REG_READ_FIELD_ALT(_a, _r, _f) \
|
||||
((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
|
||||
|
||||
/* Analog register writes may require a delay between each one (eg Merlin?) */
|
||||
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
|
||||
@ -732,6 +793,17 @@ enum {
|
||||
| HAL_MAC_HANG_UNKNOWN,
|
||||
};
|
||||
|
||||
/* Merge these with above */
|
||||
typedef enum hal_hw_hangs {
|
||||
HAL_DFS_BB_HANG_WAR = 0x1,
|
||||
HAL_RIFS_BB_HANG_WAR = 0x2,
|
||||
HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
|
||||
HAL_MAC_HANG_WAR = 0x8,
|
||||
HAL_PHYRESTART_CLR_WAR = 0x10,
|
||||
HAL_MAC_HANG_DETECTED = 0x40000000,
|
||||
HAL_BB_HANG_DETECTED = 0x80000000
|
||||
} hal_hw_hangs_t;
|
||||
|
||||
/*
|
||||
* Device revision information.
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user