Convert the imx5 interrupt controller driver to INTRNG.
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4c7a024bff
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2c10dcc47b
@ -118,3 +118,5 @@ device wlan_amrr # AMRR transmit rate control algorithm
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# Flattened Device Tree
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options FDT # Configure using FDT/DTB data
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makeoptions MODULES_EXTRA=dtb/imx5
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options INTRNG
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@ -34,14 +34,12 @@ __FBSDID("$FreeBSD$");
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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@ -51,26 +49,178 @@ __FBSDID("$FreeBSD$");
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#include <arm/freescale/imx/imx51_tzicreg.h>
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#include "pic_if.h"
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#define TZIC_NIRQS 128
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struct tzic_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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struct tzic_softc {
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struct resource * tzic_res[3];
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bus_space_tag_t tzic_bst;
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bus_space_handle_t tzic_bsh;
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uint8_t ver;
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device_t dev;
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struct resource *tzicregs;
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struct tzic_irqsrc isrcs[TZIC_NIRQS];
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};
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static struct resource_spec tzic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct tzic_softc *tzic_sc;
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static struct tzic_softc *tzic_sc = NULL;
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static inline uint32_t
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tzic_read_4(struct tzic_softc *sc, int reg)
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{
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#define tzic_read_4(reg) \
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bus_space_read_4(tzic_sc->tzic_bst, tzic_sc->tzic_bsh, reg)
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#define tzic_write_4(reg, val) \
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bus_space_write_4(tzic_sc->tzic_bst, tzic_sc->tzic_bsh, reg, val)
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return (bus_read_4(sc->tzicregs, reg));
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}
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static void tzic_post_filter(void *);
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static inline void
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tzic_write_4(struct tzic_softc *sc, int reg, uint32_t val)
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{
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bus_write_4(sc->tzicregs, reg, val);
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}
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static inline void
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tzic_irq_eoi(struct tzic_softc *sc)
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{
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tzic_write_4(sc, TZIC_PRIOMASK, 0xff);
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}
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static inline void
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tzic_irq_mask(struct tzic_softc *sc, u_int irq)
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{
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tzic_write_4(sc, TZIC_ENCLEAR(irq >> 5), (1u << (irq & 0x1f)));
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}
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static inline void
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tzic_irq_unmask(struct tzic_softc *sc, u_int irq)
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{
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tzic_write_4(sc, TZIC_ENSET(irq >> 5), (1u << (irq & 0x1f)));
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}
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static int
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tzic_intr(void *arg)
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{
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struct tzic_softc *sc = arg;
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int b, i, irq;
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uint32_t pending;
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/* Get active interrupt */
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for (i = 0; i < TZIC_NIRQS / 32; ++i) {
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pending = tzic_read_4(sc, TZIC_PND(i));
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if ((b = 31 - __builtin_clz(pending)) < 0)
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continue;
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irq = i * 32 + b;
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tzic_write_4(sc, TZIC_PRIOMASK, 0);
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if (intr_isrc_dispatch(&sc->isrcs[irq].isrc,
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curthread->td_intr_frame) != 0) {
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tzic_irq_mask(sc, irq);
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tzic_irq_eoi(sc);
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arm_irq_memory_barrier(irq);
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if (bootverbose) {
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device_printf(sc->dev,
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"Stray irq %u disabled\n", irq);
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}
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}
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return (FILTER_HANDLED);
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}
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if (bootverbose)
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device_printf(sc->dev, "Spurious interrupt detected\n");
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return (FILTER_HANDLED);
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}
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static void
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tzic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq = ((struct tzic_irqsrc *)isrc)->irq;
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struct tzic_softc *sc = device_get_softc(dev);
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arm_irq_memory_barrier(irq);
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tzic_irq_unmask(sc, irq);
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}
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static void
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tzic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq = ((struct tzic_irqsrc *)isrc)->irq;
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struct tzic_softc *sc = device_get_softc(dev);
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tzic_irq_mask(sc, irq);
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}
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static int
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tzic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct intr_map_data_fdt *daf;
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struct tzic_softc *sc;
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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daf = (struct intr_map_data_fdt *)data;
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if (daf->ncells != 1 || daf->cells[0] >= TZIC_NIRQS)
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return (EINVAL);
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sc = device_get_softc(dev);
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*isrcp = &sc->isrcs[daf->cells[0]].isrc;
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return (0);
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}
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static void
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tzic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct tzic_softc *sc = device_get_softc(dev);
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tzic_irq_mask(sc, ((struct tzic_irqsrc *)isrc)->irq);
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tzic_irq_eoi(sc);
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}
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static void
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tzic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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tzic_enable_intr(dev, isrc);
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}
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static void
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tzic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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tzic_irq_eoi(device_get_softc(dev));
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}
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static int
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tzic_pic_attach(struct tzic_softc *sc)
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{
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struct intr_pic *pic;
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const char *name;
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intptr_t xref;
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int error;
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u_int irq;
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name = device_get_nameunit(sc->dev);
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for (irq = 0; irq < TZIC_NIRQS; irq++) {
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sc->isrcs[irq].irq = irq;
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error = intr_isrc_register(&sc->isrcs[irq].isrc,
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sc->dev, 0, "%s,%u", name, irq);
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if (error != 0)
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return (error);
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}
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xref = OF_xref_from_node(ofw_bus_get_node(sc->dev));
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pic = intr_pic_register(sc->dev, xref);
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if (pic == NULL)
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return (ENXIO);
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return (intr_pic_claim_root(sc->dev, xref, tzic_intr, sc, 0));
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}
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static int
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tzic_probe(device_t dev)
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@ -89,42 +239,47 @@ tzic_probe(device_t dev)
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static int
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tzic_attach(device_t dev)
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{
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struct tzic_softc *sc = device_get_softc(dev);
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int i;
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uint32_t reg;
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struct tzic_softc *sc = device_get_softc(dev);
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int i;
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if (tzic_sc)
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return (ENXIO);
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tzic_sc = sc;
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sc->dev = dev;
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if (bus_alloc_resources(dev, tzic_spec, sc->tzic_res)) {
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i = 0;
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sc->tzicregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
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RF_ACTIVE);
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if (sc->tzicregs == NULL) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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arm_post_filter = tzic_post_filter;
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/* Distributor Interface */
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sc->tzic_bst = rman_get_bustag(sc->tzic_res[0]);
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sc->tzic_bsh = rman_get_bushandle(sc->tzic_res[0]);
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tzic_sc = sc;
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reg = tzic_read_4(TZIC_INTCNTL);
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tzic_write_4(TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
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reg = tzic_read_4(TZIC_INTCNTL);
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tzic_write_4(TZIC_PRIOMASK, 0x1f);
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reg = tzic_read_4(TZIC_PRIOMASK);
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tzic_write_4(TZIC_SYNCCTRL, 0x02);
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reg = tzic_read_4(TZIC_SYNCCTRL);
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/* route all interrupts to IRQ. secure interrupts are for FIQ */
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for (i = 0; i < 4; i++)
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tzic_write_4(TZIC_INTSEC(i), 0xffffffff);
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tzic_write_4(sc, TZIC_INTSEC(i), 0xffffffff);
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/* disable all interrupts */
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for (i = 0; i < 4; i++)
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tzic_write_4(TZIC_ENCLEAR(i), 0xffffffff);
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tzic_write_4(sc, TZIC_ENCLEAR(i), 0xffffffff);
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/* Set all interrupts to priority 0 (max). */
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for (i = 0; i < 128 / 4; ++i)
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tzic_write_4(sc, TZIC_PRIORITY(i), 0);
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/*
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* Set priority mask to lowest (unmasked) prio, set synchronizer to
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* low-latency mode (as opposed to low-power), enable the controller.
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*/
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tzic_write_4(sc, TZIC_PRIOMASK, 0xff);
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tzic_write_4(sc, TZIC_SYNCCTRL, 0);
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tzic_write_4(sc, TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
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/* Register as a root pic. */
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if (tzic_pic_attach(sc) != 0) {
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device_printf(dev, "could not attach PIC\n");
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return (ENXIO);
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}
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return (0);
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}
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@ -132,7 +287,15 @@ tzic_attach(device_t dev)
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static device_method_t tzic_methods[] = {
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DEVMETHOD(device_probe, tzic_probe),
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DEVMETHOD(device_attach, tzic_attach),
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{ 0, 0 }
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DEVMETHOD(pic_disable_intr, tzic_disable_intr),
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DEVMETHOD(pic_enable_intr, tzic_enable_intr),
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DEVMETHOD(pic_map_intr, tzic_map_intr),
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DEVMETHOD(pic_post_filter, tzic_post_filter),
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DEVMETHOD(pic_post_ithread, tzic_post_ithread),
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DEVMETHOD(pic_pre_ithread, tzic_pre_ithread),
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DEVMETHOD_END
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};
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static driver_t tzic_driver = {
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@ -143,48 +306,5 @@ static driver_t tzic_driver = {
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static devclass_t tzic_devclass;
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/*
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* Memory space of controller located outside of device range, so let him to
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* attach not only to simplebus, but ofwbus also.
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*/
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EARLY_DRIVER_MODULE(tzic, ofwbus, tzic_driver, tzic_devclass, 0, 0,
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BUS_PASS_INTERRUPT);
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EARLY_DRIVER_MODULE(tzic, simplebus, tzic_driver, tzic_devclass, 0, 0,
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BUS_PASS_INTERRUPT);
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static void
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tzic_post_filter(void *arg)
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{
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}
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int
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arm_get_next_irq(int last_irq)
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{
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uint32_t pending;
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int i, b;
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for (i = 0; i < 4; i++) {
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pending = tzic_read_4(TZIC_PND(i));
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for (b = 0; pending != 0 && b < 32; b++)
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if (pending & (1 << b)) {
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return (i * 32 + b);
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}
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}
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return (-1);
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}
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void
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arm_mask_irq(uintptr_t nb)
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{
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tzic_write_4(TZIC_ENCLEAR(nb / 32), (1UL <<(nb % 32)));
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}
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void
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arm_unmask_irq(uintptr_t nb)
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{
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tzic_write_4(TZIC_ENSET(nb / 32), (1UL <<(nb % 32)));
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}
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