Move all of the XSAVE support under #ifdef I686_CPU and fix the build
without I686_CPU.
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jhb
parent
361372e423
commit
2c3d3d2d72
@ -670,10 +670,14 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
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regs = td->td_frame;
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oonstack = sigonstack(regs->tf_esp);
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#ifdef CPU_ENABLE_SSE
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if (cpu_max_ext_state_size > sizeof(union savefpu) && use_xsave) {
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xfpusave_len = cpu_max_ext_state_size - sizeof(union savefpu);
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xfpusave = __builtin_alloca(xfpusave_len);
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} else {
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#else
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{
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#endif
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xfpusave_len = 0;
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xfpusave = NULL;
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}
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@ -2908,7 +2912,9 @@ init386(first)
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unsigned long gdtmachpfn;
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int error, gsel_tss, metadata_missing, x, pa;
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struct pcpu *pc;
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#ifdef CPU_ENABLE_SSE
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struct xstate_hdr *xhdr;
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#endif
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struct callback_register event = {
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.type = CALLBACKTYPE_event,
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.address = {GSEL(GCODE_SEL, SEL_KPL), (unsigned long)Xhypervisor_callback },
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@ -3117,11 +3123,13 @@ init386(first)
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*/
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thread0.td_pcb = get_pcb_td(&thread0);
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bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
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1);
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xhdr->xstate_bv = xsave_mask;
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}
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#endif
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PCPU_SET(curpcb, thread0.td_pcb);
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/* make an initial tss so cpu can get interrupt stack on syscall! */
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/* Note: -16 is so we can grow the trapframe if we came from vm86 */
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@ -3162,7 +3170,9 @@ init386(first)
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struct gate_descriptor *gdp;
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int gsel_tss, metadata_missing, x, pa;
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struct pcpu *pc;
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#ifdef CPU_ENABLE_SSE
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struct xstate_hdr *xhdr;
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#endif
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thread0.td_kstack = proc0kstack;
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thread0.td_kstack_pages = KSTACK_PAGES;
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@ -3417,11 +3427,13 @@ init386(first)
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*/
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thread0.td_pcb = get_pcb_td(&thread0);
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bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
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1);
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xhdr->xstate_bv = xsave_mask;
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}
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#endif
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PCPU_SET(curpcb, thread0.td_pcb);
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/* make an initial tss so cpu can get interrupt stack on syscall! */
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/* Note: -16 is so we can grow the trapframe if we came from vm86 */
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@ -3886,7 +3898,9 @@ static void
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get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
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size_t xfpusave_len)
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{
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#ifdef CPU_ENABLE_SSE
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size_t max_len, len;
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#endif
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#ifndef DEV_NPX
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mcp->mc_fpformat = _MC_FPFMT_NODEV;
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@ -3897,6 +3911,7 @@ get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
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bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0],
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sizeof(mcp->mc_fpstate));
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mcp->mc_fpformat = npxformat();
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#ifdef CPU_ENABLE_SSE
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if (!use_xsave || xfpusave_len == 0)
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return;
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max_len = cpu_max_ext_state_size - sizeof(union savefpu);
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@ -3909,6 +3924,7 @@ get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
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mcp->mc_xfpustate_len = len;
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bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len);
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#endif
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#endif
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}
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static int
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@ -106,6 +106,10 @@ __FBSDID("$FreeBSD$");
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#define NSFBUFS (512 + maxusers * 16)
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#endif
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#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
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#define CPU_ENABLE_SSE
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#endif
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_Static_assert(OFFSETOF_CURTHREAD == offsetof(struct pcpu, pc_curthread),
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"OFFSETOF_CURTHREAD does not correspond with offset of pc_curthread.");
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_Static_assert(OFFSETOF_CURPCB == offsetof(struct pcpu, pc_curpcb),
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@ -152,14 +156,18 @@ void *
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alloc_fpusave(int flags)
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{
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void *res;
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#ifdef CPU_ENABLE_SSE
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struct savefpu_ymm *sf;
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#endif
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res = malloc(cpu_max_ext_state_size, M_DEVBUF, flags);
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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sf = (struct savefpu_ymm *)res;
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bzero(&sf->sv_xstate.sx_hd, sizeof(sf->sv_xstate.sx_hd));
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sf->sv_xstate.sx_hd.xstate_bv = xsave_mask;
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}
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#endif
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return (res);
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}
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/*
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@ -398,17 +406,21 @@ void
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cpu_thread_alloc(struct thread *td)
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{
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struct pcb *pcb;
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#ifdef CPU_ENABLE_SSE
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struct xstate_hdr *xhdr;
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#endif
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td->td_pcb = pcb = get_pcb_td(td);
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td->td_frame = (struct trapframe *)((caddr_t)pcb - 16) - 1;
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pcb->pcb_ext = NULL;
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pcb->pcb_save = get_pcb_user_save_pcb(pcb);
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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xhdr = (struct xstate_hdr *)(pcb->pcb_save + 1);
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bzero(xhdr, sizeof(*xhdr));
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xhdr->xstate_bv = xsave_mask;
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}
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#endif
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}
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void
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@ -212,17 +212,21 @@ int hw_float;
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SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
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&hw_float, 0, "Floating point instructions executed in hardware");
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#ifdef CPU_ENABLE_SSE
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int use_xsave;
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uint64_t xsave_mask;
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#endif
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static uma_zone_t fpu_save_area_zone;
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static union savefpu *npx_initialstate;
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#ifdef CPU_ENABLE_SSE
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struct xsave_area_elm_descr {
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u_int offset;
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u_int size;
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} *xsave_area_desc;
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static int use_xsaveopt;
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#endif
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static volatile u_int npx_traps_while_probing;
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@ -338,6 +342,7 @@ npx_probe(void)
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return (hw_float);
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}
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#ifdef CPU_ENABLE_SSE
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/*
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* Enable XSAVE if supported and allowed by user.
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* Calculate the xsave_mask.
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@ -373,13 +378,15 @@ npxinit_bsp1(void)
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if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0)
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use_xsaveopt = 1;
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}
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#endif
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/*
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* Calculate the fpu save area size.
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*/
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static void
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npxinit_bsp2(void)
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{
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#ifdef CPU_ENABLE_SSE
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u_int cp[4];
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if (use_xsave) {
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@ -392,6 +399,7 @@ npxinit_bsp2(void)
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do_cpuid(1, cp);
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cpu_feature2 = cp[2];
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} else
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#endif
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cpu_max_ext_state_size = sizeof(union savefpu);
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}
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@ -403,19 +411,25 @@ npxinit(bool bsp)
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{
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static union savefpu dummy;
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register_t saveintr;
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#ifdef CPU_ENABLE_SSE
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u_int mxcsr;
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#endif
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u_short control;
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if (bsp) {
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if (!npx_probe())
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return;
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#ifdef CPU_ENABLE_SSE
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npxinit_bsp1();
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#endif
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}
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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load_cr4(rcr4() | CR4_XSAVE);
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load_xcr(XCR0, xsave_mask);
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}
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#endif
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/*
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* XCR0 shall be set up before CPU can report the save area size.
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@ -459,7 +473,9 @@ static void
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npxinitstate(void *arg __unused)
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{
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register_t saveintr;
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#ifdef CPU_ENABLE_SSE
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int cp[4], i, max_ext_n;
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#endif
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if (!hw_float)
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return;
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@ -495,6 +511,7 @@ npxinitstate(void *arg __unused)
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bzero(npx_initialstate->sv_87.sv_ac,
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sizeof(npx_initialstate->sv_87.sv_ac));
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#ifdef CPU_ENABLE_SSE
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/*
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* Create a table describing the layout of the CPU Extended
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* Save Area.
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@ -519,6 +536,7 @@ npxinitstate(void *arg __unused)
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xsave_area_desc[i].size = cp[0];
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}
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}
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#endif
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fpu_save_area_zone = uma_zcreate("FPU_save_area",
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cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
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@ -897,9 +915,11 @@ npxsave(addr)
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{
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stop_emulating();
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#ifdef CPU_ENABLE_SSE
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if (use_xsaveopt)
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xsaveopt((char *)addr, xsave_mask);
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else
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#endif
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fpusave(addr);
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start_emulating();
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PCPU_SET(fpcurthread, NULL);
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@ -972,9 +992,12 @@ int
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npxgetregs(struct thread *td)
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{
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struct pcb *pcb;
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#ifdef CPU_ENABLE_SSE
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uint64_t *xstate_bv, bit;
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char *sa;
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int max_ext_n, i, owned;
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int max_ext_n, i;
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#endif
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int owned;
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if (!hw_float)
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return (_MC_FPOWNED_NONE);
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@ -1004,6 +1027,7 @@ npxgetregs(struct thread *td)
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owned = _MC_FPOWNED_PCB;
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}
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critical_exit();
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#ifdef CPU_ENABLE_SSE
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if (use_xsave) {
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/*
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* Handle partially saved state.
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@ -1026,6 +1050,7 @@ npxgetregs(struct thread *td)
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*xstate_bv |= bit;
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}
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}
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#endif
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return (owned);
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}
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@ -1040,6 +1065,7 @@ npxuserinited(struct thread *td)
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pcb->pcb_flags |= PCB_NPXUSERINITDONE;
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}
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#ifdef CPU_ENABLE_SSE
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int
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npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
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{
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@ -1077,13 +1103,16 @@ npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
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return (0);
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}
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#endif
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int
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npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
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size_t xfpustate_size)
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{
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struct pcb *pcb;
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#ifdef CPU_ENABLE_SSE
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int error;
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#endif
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if (!hw_float)
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return (ENXIO);
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@ -1091,12 +1120,12 @@ npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
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pcb = td->td_pcb;
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critical_enter();
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if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
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#ifdef CPU_ENABLE_SSE
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error = npxsetxstate(td, xfpustate, xfpustate_size);
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if (error != 0) {
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critical_exit();
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return (error);
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}
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#ifdef CPU_ENABLE_SSE
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if (!cpu_fxsr)
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#endif
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fnclex(); /* As in npxdrop(). */
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@ -1106,9 +1135,11 @@ npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
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pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
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} else {
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critical_exit();
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#ifdef CPU_ENABLE_SSE
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error = npxsetxstate(td, xfpustate, xfpustate_size);
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if (error != 0)
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return (error);
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#endif
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bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
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npxuserinited(td);
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}
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