From 2cb1b07d692ea2df25e5f96a8f079f14c73230a2 Mon Sep 17 00:00:00 2001 From: ian Date: Sat, 22 Nov 2014 03:03:11 +0000 Subject: [PATCH] When doing a PREREAD sync of an mbuf-type dma buffer, do a writeback of the first cacheline if the buffer start address is not on a cacheline boundary. Normally a buffer which is not cacheline-aligned is bounced, but a special rule applies for mbufs, which are always misaligned due to the header. We know the cpu will not write to the header while dma is in progress (so we've been told anyway), but it may have written to the header shortly before starting a read, so we need to flush that write out to memory before invalidating the whole buffer. In collaboration with Mical Meloun and Svata Kraus. --- sys/arm/arm/busdma_machdep-v6.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/sys/arm/arm/busdma_machdep-v6.c b/sys/arm/arm/busdma_machdep-v6.c index 05bc5863cdd1..d7fcffa31d5e 100644 --- a/sys/arm/arm/busdma_machdep-v6.c +++ b/sys/arm/arm/busdma_machdep-v6.c @@ -1456,7 +1456,24 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) break; case BUS_DMASYNC_PREREAD: + /* + * An mbuf may start in the middle of a cacheline. There + * will be no cpu writes to the beginning of that line + * (which contains the mbuf header) while dma is in + * progress. Handle that case by doing a writeback of + * just the first cacheline before invalidating the + * overall buffer. Any mbuf in a chain may have this + * misalignment. Buffers which are not mbufs bounce if + * they are not aligned to a cacheline. + */ while (sl != end) { + if (sl->vaddr & arm_dcache_align_mask) { + KASSERT(map->flags & DMAMAP_MBUF, + ("unaligned buffer is not an mbuf")); + cpu_dcache_wb_range(sl->vaddr, 1); + l2cache_wb_range(sl->vaddr, + sl->busaddr, 1); + } cpu_dcache_inv_range(sl->vaddr, sl->datacount); l2cache_inv_range(sl->vaddr, sl->busaddr, sl->datacount);