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- Fix incorrect values in the computation of CCK and OFDM transmit power

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for the rtl8188eu chipset
- Rename struct r92c_rom member names: s/channel_plan/reserved5/,
  s/xtal_calib/channel_plan to be compliant with definitions of the efuse
  in vendor hal_pg.h
This commit is contained in:
Kevin Lo 2017-06-17 14:39:25 +00:00
parent c40a5f8a40
commit 2cd325579c
4 changed files with 11 additions and 68 deletions
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28
sys/dev/rtwn/rtl8188e/r88e_chan.c
View File

@ -89,8 +89,7 @@ r88e_get_txpower(struct rtwn_softc *sc, int chain,
{
struct r92c_softc *rs = sc->sc_priv;
const struct rtwn_r88e_txpwr *rt = rs->rs_txpwr;
const struct rtwn_r88e_txagc *base = rs->rs_txagc;
uint16_t cckpow, ofdmpow, bw20pow, htpow;
uint8_t cckpow, ofdmpow, bw20pow, htpow = 0;
int max_mcs, ridx, group;
/* Determine channel group. */
@ -106,35 +105,24 @@ r88e_get_txpower(struct rtwn_softc *sc, int chain,
KASSERT(max_mcs <= RTWN_RIDX_COUNT, ("increase ridx limit\n"));
memset(power, 0, max_mcs * sizeof(power[0]));
if (rs->regulatory == 0) {
for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
power[ridx] = base->pwr[0][ridx];
}
for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++) {
if (rs->regulatory == 3)
power[ridx] = base->pwr[0][ridx];
else if (rs->regulatory == 1) {
if (!IEEE80211_IS_CHAN_HT40(c))
power[ridx] = base->pwr[group][ridx];
} else if (rs->regulatory != 2)
power[ridx] = base->pwr[0][ridx];
}
/* Compute per-CCK rate Tx power. */
cckpow = rt->cck_tx_pwr[group];
for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
power[ridx] += cckpow;
for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) {
power[ridx] = (ridx == RTWN_RIDX_CCK2) ? cckpow - 9 : cckpow;
}
htpow = rt->ht40_tx_pwr[group];
if (group < 5)
htpow = rt->ht40_tx_pwr[group];
/* Compute per-OFDM rate Tx power. */
ofdmpow = htpow + rt->ofdm_tx_pwr_diff;
for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
power[ridx] += ofdmpow;
power[ridx] = ofdmpow;
bw20pow = htpow + rt->bw20_tx_pwr_diff;
for (ridx = RTWN_RIDX_MCS(0); ridx <= max_mcs; ridx++)
power[ridx] += bw20pow;
power[ridx] = bw20pow;
/* Apply max limit. */
for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {

43
sys/dev/rtwn/rtl8188e/r88e_priv.h
View File

@ -227,47 +227,4 @@ static const struct rtwn_rf_prog rtl8188eu_rf[] = {
{ 0, NULL, NULL, { 0 }, NULL }
};
struct rtwn_r88e_txagc {
uint8_t pwr[R88E_GROUP_2G][20]; /* RTWN_RIDX_MCS(7) + 1 */
};
/*
* Per RF chain/group/rate Tx gain values.
*/
static const struct rtwn_r88e_txagc r88e_txagc[] = {
{ { /* Chain 0. */
{ /* Group 0. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
},
{ /* Group 1. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
},
{ /* Group 2. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
},
{ /* Group 3. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
},
{ /* Group 4. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
},
{ /* Group 5. */
0x00, 0x00, 0x00, 0x00, /* CCK1~11. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */
}
} }
};
#endif /* R88E_PRIV_H */

2
sys/dev/rtwn/rtl8188e/usb/r88eu_attach.c
View File

@ -85,7 +85,7 @@ r88eu_attach_private(struct rtwn_softc *sc)
rs = malloc(sizeof(struct r92c_softc), M_RTWN_PRIV, M_WAITOK | M_ZERO);
rs->rs_txpwr = &r88e_txpwr;
rs->rs_txagc = &r88e_txagc;
rs->rs_txagc = NULL;
rs->rs_set_bw20 = r88e_set_bw20;
rs->rs_get_txpower = r88e_get_txpower;

6
sys/dev/rtwn/rtl8192c/r92c_rom_image.h
View File

@ -48,7 +48,7 @@ struct r92c_rom {
uint8_t ofdm_tx_pwr_diff[R92C_GROUP_2G];
uint8_t ht40_max_pwr[R92C_GROUP_2G];
uint8_t ht20_max_pwr[R92C_GROUP_2G];
uint8_t xtal_calib;
uint8_t channel_plan;
uint8_t tssi[R92C_MAX_CHAINS];
uint8_t thermal_meter;
#define R92C_ROM_THERMAL_METER_M 0x1f
@ -58,9 +58,7 @@ struct r92c_rom {
uint8_t rf_opt2;
uint8_t rf_opt3;
uint8_t rf_opt4;
uint8_t channel_plan;
#define R92C_CHANNEL_PLAN_BY_HW 0x80
uint8_t reserved5;
uint8_t version;
uint8_t customer_id;
} __packed;