arm64: rk3399: Add clock and gate for usb3 clocks
MFC after: 1 month
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manu
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5b55c17150
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2ce78127ee
@ -54,9 +54,18 @@ __FBSDID("$FreeBSD$");
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#define SCLK_USB2PHY0_REF 123
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#define SCLK_USB2PHY1_REF 124
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#define SCLK_USB3OTG0_REF 129
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#define SCLK_USB3OTG1_REF 130
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#define SCLK_USB3OTG0_SUSPEND 131
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#define SCLK_USB3OTG1_SUSPEND 132
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#define ACLK_EMMC_CORE 241
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#define ACLK_EMMC_NOC 242
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#define ACLK_EMMC_GRF 243
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#define ACLK_USB3_NOC 245
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#define ACLK_USB3OTG0 246
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#define ACLK_USB3OTG1 247
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#define ACLK_USB3_RKSOC_AXI_PERF 248
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#define ACLK_USB3_GRF 249
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#define PCLK_GPIO2 336
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#define PCLK_GPIO3 337
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#define PCLK_GPIO4 338
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@ -103,6 +112,12 @@ static struct rk_cru_gate rk3399_gates[] = {
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CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1)
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CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0)
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/* CRU_CLKGATE_CON12 */
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CRU_GATE(SCLK_USB3OTG0_REF, "sclk_usb3otg0_ref", "xin24m", 0x330, 1)
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CRU_GATE(SCLK_USB3OTG1_REF, "sclk_usb3otg1_ref", "xin24m", 0x330, 2)
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CRU_GATE(SCLK_USB3OTG0_SUSPEND, "sclk_usb3otg0_suspend", "xin24m", 0x330, 3)
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CRU_GATE(SCLK_USB3OTG1_SUSPEND, "sclk_usb3otg1_suspend", "xin24m", 0x330, 4)
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/* CRU_CLKGATE_CON20 */
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CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5)
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CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6)
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@ -117,6 +132,13 @@ static struct rk_cru_gate rk3399_gates[] = {
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CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9)
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CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10)
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/* CRU_CLKGATE_CON30 */
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CRU_GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 0x378, 0)
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CRU_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0x378, 1)
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CRU_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0x378, 2)
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CRU_GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0x378, 3)
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CRU_GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0x378, 4)
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/* CRU_CLKGATE_CON31 */
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CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3)
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CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4)
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@ -1066,6 +1088,32 @@ static struct rk_clk_composite_def pclk_perilp1 = {
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/* USB3 clock */
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#define ACLK_USB3 244
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static const char *aclk_usb3_parents[] = {"cpll", "gpll", "npll", "npll"};
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static struct rk_clk_composite_def aclk_usb3 = {
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.clkdef = {
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.id = ACLK_USB3,
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.name = "aclk_usb3",
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.parent_names = aclk_usb3_parents,
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.parent_cnt = nitems(aclk_usb3_parents),
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},
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/* CRU_CLKSET_CON39 */
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.muxdiv_offset = 0x19C,
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.mux_shift = 6,
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.mux_width = 2,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON12 */
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.gate_offset = 0x330,
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.gate_shift = 0,
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.flags = RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/*
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* i2c
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*/
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@ -1210,6 +1258,114 @@ static struct rk_clk_composite_def i2c7 = {
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/* USB3 */
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#define SCLK_UPHY0_TCPDPHY_REF 125
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#define SCLK_UPHY0_TCPDCORE 126
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/* Missing xin32k exported by rk808 */
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static const char *uphy0_tcpdphy_ref_parents[] = {"xin24m"};
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static struct rk_clk_composite_def uphy0_tcpdphy_ref = {
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.clkdef = {
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.id = SCLK_UPHY0_TCPDPHY_REF,
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.name = "uphy0_tcpdphy_ref",
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.parent_names = uphy0_tcpdphy_ref_parents,
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.parent_cnt = nitems(uphy0_tcpdphy_ref_parents),
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},
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/* CRU_CLKSET_CON64 */
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.muxdiv_offset = 0x0200,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 8,
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.div_width = 5,
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/* CRU_CLKGATE_CON13 */
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.gate_offset = 0x0334,
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.gate_shift = 4,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/* Missing xin32k exported by rk808 */
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static const char *uphy0_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"};
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static struct rk_clk_composite_def uphy0_tcpdcore = {
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.clkdef = {
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.id = SCLK_UPHY0_TCPDCORE,
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.name = "uphy0_tcpdcore",
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.parent_names = uphy0_tcpdcore_parents,
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.parent_cnt = nitems(uphy0_tcpdcore_parents),
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},
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/* CRU_CLKSET_CON64 */
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.muxdiv_offset = 0x0200,
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.mux_shift = 6,
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.mux_width = 2,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON13 */
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.gate_offset = 0x0334,
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.gate_shift = 5,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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#define SCLK_UPHY1_TCPDPHY_REF 127
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#define SCLK_UPHY1_TCPDCORE 128
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/* Missing xin32k exported by rk808 */
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static const char *uphy1_tcpdphy_ref_parents[] = {"xin24m"};
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static struct rk_clk_composite_def uphy1_tcpdphy_ref = {
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.clkdef = {
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.id = SCLK_UPHY1_TCPDPHY_REF,
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.name = "uphy1_tcpdphy_ref",
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.parent_names = uphy1_tcpdphy_ref_parents,
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.parent_cnt = nitems(uphy1_tcpdphy_ref_parents),
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},
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/* CRU_CLKSET_CON65 */
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.muxdiv_offset = 0x0204,
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.mux_shift = 15,
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.mux_width = 1,
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.div_shift = 8,
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.div_width = 5,
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/* CRU_CLKGATE_CON13 */
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.gate_offset = 0x0334,
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.gate_shift = 6,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/* Missing xin32k exported by rk808 */
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static const char *uphy1_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"};
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static struct rk_clk_composite_def uphy1_tcpdcore = {
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.clkdef = {
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.id = SCLK_UPHY1_TCPDCORE,
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.name = "uphy1_tcpdcore",
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.parent_names = uphy1_tcpdcore_parents,
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.parent_cnt = nitems(uphy1_tcpdcore_parents),
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},
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/* CRU_CLKSET_CON65 */
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.muxdiv_offset = 0x0204,
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.mux_shift = 6,
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.mux_width = 2,
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.div_shift = 0,
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.div_width = 5,
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/* CRU_CLKGATE_CON13 */
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.gate_offset = 0x0334,
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.gate_shift = 7,
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.flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE,
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};
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/*
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* ARM CPU clocks (LITTLE and big)
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*/
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@ -1591,6 +1747,10 @@ static struct rk_clk rk3399_clks[] = {
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &pclk_perilp1,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &aclk_usb3,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &i2c1,
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@ -1615,6 +1775,22 @@ static struct rk_clk rk3399_clks[] = {
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &i2c7,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &uphy0_tcpdphy_ref,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &uphy0_tcpdcore,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &uphy1_tcpdphy_ref,
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},
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{
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.type = RK_CLK_COMPOSITE,
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.clk.composite = &uphy1_tcpdcore,
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},
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{
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.type = RK_CLK_ARMCLK,
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