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cxgbe(4): Include firmware for T6 cards in the driver. Update all

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firmwares to 1.16.12.0.

Obtained from:	Chelsio Communications
MFC after:	3 days
Sponsored by:	Chelsio Communications
This commit is contained in:
np 2016-11-30 00:26:35 +00:00
parent cf9b3d8c3e
commit 2d04362fed
18 changed files with 30954 additions and 20079 deletions
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28
sys/conf/files
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@ -1381,7 +1381,7 @@ t4fw.fwo optional cxgbe \
no-implicit-rule \
clean "t4fw.fwo"
t4fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t4fw-1.15.37.0.bin.uu" \
dependency "$S/dev/cxgbe/firmware/t4fw-1.16.12.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t4fw.fw"
@ -1405,10 +1405,34 @@ t5fw.fwo optional cxgbe \
no-implicit-rule \
clean "t5fw.fwo"
t5fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t5fw-1.15.37.0.bin.uu" \
dependency "$S/dev/cxgbe/firmware/t5fw-1.16.12.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t5fw.fw"
t6fw_cfg.c optional cxgbe \
compile-with "${AWK} -f $S/tools/fw_stub.awk t6fw_cfg.fw:t6fw_cfg t6fw.fw:t6fw -mt6fw_cfg -c${.TARGET}" \
no-implicit-rule before-depend local \
clean "t6fw_cfg.c"
t6fw_cfg.fwo optional cxgbe \
dependency "t6fw_cfg.fw" \
compile-with "${NORMAL_FWO}" \
no-implicit-rule \
clean "t6fw_cfg.fwo"
t6fw_cfg.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t6fw_cfg.txt" \
compile-with "${CP} ${.ALLSRC} ${.TARGET}" \
no-obj no-implicit-rule \
clean "t6fw_cfg.fw"
t6fw.fwo optional cxgbe \
dependency "t6fw.fw" \
compile-with "${NORMAL_FWO}" \
no-implicit-rule \
clean "t6fw.fwo"
t6fw.fw optional cxgbe \
dependency "$S/dev/cxgbe/firmware/t6fw-1.16.12.0.bin.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "t6fw.fw"
dev/cy/cy.c optional cy
dev/cy/cy_isa.c optional cy isa
dev/cy/cy_pci.c optional cy pci

3
sys/dev/cxgbe/common/common.h
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@ -578,7 +578,8 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
unsigned int flags);
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
unsigned int flags, unsigned int defq);
unsigned int flags, unsigned int defq, unsigned int skeyidx,
unsigned int skey);
int t4_read_rss(struct adapter *adapter, u16 *entries);
void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
unsigned int start_index, unsigned int rw);

19
sys/dev/cxgbe/common/t4_hw.c
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@ -4754,7 +4754,7 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
c.u.manual.mode_pkd =
cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
c.u.basicvirtual.mode_pkd =
c.u.basicvirtual.mode_keymode =
cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
} else
@ -4769,11 +4769,14 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
* @viid: the VI id
* @flags: RSS flags
* @defq: id of the default RSS queue for the VI.
* @skeyidx: RSS secret key table index for non-global mode
* @skey: RSS vf_scramble key for VI.
*
* Configures VI-specific RSS properties.
*/
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
unsigned int flags, unsigned int defq)
unsigned int flags, unsigned int defq, unsigned int skeyidx,
unsigned int skey)
{
struct fw_rss_vi_config_cmd c;
@ -4784,6 +4787,10 @@ int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
c.retval_len16 = cpu_to_be32(FW_LEN16(c));
c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
}
@ -4902,11 +4909,11 @@ void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
if (idx >= 0 && idx < rss_key_addr_cnt) {
if (rss_key_addr_cnt > 16)
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
V_KEYWRADDRX(idx >> 4) |
vrt | V_KEYWRADDRX(idx >> 4) |
V_T6_VFWRADDR(idx) | F_KEYWREN);
else
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
V_KEYWRADDR(idx) | F_KEYWREN);
vrt| V_KEYWRADDR(idx) | F_KEYWREN);
}
}
@ -5794,8 +5801,10 @@ const char *t4_get_port_type_description(enum fw_port_type port_type)
"KR4_100G",
"CR4_QSFP",
"CR_QSFP",
"CR2_QSFP",
"CR_SFP28",
"SFP28",
"KR_SFP28",
"CR2_QSFP",
};
if (port_type < ARRAY_SIZE(port_type_description))

9522
sys/dev/cxgbe/firmware/t4fw-1.15.37.0.bin.uu
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9594
sys/dev/cxgbe/firmware/t4fw-1.16.12.0.bin.uu Normal file
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146
sys/dev/cxgbe/firmware/t4fw_interface.h
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@ -114,6 +114,7 @@ enum fw_wr_opcodes {
FW_RI_RECV_WR = 0x17,
FW_RI_BIND_MW_WR = 0x18,
FW_RI_FR_NSMR_WR = 0x19,
FW_RI_FR_NSMR_TPTE_WR = 0x20,
FW_RI_INV_LSTAG_WR = 0x1a,
FW_RI_SEND_IMMEDIATE_WR = 0x15,
FW_RI_ATOMIC_WR = 0x16,
@ -915,7 +916,8 @@ enum fw_flowc_mnem {
FW_FLOWC_MNEM_DCBPRIO = 12,
FW_FLOWC_MNEM_SND_SCALE = 13,
FW_FLOWC_MNEM_RCV_SCALE = 14,
FW_FLOWC_MNEM_MAX = 15,
FW_FLOWC_MNEM_ULP_MODE = 15,
FW_FLOWC_MNEM_MAX = 16,
};
struct fw_flowc_mnemval {
@ -1338,7 +1340,7 @@ struct fw_ri_cqe {
struct fw_ri_scqe {
__be32 qpid_n_stat_rxtx_type;
__be32 plen;
__be32 reserved;
__be32 stag;
__be32 wrid;
} scqe;
struct fw_ri_rcqe {
@ -1806,6 +1808,18 @@ struct fw_ri_fr_nsmr_wr {
#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
struct fw_ri_fr_nsmr_tpte_wr {
__u8 opcode;
__u8 flags;
__u16 wrid;
__u8 r1[3];
__u8 len16;
__be32 r2;
__be32 stag;
struct fw_ri_tpte tpte;
__be64 pbl[2];
};
struct fw_ri_inv_lstag_wr {
__u8 opcode;
__u8 flags;
@ -3394,7 +3408,10 @@ struct fw_tlstx_data_wr {
__be32 ddraddr;
__be32 ctxloc_to_exp;
__be16 mfs;
__u8 r6[6];
__be16 adjustedplen_pkd;
__be16 expinplenmax_pkd;
__u8 pdusinplenmax_pkd;
__u8 r9;
};
#define S_FW_TLSTX_DATA_WR_COMPL 21
@ -3483,6 +3500,30 @@ struct fw_tlstx_data_wr {
#define G_FW_TLSTX_DATA_WR_EXP(x) \
(((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
(((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
(((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
(((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
struct fw_tls_keyctx_tx_wr {
__be32 op_to_compl;
__be32 flowid_len16;
@ -3897,6 +3938,14 @@ struct fw_crypto_lookaside_wr {
#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
@ -3994,6 +4043,7 @@ enum fw_cmd_opcodes {
FW_FCOE_STATS_CMD = 0x37,
FW_FCOE_FCF_CMD = 0x38,
FW_DCB_IEEE_CMD = 0x3a,
FW_DIAG_CMD = 0x3d,
FW_PTP_CMD = 0x3e,
FW_LASTC2E_CMD = 0x40,
FW_ERROR_CMD = 0x80,
@ -4632,6 +4682,7 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
};
/*
@ -4718,6 +4769,7 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
};
/*
@ -7200,12 +7252,13 @@ enum fw_port_type {
FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G */
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G, Backplane */
FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G */
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G */
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G */
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
FW_PORT_TYPE_CR_SFP28 = 19, /* No, 1, 25G - Old vpd */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G - New vpd */
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G using Backplane */
FW_PORT_TYPE_CR2_QSFP = 22, /* No, 2, 50G */
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
};
@ -7906,7 +7959,7 @@ struct fw_rss_glb_config_cmd {
__be64 r5;
} manual;
struct fw_rss_glb_config_basicvirtual {
__be32 mode_pkd;
__be32 mode_keymode;
__be32 synmapen_to_hashtoeplitz;
__be64 r8;
__be64 r9;
@ -7924,6 +7977,19 @@ struct fw_rss_glb_config_cmd {
#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
@ -8023,7 +8089,8 @@ struct fw_rss_vi_config_cmd {
struct fw_rss_vi_config_basicvirtual {
__be32 r6;
__be32 defaultq_to_udpen;
__be64 r9;
__be32 secretkeyidx_pkd;
__be32 secretkeyxor;
__be64 r10;
} basicvirtual;
} u;
@ -8090,6 +8157,14 @@ struct fw_rss_vi_config_cmd {
(((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
(((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
enum fw_sched_sc {
FW_SCHED_SC_CONFIG = 0,
FW_SCHED_SC_PARAMS = 1,
@ -8994,6 +9069,43 @@ struct fw_debug_cmd {
#define G_FW_DEBUG_CMD_TYPE(x) \
(((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
enum fw_diag_cmd_type {
FW_DIAG_CMD_TYPE_OFLDIAG = 0,
};
enum fw_diag_cmd_ofldiag_op {
FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
FW_DIAG_CMD_OFLDIAG_TEST_START,
FW_DIAG_CMD_OFLDIAG_TEST_STOP,
FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
};
enum fw_diag_cmd_ofldiag_status {
FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
};
struct fw_diag_cmd {
__be32 op_type;
__be32 len16_pkd;
union fw_diag_test {
struct fw_diag_test_ofldiag {
__u8 test_op;
__u8 r3;
__be16 test_status;
__be32 duration;
} ofldiag;
} u;
};
#define S_FW_DIAG_CMD_TYPE 0
#define M_FW_DIAG_CMD_TYPE 0xff
#define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
#define G_FW_DIAG_CMD_TYPE(x) \
(((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
/******************************************************************************
* P C I E F W R E G I S T E R
**************************************/
@ -9207,18 +9319,18 @@ enum fw_hdr_chip {
enum {
T4FW_VERSION_MAJOR = 0x01,
T4FW_VERSION_MINOR = 0x05,
T4FW_VERSION_MICRO = 0x25,
T4FW_VERSION_MINOR = 0x10,
T4FW_VERSION_MICRO = 0x0c,
T4FW_VERSION_BUILD = 0x00,
T5FW_VERSION_MAJOR = 0x01,
T5FW_VERSION_MINOR = 0x05,
T5FW_VERSION_MICRO = 0x25,
T5FW_VERSION_MINOR = 0x10,
T5FW_VERSION_MICRO = 0x0c,
T5FW_VERSION_BUILD = 0x00,
T6FW_VERSION_MAJOR = 0x00,
T6FW_VERSION_MINOR = 0x00,
T6FW_VERSION_MICRO = 0x00,
T6FW_VERSION_MAJOR = 0x01,
T6FW_VERSION_MINOR = 0x10,
T6FW_VERSION_MICRO = 0x0c,
T6FW_VERSION_BUILD = 0x00,
};

10501
sys/dev/cxgbe/firmware/t5fw-1.15.37.0.bin.uu
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10663
sys/dev/cxgbe/firmware/t5fw-1.16.12.0.bin.uu Normal file
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3
sys/dev/cxgbe/firmware/t5fw_cfg_uwire.txt
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@ -467,7 +467,6 @@
fcoe_nfcf = 16
fcoe_nvnp = 32
fcoe_nssn = 1024
fcoe_nfcb = 256
# The following function, 1023, is not an actual PCIE function but is used to
@ -602,7 +601,7 @@
[fini]
version = 0x1425001c
checksum = 0xa4a80156
checksum = 0xf9115d76
# Total resources used by above allocations:
# Virtual Interfaces: 104

8839
sys/dev/cxgbe/firmware/t6fw-1.16.12.0.bin.uu Normal file
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583
sys/dev/cxgbe/firmware/t6fw_cfg.txt Normal file
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@ -0,0 +1,583 @@
# Chelsio T6 Factory Default configuration file.
#
# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
# TO ADAPTERS.
# This file provides the default, power-on configuration for 2-port T6-based
# adapters shipped from the factory. These defaults are designed to address
# the needs of the vast majority of Terminator customers. The basic idea is to
# have a default configuration which allows a customer to plug a Terminator
# adapter in and have it work regardless of OS, driver or application except in
# the most unusual and/or demanding customer applications.
#
# Many of the Terminator resources which are described by this configuration
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
# Some of the more important resources to allocate and their constaints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
# 4. MSI-X Vectors: 1088.
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
# address matching on Ingress Packets.
#
# Some of the important OS/Driver resource needs are:
# 6. Some OS Drivers will manage all resources through a single Physical
# Function (currently PF4 but it could be any Physical Function).
# 7. Some OS Drivers will manage different ports and functions (NIC,
# storage, etc.) on different Physical Functions. For example, NIC
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
#
# Some of the customer application needs which need to be accommodated:
# 8. Some customers will want to support large CPU count systems with
# good scaling. Thus, we'll need to accommodate a number of
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
# to be involved per port and per application function. For example,
# in the case where all ports and application functions will be
# managed via a single Unified PF and we want to accommodate scaling up
# to 8 CPUs, we would want:
#
# 2 ports *
# 3 application functions (NIC, FCoE, iSCSI) per port *
# 16 Ingress Queue/MSI-X Vectors per application function
#
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
# (Plus a few for Firmware Event Queues, etc.)
#
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
# and "PCI Device Passthrough" -- this is especially true for the NIC
# application functionality.
#
# Global configuration settings.
#
[global]
rss_glb_config_mode = basicvirtual
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
# PL_TIMEOUT register
pl_timeout_value = 200 # the timeout value in units of us
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
# Page Size and a 64B L1 Cache Line Size. It programs the
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
# If a Master PF Driver finds itself on a machine with different
# parameters, then the Master PF Driver is responsible for initializing
# these parameters to appropriate values.
#
# Notes:
# 1. The Free List Buffer Sizes below are raw and the firmware will
# round them up to the Ingress Padding Boundary.
# 2. The SGE Timer Values below are expressed below in microseconds.
# The firmware will convert these values to Core Clock Ticks when
# it processes the configuration parameters.
#
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
# enable TP_OUT_CONFIG.IPIDSPLITMODE
reg[0x7d04] = 0x00010000/0x00010000
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
#Tick granularities in kbps
tsch_ticks = 100000, 10000, 1000, 10
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
# filter control: compact, fcoemask
# server sram : srvrsram
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
# protocol, tos, vlan, vnic_id, port, fcoe
# valid filterModes are described the Terminator 5 Data Book
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
# filter tuples enforced in LE active region (equal to or subset of filterMode)
filterMask = protocol, fcoe
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP RX payload
tp_pmrx = 30
# TP RX payload page size
tp_pmrx_pagesize = 64K
# TP number of RX channels
tp_nrxch = 0 # 0 (auto) = 1
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP TX payload
tp_pmtx = 50
# TP TX payload page size
tp_pmtx_pagesize = 64K
# TP number of TX channels
tp_ntxch = 0 # 0 (auto) = equal number of ports
# TP OFLD MTUs
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
reg[0x7d04] = 0x00010008/0x00010008
# TP_GLOBAL_CONFIG
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
# TP_PC_CONFIG
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
# TP_PARA_REG0
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
# LE_DB_CONFIG
reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
# LE IPv4 compression disabled
# LE_DB_HASH_CONFIG
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
# ULP_TX_CONFIG
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
# Enable more error msg for ...
# TPT error.
# ULP_RX_MISC_FEATURE_ENABLE
#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
# Enable offset decrement after ...
# PI extraction and before DDP
# ulp insert pi source info in DIF
# iscsi_eff_offset_en
#Enable iscsi completion moderation feature
reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
# PI extraction and before DDP.
# ulp insert pi source info in
# DIF.
# Enable iscsi hdr cmd mode.
# iscsi force cmd mode.
# Enable iscsi cmp mode.
# MC configuration
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
# Some "definitions" to make the rest of this a bit more readable. We support
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
# per function per port ...
#
# NMSIX = 1088 # available MSI-X Vectors
# NVI = 256 # available Virtual Interfaces
# NMPSTCAM = 336 # MPS TCAM entries
#
# NPORTS = 2 # ports
# NCPUS = 16 # CPUs we want to support scalably
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
# PF" which many OS Drivers will use to manage most or all functions.
#
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
# will be specified as the "Ingress Queue Asynchronous Destination Index."
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
# than or equal to the number of Ingress Queues ...
#
# NVI_NIC = 4 # NIC access to NPORTS
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
#
# NVI_OFLD = 0 # Offload uses NIC function to access ports
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
#
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
#
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
# NETHCTRL_WD = 64 # Wire Direct TX Queues
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
#
# NVI_ISCSI = 4 # ISCSI access to NPORTS
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
#
# NVI_FCOE = 4 # FCOE access to NPORTS
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
# Two extra Ingress Queues per function for Firmware Events and Forwarded
# Interrupts, and two extra interrupts per function for Firmware Events (or a
# Forwarded Interrupt Queue) and General Interrupts per function.
#
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
# # Forwarded Interrupts
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
# # General Interrupts
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
#
# NVI_HYPERV = 16 # VMs we want to support
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
# NEQ_HYPERV = 32 # VIQs Free Lists
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
#
# NVI_UNIFIED = 28
# NFLIQ_UNIFIED = 106
# NETHCTRL_UNIFIED = 32
# NEQ_UNIFIED = 124
# NMPSTCAM_UNIFIED = 40
#
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
# that up to 128 to make sure the Unified PF doesn't run out of resources.
#
# NMSIX_UNIFIED = 128
#
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
# which is 34 but they're probably safe with 32.
#
# NMSIX_STORAGE = 32
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
# associated with it. Thus, the MSI-X Vector allocations we give to the
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
# provision many more Virtual Functions than we can if the UnifiedPF were
# one of PF0-3.
#
# All of the below PCI-E parameters are actually stored in various *_init.txt
# files. We include them below essentially as comments.
#
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
# ports 0-3.
#
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
#
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
# storage applications across all four possible ports.
#
# Additionally, since the UnifiedPF isn't one of the per-port Physical
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
# different PCI Device IDs which will allow Unified and Per-Port Drivers
# to directly select the type of Physical Function to which they wish to be
# attached.
#
# Note that the actual values used for the PCI-E Intelectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
# PF0_INT = 8 # NCPUS
# PF1_INT = 8 # NCPUS
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
#
# PF4_INT = 128 # NMSIX_UNIFIED
# PF5_INT = 32 # NMSIX_STORAGE
# PF6_INT = 32 # NMSIX_STORAGE
# PF7_INT = 0 # Nothing Assigned
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
#
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
#
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
#
# NVF = 16
# For those OSes which manage different ports on different PFs, we need
# only enough resources to support a single port's NIC application functions
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
# managed on the "storage PFs" (see below).
#
[function "0"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x1 # access to only one port
[function "1"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x2 # access to only one port
[function "2"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x4 # access to only one port
[function "3"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x8 # access to only one port
# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here. For Egress
# Queues we need to account for both TX Queues as well as Free List Queues
# (because the host is responsible for producing Free List Buffers for the
# hardware to consume).
#
[function "4"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
neq = 256 # NEQ_UNIFIED + NEQ_WD
nqpcq = 12288
nexactf = 40 # NMPSTCAM_UNIFIED
cmask = all # access to all channels
pmask = all # access to all four ports ...
nethofld = 1024 # number of user mode ethernet flow contexts
ncrypto_lookaside = 16 # Number of lookaside flow contexts
nclip = 320 # number of clip region entries
nfilter = 496 # number of filter region entries
nserver = 496 # number of server region entries
nhash = 12288 # number of hash region entries
nhpfilter = 0 # number of high priority filter region entries
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
tp_l2t = 3072
tp_ddp = 2
tp_ddp_iscsi = 2
tp_tls_key = 3
tp_stag = 2
tp_pbl = 5
tp_rq = 7
tp_srq = 128
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
# "Queue Sets" each.
#
[function "5"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NPORTS
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
nethctrl = 32 # NPORTS*NCPUS
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
cmask = all # access to all channels
pmask = all # access to all four ports ...
nserver = 16
nhash = 2048
tp_l2t = 1020
nclip = 64
protocol = iscsi_initiator_fofld
tp_ddp_iscsi = 2
iscsi_ntask = 2048
iscsi_nsess = 2048
iscsi_nconn_per_session = 1
iscsi_ninitiator_instance = 64
[function "6"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NPORTS
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
nethctrl = 32 # NPORTS*NCPUS
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
# which is OK since < MIN(SUM PF0..3, PF4)
# and we never load PF0..3 and PF4 concurrently
cmask = all # access to all channels
pmask = all # access to all four ports ...
nhash = 2048
tp_l2t = 4
protocol = fcoe_initiator
tp_ddp = 2
fcoe_nfcf = 16
fcoe_nvnp = 32
fcoe_nssn = 1024
# The following function, 1023, is not an actual PCIE function but is used to
# configure and reserve firmware internal resources that come from the global
# resource pool.
#
[function "1023"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NVI_UNIFIED
cmask = all # access to all channels
pmask = all # access to all four ports ...
nexactf = 8 # NPORTS + DCBX +
nfilter = 16 # number of filter region entries
# For Virtual functions, we only allow NIC functionality and we only allow
# access to one port (1 << PF). Note that because of limitations in the
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
# and GTS registers, the number of Ingress and Egress Queues must be a power
# of 2.
#
[function "0/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
[function "1/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
[function "2/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
[function "3/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
# folling params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
# lpbk_mem: %-age of port/bg mem to use for loopback
# hwm: high watermark; bytes available when starting to send pause
# frames (in units of 0.1 MTU)
# lwm: low watermark; bytes remaining when sending 'unpause' frame
# (in inuits of 0.1 MTU)
# dwm: minimum delta between high and low watermark (in units of 100
# Bytes)
#
[port "0"]
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
#bg_mem = 25
#lpbk_mem = 25
hwm = 60
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
aec_retry_cnt = 4
[port "1"]
dcb = ppp, dcbx
#bg_mem = 25
#lpbk_mem = 25
hwm = 60
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
aec_retry_cnt = 4
[fini]
version = 0x01000023
checksum = 0x683208a2
# Total resources used by above allocations:
# Virtual Interfaces: 104
# Ingress Queues/w Free Lists and Interrupts: 526
# Egress Queues: 702
# MPS TCAM Entries: 336
# MSI-X Vectors: 736
# Virtual Functions: 64
#
# $FreeBSD$
#

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sys/dev/cxgbe/firmware/t6fw_cfg_fpga.txt Normal file
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# Chelsio T6 Factory Default configuration file.
#
# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
# TO ADAPTERS.
# This file provides the default, power-on configuration for 2-port T6-based
# adapters shipped from the factory. These defaults are designed to address
# the needs of the vast majority of Terminator customers. The basic idea is to
# have a default configuration which allows a customer to plug a Terminator
# adapter in and have it work regardless of OS, driver or application except in
# the most unusual and/or demanding customer applications.
#
# Many of the Terminator resources which are described by this configuration
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
# Some of the more important resources to allocate and their constaints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
# 4. MSI-X Vectors: 1088.
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
# address matching on Ingress Packets.
#
# Some of the important OS/Driver resource needs are:
# 6. Some OS Drivers will manage all resources through a single Physical
# Function (currently PF4 but it could be any Physical Function).
# 7. Some OS Drivers will manage different ports and functions (NIC,
# storage, etc.) on different Physical Functions. For example, NIC
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
#
# Some of the customer application needs which need to be accommodated:
# 8. Some customers will want to support large CPU count systems with
# good scaling. Thus, we'll need to accommodate a number of
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
# to be involved per port and per application function. For example,
# in the case where all ports and application functions will be
# managed via a single Unified PF and we want to accommodate scaling up
# to 8 CPUs, we would want:
#
# 2 ports *
# 3 application functions (NIC, FCoE, iSCSI) per port *
# 16 Ingress Queue/MSI-X Vectors per application function
#
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
# (Plus a few for Firmware Event Queues, etc.)
#
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
# and "PCI Device Passthrough" -- this is especially true for the NIC
# application functionality.
#
# Global configuration settings.
#
[global]
rss_glb_config_mode = basicvirtual
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
# PL_TIMEOUT register
pl_timeout_value = 1000 # the timeout value in units of us
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
# Page Size and a 64B L1 Cache Line Size. It programs the
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
# If a Master PF Driver finds itself on a machine with different
# parameters, then the Master PF Driver is responsible for initializing
# these parameters to appropriate values.
#
# Notes:
# 1. The Free List Buffer Sizes below are raw and the firmware will
# round them up to the Ingress Padding Boundary.
# 2. The SGE Timer Values below are expressed below in microseconds.
# The firmware will convert these values to Core Clock Ticks when
# it processes the configuration parameters.
#
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
#DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer
#SGE DBQ tick value. All timers are multiple of this value
# sge_dbq_timertick = 5 #in usecs
# sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16
# enable TP_OUT_CONFIG.IPIDSPLITMODE
reg[0x7d04] = 0x00010000/0x00010000
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
#Tick granularities in kbps
tsch_ticks = 1000, 100, 10, 1
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
# filter control: compact, fcoemask
# server sram : srvrsram
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
# protocol, tos, vlan, vnic_id, port, fcoe
# valid filterModes are described the Terminator 5 Data Book
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
# filter tuples enforced in LE active region (equal to or subset of filterMode)
filterMask = protocol, fcoe
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP RX payload
tp_pmrx = 30
# TP RX payload page size
tp_pmrx_pagesize = 64K
# TP number of RX channels
tp_nrxch = 0 # 0 (auto) = 1
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP TX payload
tp_pmtx = 50
# TP TX payload page size
tp_pmtx_pagesize = 64K
# TP number of TX channels
tp_ntxch = 0 # 0 (auto) = equal number of ports
# TP OFLD MTUs
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
reg[0x7d04] = 0x00010008/0x00010008
# TP_GLOBAL_CONFIG
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
# TP_PC_CONFIG
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
# TP_PARA_REG0
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
# LE_DB_CONFIG
reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable,
# LE IPv4 compression disabled
# LE_DB_HASH_CONFIG
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
# ULP_TX_CONFIG
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
# Enable more error msg for ...
# TPT error.
# ULP_RX_MISC_FEATURE_ENABLE
reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
# Enable offset decrement after ...
# PI extraction and before DDP
# ulp insert pi source info in DIF
# iscsi_eff_offset_en
#Enable iscsi completion moderation feature
#reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
# PI extraction and before DDP.
# ulp insert pi source info in
# DIF.
# Enable iscsi hdr cmd mode.
# iscsi force cmd mode.
# Enable iscsi cmp mode.
# Some "definitions" to make the rest of this a bit more readable. We support
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
# per function per port ...
#
# NMSIX = 1088 # available MSI-X Vectors
# NVI = 256 # available Virtual Interfaces
# NMPSTCAM = 336 # MPS TCAM entries
#
# NPORTS = 2 # ports
# NCPUS = 16 # CPUs we want to support scalably
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
# PF" which many OS Drivers will use to manage most or all functions.
#
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
# will be specified as the "Ingress Queue Asynchronous Destination Index."
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
# than or equal to the number of Ingress Queues ...
#
# NVI_NIC = 4 # NIC access to NPORTS
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
#
# NVI_OFLD = 0 # Offload uses NIC function to access ports
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
#
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
#
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
# NETHCTRL_WD = 64 # Wire Direct TX Queues
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
#
# NVI_ISCSI = 4 # ISCSI access to NPORTS
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
#
# NVI_FCOE = 4 # FCOE access to NPORTS
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
# Two extra Ingress Queues per function for Firmware Events and Forwarded
# Interrupts, and two extra interrupts per function for Firmware Events (or a
# Forwarded Interrupt Queue) and General Interrupts per function.
#
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
# # Forwarded Interrupts
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
# # General Interrupts
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
#
# NVI_HYPERV = 16 # VMs we want to support
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
# NEQ_HYPERV = 32 # VIQs Free Lists
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
#
# NVI_UNIFIED = 28
# NFLIQ_UNIFIED = 106
# NETHCTRL_UNIFIED = 32
# NEQ_UNIFIED = 124
# NMPSTCAM_UNIFIED = 40
#
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
# that up to 128 to make sure the Unified PF doesn't run out of resources.
#
# NMSIX_UNIFIED = 128
#
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
# which is 34 but they're probably safe with 32.
#
# NMSIX_STORAGE = 32
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
# associated with it. Thus, the MSI-X Vector allocations we give to the
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
# provision many more Virtual Functions than we can if the UnifiedPF were
# one of PF0-1.
#
# All of the below PCI-E parameters are actually stored in various *_init.txt
# files. We include them below essentially as comments.
#
# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
# ports 0-1.
#
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
#
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
# storage applications across all four possible ports.
#
# Additionally, since the UnifiedPF isn't one of the per-port Physical
# Functions, we give the UnifiedPF and the PF0-1 Physical Functions
# different PCI Device IDs which will allow Unified and Per-Port Drivers
# to directly select the type of Physical Function to which they wish to be
# attached.
#
# Note that the actual values used for the PCI-E Intelectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
# PF0_INT = 8 # NCPUS
# PF1_INT = 8 # NCPUS
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
#
# PF4_INT = 128 # NMSIX_UNIFIED
# PF5_INT = 32 # NMSIX_STORAGE
# PF6_INT = 32 # NMSIX_STORAGE
# PF7_INT = 0 # Nothing Assigned
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
#
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
#
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
#
# NVF = 16
# For those OSes which manage different ports on different PFs, we need
# only enough resources to support a single port's NIC application functions
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
# managed on the "storage PFs" (see below).
#
# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here. For Egress
# Queues we need to account for both TX Queues as well as Free List Queues
# (because the host is responsible for producing Free List Buffers for the
# hardware to consume).
#
[function "0"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
nethctrl = 96 # NETHCTRL_UNIFIED + NETHCTRL_WD
neq = 252 # NEQ_UNIFIED + NEQ_WD
nexactf = 40 # NMPSTCAM_UNIFIED
nrawf = 2
cmask = all # access to all channels
pmask = all # access to all four ports ...
nethofld = 1024 # number of user mode ethernet flow contexts
ncrypto_lookaside = 32
nclip = 32 # number of clip region entries
nfilter = 48 # number of filter region entries
nserver = 48 # number of server region entries
nhash = 2048 # number of hash region entries
nhpfilter = 0 # number of high priority filter region entries
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
tp_l2t = 3072
tp_ddp = 2
tp_ddp_iscsi = 2
tp_tls_key = 3
tp_stag = 2
tp_pbl = 5
tp_rq = 7
tp_srq = 128
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
# "Queue Sets" each.
#
[function "1"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NPORTS
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
nethctrl = 32 # NPORTS*NCPUS
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
cmask = all # access to all channels
pmask = all # access to all four ports ...
nserver = 16
nhash = 2048
tp_l2t = 1020
protocol = iscsi_initiator_fofld
tp_ddp_iscsi = 2
iscsi_ntask = 2048
iscsi_nsess = 2048
iscsi_nconn_per_session = 1
iscsi_ninitiator_instance = 64
# The following function, 1023, is not an actual PCIE function but is used to
# configure and reserve firmware internal resources that come from the global
# resource pool.
#
[function "1023"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NVI_UNIFIED
cmask = all # access to all channels
pmask = all # access to all four ports ...
nexactf = 8 # NPORTS + DCBX +
nfilter = 16 # number of filter region entries
#nhpfilter = 0 # number of high priority filter region entries
# For Virtual functions, we only allow NIC functionality and we only allow
# access to one port (1 << PF). Note that because of limitations in the
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
# and GTS registers, the number of Ingress and Egress Queues must be a power
# of 2.
#
[function "0/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
[function "1/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
# folling params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
# lpbk_mem: %-age of port/bg mem to use for loopback
# hwm: high watermark; bytes available when starting to send pause
# frames (in units of 0.1 MTU)
# lwm: low watermark; bytes remaining when sending 'unpause' frame
# (in inuits of 0.1 MTU)
# dwm: minimum delta between high and low watermark (in units of 100
# Bytes)
#
[port "0"]
dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload
hwm = 30
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
[port "1"]
dcb = ppp, dcbx, b2b
hwm = 30
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
[fini]
version = 0x1425001d
checksum = 0x5001af51
# Total resources used by above allocations:
# Virtual Interfaces: 104
# Ingress Queues/w Free Lists and Interrupts: 526
# Egress Queues: 702
# MPS TCAM Entries: 336
# MSI-X Vectors: 736
# Virtual Functions: 64
#
# $FreeBSD$
#

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sys/dev/cxgbe/firmware/t6fw_cfg_uwire.txt Normal file
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# Chelsio T6 Factory Default configuration file.
#
# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved.
#
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
# TO ADAPTERS.
# This file provides the default, power-on configuration for 2-port T6-based
# adapters shipped from the factory. These defaults are designed to address
# the needs of the vast majority of Terminator customers. The basic idea is to
# have a default configuration which allows a customer to plug a Terminator
# adapter in and have it work regardless of OS, driver or application except in
# the most unusual and/or demanding customer applications.
#
# Many of the Terminator resources which are described by this configuration
# are finite. This requires balancing the configuration/operation needs of
# device drivers across OSes and a large number of customer application.
#
# Some of the more important resources to allocate and their constaints are:
# 1. Virtual Interfaces: 256.
# 2. Ingress Queues with Free Lists: 1024.
# 3. Egress Queues: 128K.
# 4. MSI-X Vectors: 1088.
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
# address matching on Ingress Packets.
#
# Some of the important OS/Driver resource needs are:
# 6. Some OS Drivers will manage all resources through a single Physical
# Function (currently PF4 but it could be any Physical Function).
# 7. Some OS Drivers will manage different ports and functions (NIC,
# storage, etc.) on different Physical Functions. For example, NIC
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
#
# Some of the customer application needs which need to be accommodated:
# 8. Some customers will want to support large CPU count systems with
# good scaling. Thus, we'll need to accommodate a number of
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
# to be involved per port and per application function. For example,
# in the case where all ports and application functions will be
# managed via a single Unified PF and we want to accommodate scaling up
# to 8 CPUs, we would want:
#
# 2 ports *
# 3 application functions (NIC, FCoE, iSCSI) per port *
# 16 Ingress Queue/MSI-X Vectors per application function
#
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
# (Plus a few for Firmware Event Queues, etc.)
#
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
# and "PCI Device Passthrough" -- this is especially true for the NIC
# application functionality.
#
# Global configuration settings.
#
[global]
rss_glb_config_mode = basicvirtual
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
# PL_TIMEOUT register
pl_timeout_value = 200 # the timeout value in units of us
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
# Page Size and a 64B L1 Cache Line Size. It programs the
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
# If a Master PF Driver finds itself on a machine with different
# parameters, then the Master PF Driver is responsible for initializing
# these parameters to appropriate values.
#
# Notes:
# 1. The Free List Buffer Sizes below are raw and the firmware will
# round them up to the Ingress Padding Boundary.
# 2. The SGE Timer Values below are expressed below in microseconds.
# The firmware will convert these values to Core Clock Ticks when
# it processes the configuration parameters.
#
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
# enable TP_OUT_CONFIG.IPIDSPLITMODE
reg[0x7d04] = 0x00010000/0x00010000
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
#Tick granularities in kbps
tsch_ticks = 100000, 10000, 1000, 10
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
# filter control: compact, fcoemask
# server sram : srvrsram
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
# protocol, tos, vlan, vnic_id, port, fcoe
# valid filterModes are described the Terminator 5 Data Book
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
# filter tuples enforced in LE active region (equal to or subset of filterMode)
filterMask = protocol, fcoe
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP RX payload
tp_pmrx = 30
# TP RX payload page size
tp_pmrx_pagesize = 64K
# TP number of RX channels
tp_nrxch = 0 # 0 (auto) = 1
# Percentage of dynamic memory (in either the EDRAM or external MEM)
# to use for TP TX payload
tp_pmtx = 50
# TP TX payload page size
tp_pmtx_pagesize = 64K
# TP number of TX channels
tp_ntxch = 0 # 0 (auto) = equal number of ports
# TP OFLD MTUs
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
reg[0x7d04] = 0x00010008/0x00010008
# TP_GLOBAL_CONFIG
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
# TP_PC_CONFIG
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
# TP_PARA_REG0
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
# LE_DB_CONFIG
reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
# LE IPv4 compression disabled
# LE_DB_HASH_CONFIG
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
# ULP_TX_CONFIG
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
# Enable more error msg for ...
# TPT error.
# ULP_RX_MISC_FEATURE_ENABLE
#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
# Enable offset decrement after ...
# PI extraction and before DDP
# ulp insert pi source info in DIF
# iscsi_eff_offset_en
#Enable iscsi completion moderation feature
reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
# PI extraction and before DDP.
# ulp insert pi source info in
# DIF.
# Enable iscsi hdr cmd mode.
# iscsi force cmd mode.
# Enable iscsi cmp mode.
# MC configuration
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
# Some "definitions" to make the rest of this a bit more readable. We support
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
# per function per port ...
#
# NMSIX = 1088 # available MSI-X Vectors
# NVI = 256 # available Virtual Interfaces
# NMPSTCAM = 336 # MPS TCAM entries
#
# NPORTS = 2 # ports
# NCPUS = 16 # CPUs we want to support scalably
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
# PF" which many OS Drivers will use to manage most or all functions.
#
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
# will be specified as the "Ingress Queue Asynchronous Destination Index."
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
# than or equal to the number of Ingress Queues ...
#
# NVI_NIC = 4 # NIC access to NPORTS
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
#
# NVI_OFLD = 0 # Offload uses NIC function to access ports
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
#
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
#
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
# NETHCTRL_WD = 64 # Wire Direct TX Queues
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
#
# NVI_ISCSI = 4 # ISCSI access to NPORTS
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
#
# NVI_FCOE = 4 # FCOE access to NPORTS
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
# Two extra Ingress Queues per function for Firmware Events and Forwarded
# Interrupts, and two extra interrupts per function for Firmware Events (or a
# Forwarded Interrupt Queue) and General Interrupts per function.
#
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
# # Forwarded Interrupts
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
# # General Interrupts
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
#
# NVI_HYPERV = 16 # VMs we want to support
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
# NEQ_HYPERV = 32 # VIQs Free Lists
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
#
# NVI_UNIFIED = 28
# NFLIQ_UNIFIED = 106
# NETHCTRL_UNIFIED = 32
# NEQ_UNIFIED = 124
# NMPSTCAM_UNIFIED = 40
#
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
# that up to 128 to make sure the Unified PF doesn't run out of resources.
#
# NMSIX_UNIFIED = 128
#
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
# which is 34 but they're probably safe with 32.
#
# NMSIX_STORAGE = 32
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
# associated with it. Thus, the MSI-X Vector allocations we give to the
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
# provision many more Virtual Functions than we can if the UnifiedPF were
# one of PF0-3.
#
# All of the below PCI-E parameters are actually stored in various *_init.txt
# files. We include them below essentially as comments.
#
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
# ports 0-3.
#
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
#
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
# storage applications across all four possible ports.
#
# Additionally, since the UnifiedPF isn't one of the per-port Physical
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
# different PCI Device IDs which will allow Unified and Per-Port Drivers
# to directly select the type of Physical Function to which they wish to be
# attached.
#
# Note that the actual values used for the PCI-E Intelectual Property will be
# 1 less than those below since that's the way it "counts" things. For
# readability, we use the number we actually mean ...
#
# PF0_INT = 8 # NCPUS
# PF1_INT = 8 # NCPUS
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
#
# PF4_INT = 128 # NMSIX_UNIFIED
# PF5_INT = 32 # NMSIX_STORAGE
# PF6_INT = 32 # NMSIX_STORAGE
# PF7_INT = 0 # Nothing Assigned
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
#
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
#
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
#
# NVF = 16
# For those OSes which manage different ports on different PFs, we need
# only enough resources to support a single port's NIC application functions
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
# managed on the "storage PFs" (see below).
#
[function "0"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x1 # access to only one port
[function "1"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x2 # access to only one port
[function "2"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x4 # access to only one port
[function "3"]
nvf = 16 # NVF on this function
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 1 # 1 port
niqflint = 8 # NCPUS "Queue Sets"
nethctrl = 8 # NCPUS "Queue Sets"
neq = 16 # niqflint + nethctrl Egress Queues
nexactf = 8 # number of exact MPSTCAM MAC filters
cmask = all # access to all channels
pmask = 0x8 # access to only one port
# Some OS Drivers manage all application functions for all ports via PF4.
# Thus we need to provide a large number of resources here. For Egress
# Queues we need to account for both TX Queues as well as Free List Queues
# (because the host is responsible for producing Free List Buffers for the
# hardware to consume).
#
[function "4"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 28 # NVI_UNIFIED
niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
neq = 256 # NEQ_UNIFIED + NEQ_WD
nqpcq = 12288
nexactf = 40 # NMPSTCAM_UNIFIED
cmask = all # access to all channels
pmask = all # access to all four ports ...
nethofld = 1024 # number of user mode ethernet flow contexts
ncrypto_lookaside = 16 # Number of lookaside flow contexts
nclip = 320 # number of clip region entries
nfilter = 496 # number of filter region entries
nserver = 496 # number of server region entries
nhash = 12288 # number of hash region entries
nhpfilter = 0 # number of high priority filter region entries
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
tp_l2t = 3072
tp_ddp = 2
tp_ddp_iscsi = 2
tp_tls_key = 3
tp_stag = 2
tp_pbl = 5
tp_rq = 7
tp_srq = 128
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
# "Queue Sets" each.
#
[function "5"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NPORTS
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
nethctrl = 32 # NPORTS*NCPUS
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
cmask = all # access to all channels
pmask = all # access to all four ports ...
nserver = 16
nhash = 2048
tp_l2t = 1020
nclip = 64
protocol = iscsi_initiator_fofld
tp_ddp_iscsi = 2
iscsi_ntask = 2048
iscsi_nsess = 2048
iscsi_nconn_per_session = 1
iscsi_ninitiator_instance = 64
[function "6"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NPORTS
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
nethctrl = 32 # NPORTS*NCPUS
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
# which is OK since < MIN(SUM PF0..3, PF4)
# and we never load PF0..3 and PF4 concurrently
cmask = all # access to all channels
pmask = all # access to all four ports ...
nhash = 2048
tp_l2t = 4
protocol = fcoe_initiator
tp_ddp = 2
fcoe_nfcf = 16
fcoe_nvnp = 32
fcoe_nssn = 1024
# The following function, 1023, is not an actual PCIE function but is used to
# configure and reserve firmware internal resources that come from the global
# resource pool.
#
[function "1023"]
wx_caps = all # write/execute permissions for all commands
r_caps = all # read permissions for all commands
nvi = 4 # NVI_UNIFIED
cmask = all # access to all channels
pmask = all # access to all four ports ...
nexactf = 8 # NPORTS + DCBX +
nfilter = 16 # number of filter region entries
# For Virtual functions, we only allow NIC functionality and we only allow
# access to one port (1 << PF). Note that because of limitations in the
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
# and GTS registers, the number of Ingress and Egress Queues must be a power
# of 2.
#
[function "0/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
[function "1/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
[function "2/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x1 # access to only one port ...
[function "3/*"] # NVF
wx_caps = 0x82 # DMAQ | VF
r_caps = 0x86 # DMAQ | VF | PORT
nvi = 1 # 1 port
niqflint = 4 # 2 "Queue Sets" + NXIQ
nethctrl = 2 # 2 "Queue Sets"
neq = 4 # 2 "Queue Sets" * 2
nexactf = 4
cmask = all # access to all channels
pmask = 0x2 # access to only one port ...
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
# for packets from the wire as well as the loopback path of the L2 switch. The
# folling params control how the buffer memory is distributed and the L2 flow
# control settings:
#
# bg_mem: %-age of mem to use for port/buffer group
# lpbk_mem: %-age of port/bg mem to use for loopback
# hwm: high watermark; bytes available when starting to send pause
# frames (in units of 0.1 MTU)
# lwm: low watermark; bytes remaining when sending 'unpause' frame
# (in inuits of 0.1 MTU)
# dwm: minimum delta between high and low watermark (in units of 100
# Bytes)
#
[port "0"]
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
#bg_mem = 25
#lpbk_mem = 25
hwm = 60
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
aec_retry_cnt = 4
[port "1"]
dcb = ppp, dcbx
#bg_mem = 25
#lpbk_mem = 25
hwm = 60
lwm = 15
dwm = 30
dcb_app_tlv[0] = 0x8906, ethertype, 3
dcb_app_tlv[1] = 0x8914, ethertype, 3
dcb_app_tlv[2] = 3260, socketnum, 5
aec_retry_cnt = 4
[fini]
version = 0x01000023
checksum = 0x683208a2
# Total resources used by above allocations:
# Virtual Interfaces: 104
# Ingress Queues/w Free Lists and Interrupts: 526
# Egress Queues: 702
# MPS TCAM Entries: 336
# MSI-X Vectors: 736
# Virtual Functions: 64
#
# $FreeBSD$
#

30
sys/dev/cxgbe/t4_main.c
View File

@ -3590,11 +3590,12 @@ build_medialist(struct port_info *pi, struct ifmedia *media)
break;
case FW_PORT_TYPE_CR_QSFP:
case FW_PORT_TYPE_CR_SFP28:
case FW_PORT_TYPE_SFP28:
case FW_PORT_TYPE_KR_SFP28:
switch (pi->mod_type) {
case FW_PORT_MOD_TYPE_SR:
MPASS(pi->port_type == FW_PORT_TYPE_SFP28);
ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
ifmedia_set(media, m | IFM_25G_SR);
break;
@ -3656,31 +3657,6 @@ build_medialist(struct port_info *pi, struct ifmedia *media)
}
break;
case FW_PORT_TYPE_CR2_QSFP:
switch (pi->mod_type) {
case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
ifmedia_add(media, m | IFM_50G_CR2, 0, NULL);
ifmedia_set(media, m | IFM_50G_CR2);
break;
case FW_PORT_MOD_TYPE_NONE:
m &= ~IFM_FDX;
ifmedia_add(media, m | IFM_NONE, 0, NULL);
ifmedia_set(media, m | IFM_NONE);
break;
default:
device_printf(pi->dev,
"unknown port_type (%d), mod_type (%d)\n",
pi->port_type, pi->mod_type);
ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
ifmedia_set(media, m | IFM_UNKNOWN);
break;
}
break;
case FW_PORT_TYPE_KR4_100G:
case FW_PORT_TYPE_CR4_QSFP:
switch (pi->mod_type) {
@ -4457,7 +4433,7 @@ vi_full_init(struct vi_info *vi)
F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
#endif
rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
if (rc != 0) {
if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
goto done;

1
sys/modules/cxgbe/Makefile
View File

@ -13,6 +13,7 @@ SUBDIR+= if_cxlv
SUBDIR+= if_ccv
SUBDIR+= t4_firmware
SUBDIR+= t5_firmware
SUBDIR+= t6_firmware
SUBDIR+= ${_tom}
SUBDIR+= ${_iw_cxgbe}
SUBDIR+= ${_cxgbei}

2
sys/modules/cxgbe/t4_firmware/Makefile
View File

@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T4FW_VER= 1.15.37.0
T4FW_VER= 1.16.12.0
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
CLEANFILES+= t4fw.fw

2
sys/modules/cxgbe/t5_firmware/Makefile
View File

@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T5FW_VER= 1.15.37.0
T5FW_VER= 1.16.12.0
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
CLEANFILES+= t5fw.fw

27
sys/modules/cxgbe/t6_firmware/Makefile Normal file
View File

@ -0,0 +1,27 @@
#
# $FreeBSD$
#
T6FW= ${.CURDIR}/../../../dev/cxgbe/firmware
.PATH: ${T6FW}
KMOD= t6fw_cfg
FIRMWS= ${KMOD}.txt:${KMOD}:1.0.0.0
# You can have additional configuration files in the ${T6FW} directory.
# t6fw_cfg_<name>.txt
CFG_FILES != cd ${T6FW} && echo ${KMOD}_*.txt
.for F in ${CFG_FILES}
.if exists(${F})
FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
.endif
.endfor
T6FW_VER= 1.16.12.0
FIRMWS+= t6fw.fw:t6fw:${T6FW_VER}
CLEANFILES+= t6fw.fw
t6fw.fw: t6fw-${T6FW_VER}.bin.uu
uudecode -o ${.TARGET} ${.ALLSRC}
.include <bsd.kmod.mk>