Move towards isa attachment for pccbb. This is a work in progress, but
works well with the pci attachment.
This commit is contained in:
imp
parent
885cdf40be
commit
2d3c2de7f0
@ -599,6 +599,8 @@ dev/pccard/pccard_cis.c optional pccard
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dev/pccard/pccard_cis_quirks.c optional pccard
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dev/pccard/power_if.m standard
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dev/pccbb/pccbb.c optional cbb
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dev/pccbb/pccbb_isa.c optional cbb isa
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dev/pccbb/pccbb_pci.c optional cbb pci
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dev/pci/eisa_pci.c optional pci eisa
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dev/pci/fixup_pci.c optional pci
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dev/pci/ignore_pci.c optional pci
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File diff suppressed because it is too large
Load Diff
221
sys/dev/pccbb/pccbb_isa.c
Normal file
221
sys/dev/pccbb/pccbb_isa.c
Normal file
@ -0,0 +1,221 @@
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/*
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* Copyright (c) 2002-2004 M. Warner Losh.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Driver for ISA to PCMCIA bridges compliant with the Intel ExCA
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* specification.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/condvar.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/kthread.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <isa/isavar.h>
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#include <dev/pccard/pccardreg.h>
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#include <dev/pccard/pccardvar.h>
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#include <dev/exca/excareg.h>
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#include <dev/exca/excavar.h>
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#include <dev/pccbb/pccbbreg.h>
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#include <dev/pccbb/pccbbvar.h>
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#include "power_if.h"
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#include "card_if.h"
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/*****************************************************************************
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* Configurable parameters.
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*****************************************************************************/
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/* sysctl vars */
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SYSCTL_NODE(_hw, OID_AUTO, pcic, CTLFLAG_RD, 0, "PCIC parameters");
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static int isa_intr_mask = EXCA_INT_MASK_ALLOWED;
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TUNABLE_INT("hw.cbb.intr_mask", &isa_intr_mask);
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SYSCTL_INT(_hw_pcic, OID_AUTO, intr_mask, CTLFLAG_RD, &isa_intr_mask, 0,
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"Mask of allowable interrupts for this laptop. The default is generally\n\
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correct, but some laptops do not route all the IRQ pins to the bridge to\n\
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save wires. Sometimes you need a more restrictive mask because some of the\n\
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hardware in your laptop may not have a driver so its IRQ might not be\n\
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allocated.");
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/*****************************************************************************
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* End of configurable parameters.
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*****************************************************************************/
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#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
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#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
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static struct isa_pnp_id pcic_ids[] = {
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{EXCA_PNP_ACTIONTEC, NULL}, /* AEI0218 */
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{EXCA_PNP_IBM3765, NULL}, /* IBM3765 */
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{EXCA_PNP_82365, NULL}, /* PNP0E00 */
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{EXCA_PNP_CL_PD6720, NULL}, /* PNP0E01 */
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{EXCA_PNP_VLSI_82C146, NULL}, /* PNP0E02 */
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{EXCA_PNP_82365_CARDBUS, NULL}, /* PNP0E03 */
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{EXCA_PNP_SCM_SWAPBOX, NULL}, /* SCM0469 */
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{0}
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};
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/************************************************************************/
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/* Probe/Attach */
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/************************************************************************/
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#if 0
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struct resource *res;
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int rid;
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int i;
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/* A little bogus, but go ahead and get the irq for CSC events */
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rid = 0;
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res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
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if (res == NULL) {
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/*
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* No IRQ specified, find one. This can be due to the PnP
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* data not specifying any IRQ, or the default kernel not
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* assinging an IRQ.
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*/
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for (i = 0; i < 16; i++) {
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if (((1 << i) & isa_intr_mask) == 0)
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continue;
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res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, i, i,
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1, RF_ACTIVE);
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if (res != NULL)
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break;
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}
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if (res == NULL)
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return (ENXIO);
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bus_release_resource(dev, SYS_RES_IRQ, rid, res);
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bus_set_resource(dev, SYS_RES_IRQ, 0, i, 1);
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} else {
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bus_release_resource(dev, SYS_RES_IRQ, rid, res);
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}
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if (res == NULL) {
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device_printf(dev, "Cannot allocate mem\n");
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return (ENOMEM);
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}
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#endif
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static int
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cbb_isa_activate(device_t dev)
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{
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return (ENOMEM);
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}
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static void
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cbb_isa_deactivate(device_t dev)
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{
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}
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static int
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cbb_isa_probe(device_t dev)
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{
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int error;
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struct cbb_softc *sc = device_get_softc(dev);
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/* Check isapnp ids */
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error = ISA_PNP_PROBE(device_get_parent(dev), dev, pcic_ids);
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if (error != 0 && error != ENOENT)
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return (error);
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error = cbb_isa_activate(dev);
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if (error != 0)
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return (error);
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/* Check to make sure that we have actual hardware */
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error = exca_probe_slots(dev, &sc->exca[0], sc->bst, sc->bsh);
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cbb_isa_deactivate(dev);
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return (error);
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}
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static int
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cbb_isa_attach(device_t dev)
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{
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return (ENOMEM);
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}
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static device_method_t cbb_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, cbb_isa_probe),
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DEVMETHOD(device_attach, cbb_isa_attach),
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DEVMETHOD(device_detach, cbb_detach),
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DEVMETHOD(device_shutdown, cbb_shutdown),
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DEVMETHOD(device_suspend, cbb_suspend),
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DEVMETHOD(device_resume, cbb_resume),
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/* bus methods */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, cbb_read_ivar),
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DEVMETHOD(bus_write_ivar, cbb_write_ivar),
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DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
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DEVMETHOD(bus_release_resource, cbb_release_resource),
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DEVMETHOD(bus_activate_resource, cbb_activate_resource),
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DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
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DEVMETHOD(bus_driver_added, cbb_driver_added),
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DEVMETHOD(bus_child_detached, cbb_child_detached),
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DEVMETHOD(bus_setup_intr, cbb_setup_intr),
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DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
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DEVMETHOD(bus_child_present, cbb_child_present),
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/* 16-bit card interface */
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DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
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DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
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/* power interface */
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DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
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DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
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{0,0}
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};
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static driver_t cbb_isa_driver = {
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"cbb",
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cbb_methods,
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sizeof(struct cbb_softc)
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};
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DRIVER_MODULE(cbb, isa, cbb_isa_driver, cbb_devclass, 0, 0);
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MODULE_VERSION(cbb, 1);
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MODULE_DEPEND(cbb, exca, 1, 1, 1);
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655
sys/dev/pccbb/pccbb_pci.c
Normal file
655
sys/dev/pccbb/pccbb_pci.c
Normal file
@ -0,0 +1,655 @@
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/*
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* Copyright (c) 2002-2004 M. Warner Losh.
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* Copyright (c) 2000-2001 Jonathan Chen.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1998, 1999 and 2000
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* HAYAKAWA Koichi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by HAYAKAWA Koichi.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for PCI to CardBus Bridge chips
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*
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* References:
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* TI Datasheets:
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* http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
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*
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* Written by Jonathan Chen <jon@freebsd.org>
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* The author would like to acknowledge:
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* * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
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* * Warner Losh: Newbus/newcard guru and author of the pccard side of things
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* * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
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* * David Cross: Author of the initial ugly hack for a specific cardbus card
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/condvar.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/kthread.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <sys/module.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <machine/clock.h>
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#include <dev/pccard/pccardreg.h>
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#include <dev/pccard/pccardvar.h>
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#include <dev/exca/excareg.h>
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#include <dev/exca/excavar.h>
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#include <dev/pccbb/pccbbreg.h>
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#include <dev/pccbb/pccbbvar.h>
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#include "power_if.h"
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#include "card_if.h"
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#include "pcib_if.h"
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#define DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
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#define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
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#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
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pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
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#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
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pci_write_config(DEV, REG, ( \
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pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
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static void cbb_chipinit(struct cbb_softc *sc);
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static struct yenta_chipinfo {
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uint32_t yc_id;
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const char *yc_name;
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int yc_chiptype;
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} yc_chipsets[] = {
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/* Texas Instruments chips */
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{PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
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{PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
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{PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
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{PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
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{PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
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{PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
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{PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
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{PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
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{PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
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/* ENE */
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{PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
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{PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
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/* Ricoh chips */
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{PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
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{PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
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{PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
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||||
{PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
|
||||
{PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
|
||||
{PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
|
||||
|
||||
/* Toshiba products */
|
||||
{PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
|
||||
{PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
|
||||
{PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
|
||||
{PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
|
||||
|
||||
/* Cirrus Logic */
|
||||
{PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
|
||||
{PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
|
||||
{PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
|
||||
|
||||
/* 02Micro */
|
||||
{PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
{PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
|
||||
|
||||
/* sentinel */
|
||||
{0 /* null id */, "unknown", CB_UNKNOWN},
|
||||
};
|
||||
|
||||
/************************************************************************/
|
||||
/* Probe/Attach */
|
||||
/************************************************************************/
|
||||
|
||||
static int
|
||||
cbb_chipset(uint32_t pci_id, const char **namep)
|
||||
{
|
||||
struct yenta_chipinfo *ycp;
|
||||
|
||||
for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
|
||||
continue;
|
||||
if (namep != NULL)
|
||||
*namep = ycp->yc_name;
|
||||
return (ycp->yc_chiptype);
|
||||
}
|
||||
|
||||
static int
|
||||
cbb_pci_probe(device_t brdev)
|
||||
{
|
||||
const char *name;
|
||||
uint32_t progif;
|
||||
uint32_t subclass;
|
||||
|
||||
/*
|
||||
* Do we know that we support the chipset? If so, then we
|
||||
* accept the device.
|
||||
*/
|
||||
if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
|
||||
device_set_desc(brdev, name);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* We do support generic CardBus bridges. All that we've seen
|
||||
* to date have progif 0 (the Yenta spec, and successors mandate
|
||||
* this). We do not support PCI PCMCIA bridges (with one exception)
|
||||
* with this driver since they generally are I/O mapped. Those
|
||||
* are supported by the pcic driver. This should help us be more
|
||||
* future proof.
|
||||
*/
|
||||
subclass = pci_get_subclass(brdev);
|
||||
progif = pci_get_progif(brdev);
|
||||
if (subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
|
||||
device_set_desc(brdev, "PCI-CardBus Bridge");
|
||||
return (0);
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
#ifndef BURN_BRIDGES
|
||||
/*
|
||||
* Still need this because the pci code only does power for type 0
|
||||
* header devices.
|
||||
*/
|
||||
static void
|
||||
cbb_powerstate_d0(device_t dev)
|
||||
{
|
||||
u_int32_t membase, irq;
|
||||
|
||||
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
|
||||
/* Save important PCI config data. */
|
||||
membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
|
||||
irq = pci_read_config(dev, PCIR_INTLINE, 4);
|
||||
|
||||
/* Reset the power state. */
|
||||
device_printf(dev, "chip is in D%d power mode "
|
||||
"-- setting to D0\n", pci_get_powerstate(dev));
|
||||
|
||||
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
||||
|
||||
/* Restore PCI config data. */
|
||||
pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
|
||||
pci_write_config(dev, PCIR_INTLINE, irq, 4);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Print out the config space
|
||||
*/
|
||||
static void
|
||||
cbb_print_config(device_t dev)
|
||||
{
|
||||
int i;
|
||||
|
||||
device_printf(dev, "PCI Configuration space:");
|
||||
for (i = 0; i < 256; i += 4) {
|
||||
if (i % 16 == 0)
|
||||
printf("\n 0x%02x: ", i);
|
||||
printf("0x%08x ", pci_read_config(dev, i, 4));
|
||||
}
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static int
|
||||
cbb_pci_attach(device_t brdev)
|
||||
{
|
||||
static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
|
||||
struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
|
||||
int rid, bus, pribus;
|
||||
device_t parent;
|
||||
|
||||
parent = device_get_parent(brdev);
|
||||
mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
|
||||
cv_init(&sc->cv, "cbb cv");
|
||||
sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
|
||||
sc->dev = brdev;
|
||||
sc->cbdev = NULL;
|
||||
sc->exca[0].pccarddev = NULL;
|
||||
sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
|
||||
sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
|
||||
SLIST_INIT(&sc->rl);
|
||||
STAILQ_INIT(&sc->intr_handlers);
|
||||
#ifndef BURN_BRIDGES
|
||||
cbb_powerstate_d0(brdev);
|
||||
#endif
|
||||
|
||||
rid = CBBR_SOCKBASE;
|
||||
sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
|
||||
RF_ACTIVE);
|
||||
if (!sc->base_res) {
|
||||
device_printf(brdev, "Could not map register memory\n");
|
||||
mtx_destroy(&sc->mtx);
|
||||
cv_destroy(&sc->cv);
|
||||
return (ENOMEM);
|
||||
} else {
|
||||
DEVPRINTF((brdev, "Found memory at %08lx\n",
|
||||
rman_get_start(sc->base_res)));
|
||||
}
|
||||
|
||||
sc->bst = rman_get_bustag(sc->base_res);
|
||||
sc->bsh = rman_get_bushandle(sc->base_res);
|
||||
exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
|
||||
sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
|
||||
sc->exca[0].chipset = EXCA_CARDBUS;
|
||||
sc->chipinit = cbb_chipinit;
|
||||
sc->chipinit(sc);
|
||||
|
||||
/*
|
||||
* This is a gross hack. We should be scanning the entire pci
|
||||
* tree, assigning bus numbers in a way such that we (1) can
|
||||
* reserve 1 extra bus just in case and (2) all sub busses
|
||||
* are in an appropriate range.
|
||||
*/
|
||||
bus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
|
||||
pribus = pcib_get_bus(parent);
|
||||
DEVPRINTF((brdev, "Secondary bus is %d\n", bus));
|
||||
if (bus == 0) {
|
||||
if (curr_bus_number <= pribus)
|
||||
curr_bus_number = pribus + 1;
|
||||
if (pci_read_config(brdev, PCIR_PRIBUS_2, 1) != pribus) {
|
||||
DEVPRINTF((brdev, "Setting primary bus to %d\n", pribus));
|
||||
pci_write_config(brdev, PCIR_PRIBUS_2, pribus, 1);
|
||||
}
|
||||
bus = curr_bus_number;
|
||||
DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", bus,
|
||||
bus + 1));
|
||||
sc->secbus = bus;
|
||||
sc->subbus = bus + 1;
|
||||
pci_write_config(brdev, PCIR_SECBUS_2, bus, 1);
|
||||
pci_write_config(brdev, PCIR_SUBBUS_2, bus + 1, 1);
|
||||
curr_bus_number += 2;
|
||||
}
|
||||
|
||||
/* attach children */
|
||||
sc->cbdev = device_add_child(brdev, "cardbus", -1);
|
||||
if (sc->cbdev == NULL)
|
||||
DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
|
||||
else if (device_probe_and_attach(sc->cbdev) != 0)
|
||||
DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
|
||||
|
||||
sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
|
||||
if (sc->exca[0].pccarddev == NULL)
|
||||
DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
|
||||
else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
|
||||
DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
|
||||
|
||||
/* Map and establish the interrupt. */
|
||||
rid = 0;
|
||||
sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
|
||||
RF_SHAREABLE | RF_ACTIVE);
|
||||
if (sc->irq_res == NULL) {
|
||||
printf("cbb: Unable to map IRQ...\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
|
||||
cbb_intr, sc, &sc->intrhand)) {
|
||||
device_printf(brdev, "couldn't establish interrupt");
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* reset 16-bit pcmcia bus */
|
||||
exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
|
||||
|
||||
/* turn off power */
|
||||
cbb_power(brdev, CARD_OFF);
|
||||
|
||||
/* CSC Interrupt: Card detect interrupt on */
|
||||
cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
|
||||
|
||||
/* reset interrupt */
|
||||
cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
|
||||
|
||||
if (bootverbose)
|
||||
cbb_print_config(brdev);
|
||||
|
||||
/* Start the thread */
|
||||
if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
|
||||
"%s", device_get_nameunit(brdev))) {
|
||||
device_printf(brdev, "unable to create event thread.\n");
|
||||
panic("cbb_create_event_thread");
|
||||
}
|
||||
return (0);
|
||||
err:
|
||||
if (sc->irq_res)
|
||||
bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
|
||||
if (sc->base_res) {
|
||||
bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
|
||||
sc->base_res);
|
||||
}
|
||||
mtx_destroy(&sc->mtx);
|
||||
cv_destroy(&sc->cv);
|
||||
return (ENOMEM);
|
||||
}
|
||||
|
||||
static void
|
||||
cbb_chipinit(struct cbb_softc *sc)
|
||||
{
|
||||
uint32_t mux, sysctrl, reg;
|
||||
|
||||
/* Set CardBus latency timer */
|
||||
if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
|
||||
pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
|
||||
|
||||
/* Set PCI latency timer */
|
||||
if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
|
||||
pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
|
||||
|
||||
/* Enable memory access */
|
||||
PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
|
||||
| PCIM_CMD_MEMEN
|
||||
| PCIM_CMD_PORTEN
|
||||
| PCIM_CMD_BUSMASTEREN, 2);
|
||||
|
||||
/* disable Legacy IO */
|
||||
switch (sc->chipset) {
|
||||
case CB_RF5C46X:
|
||||
PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
|
||||
& ~(CBBM_BRIDGECTRL_RL_3E0_EN |
|
||||
CBBM_BRIDGECTRL_RL_3E2_EN), 2);
|
||||
break;
|
||||
default:
|
||||
pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Use PCI interrupt for interrupt routing */
|
||||
PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
|
||||
& ~(CBBM_BRIDGECTRL_MASTER_ABORT |
|
||||
CBBM_BRIDGECTRL_INTR_IREQ_EN),
|
||||
| CBBM_BRIDGECTRL_WRITE_POST_EN,
|
||||
2);
|
||||
|
||||
/*
|
||||
* XXX this should be a function table, ala OLDCARD. This means
|
||||
* that we could more easily support ISA interrupts for pccard
|
||||
* cards if we had to.
|
||||
*/
|
||||
switch (sc->chipset) {
|
||||
case CB_TI113X:
|
||||
/*
|
||||
* The TI 1031, TI 1130 and TI 1131 all require another bit
|
||||
* be set to enable PCI routing of interrupts, and then
|
||||
* a bit for each of the CSC and Function interrupts we
|
||||
* want routed.
|
||||
*/
|
||||
PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
|
||||
| CBBM_CBCTRL_113X_PCI_INTR |
|
||||
CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
|
||||
1);
|
||||
PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
|
||||
& ~(CBBM_DEVCTRL_INT_SERIAL |
|
||||
CBBM_DEVCTRL_INT_PCI), 1);
|
||||
break;
|
||||
case CB_TI12XX:
|
||||
/*
|
||||
* Some TI 12xx (and [14][45]xx) based pci cards
|
||||
* sometimes have issues with the MFUNC register not
|
||||
* being initialized due to a bad EEPROM on board.
|
||||
* Laptops that this matters on have this register
|
||||
* properly initialized.
|
||||
*
|
||||
* The TI125X parts have a different register.
|
||||
*/
|
||||
mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
|
||||
sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
|
||||
if (mux == 0) {
|
||||
mux = (mux & ~CBBM_MFUNC_PIN0) |
|
||||
CBBM_MFUNC_PIN0_INTA;
|
||||
if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
|
||||
mux = (mux & ~CBBM_MFUNC_PIN1) |
|
||||
CBBM_MFUNC_PIN1_INTB;
|
||||
pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
|
||||
}
|
||||
/*FALLTHROUGH*/
|
||||
case CB_TI125X:
|
||||
/*
|
||||
* Disable zoom video. Some machines initialize this
|
||||
* improperly and exerpience has shown that this helps
|
||||
* prevent strange behavior.
|
||||
*/
|
||||
pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
|
||||
break;
|
||||
case CB_O2MICRO:
|
||||
/*
|
||||
* Issue #1: INT# generated at the same time as
|
||||
* selected ISA IRQ. When IREQ# or STSCHG# is active,
|
||||
* in addition to the ISA IRQ being generated, INT#
|
||||
* will also be generated at the same time.
|
||||
*
|
||||
* Some of the older controllers have an issue in
|
||||
* which the slot's PCI INT# will be asserted whenever
|
||||
* IREQ# or STSCGH# is asserted even if ExCA registers
|
||||
* 03h or 05h have an ISA IRQ selected.
|
||||
*
|
||||
* The fix for this issue, which will work for any
|
||||
* controller (old or new), is to set ExCA registers
|
||||
* 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
|
||||
* These bits are undocumented. By setting this
|
||||
* register (of each slot) to '1010xxxxb' a routing of
|
||||
* IREQ# to INTC# and STSCHG# to INTC# is selected.
|
||||
* Since INTC# isn't connected there will be no
|
||||
* unexpected PCI INT when IREQ# or STSCHG# is active.
|
||||
* However, INTA# (slot 0) or INTB# (slot 1) will
|
||||
* still be correctly generated if NO ISA IRQ is
|
||||
* selected (ExCA regs 03h or 05h are cleared).
|
||||
*/
|
||||
reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
|
||||
reg = (reg & 0x0f) |
|
||||
EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
|
||||
exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
|
||||
|
||||
break;
|
||||
case CB_TOPIC97:
|
||||
/*
|
||||
* Disable Zoom Video, ToPIC 97, 100.
|
||||
*/
|
||||
pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1);
|
||||
/*
|
||||
* ToPIC 97, 100
|
||||
* At offset 0xa1: INTERRUPT CONTROL register
|
||||
* 0x1: Turn on INT interrupts.
|
||||
*/
|
||||
PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL,
|
||||
| CBBM_TOPIC_INTCTRL_INTIRQSEL, 1);
|
||||
goto topic_common;
|
||||
case CB_TOPIC95:
|
||||
/*
|
||||
* SOCKETCTRL appears to be TOPIC 95/B specific
|
||||
*/
|
||||
PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL,
|
||||
| CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4);
|
||||
|
||||
topic_common:;
|
||||
/*
|
||||
* At offset 0xa0: SLOT CONTROL
|
||||
* 0x80 Enable CardBus Functionality
|
||||
* 0x40 Enable CardBus and PC Card registers
|
||||
* 0x20 Lock ID in exca regs
|
||||
* 0x10 Write protect ID in config regs
|
||||
* Clear the rest of the bits, which defaults the slot
|
||||
* in legacy mode to 0x3e0 and offset 0. (legacy
|
||||
* mode is determined elsewhere)
|
||||
*/
|
||||
pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL,
|
||||
CBBM_TOPIC_SLOTCTRL_SLOTON |
|
||||
CBBM_TOPIC_SLOTCTRL_SLOTEN |
|
||||
CBBM_TOPIC_SLOTCTRL_ID_LOCK |
|
||||
CBBM_TOPIC_SLOTCTRL_ID_WP, 1);
|
||||
|
||||
/*
|
||||
* At offset 0xa3 Card Detect Control Register
|
||||
* 0x80 CARDBUS enbale
|
||||
* 0x01 Cleared for hardware change detect
|
||||
*/
|
||||
PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC,
|
||||
| CBBM_TOPIC_CDC_CARDBUS,
|
||||
& ~CBBM_TOPIC_CDC_SWDETECT, 4);
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Need to tell ExCA registers to CSC interrupts route via PCI
|
||||
* interrupts. There are two ways to do this. Once is to set
|
||||
* INTR_ENABLE and the other is to set CSC to 0. Since both
|
||||
* methods are mutually compatible, we do both.
|
||||
*/
|
||||
exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
|
||||
exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
|
||||
|
||||
cbb_disable_func_intr(sc);
|
||||
|
||||
/* close all memory and io windows */
|
||||
pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
|
||||
pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
|
||||
pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
|
||||
pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
|
||||
pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
|
||||
pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
|
||||
pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
|
||||
pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
|
||||
}
|
||||
|
||||
static device_method_t cbb_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, cbb_pci_probe),
|
||||
DEVMETHOD(device_attach, cbb_pci_attach),
|
||||
DEVMETHOD(device_detach, cbb_detach),
|
||||
DEVMETHOD(device_shutdown, cbb_shutdown),
|
||||
DEVMETHOD(device_suspend, cbb_suspend),
|
||||
DEVMETHOD(device_resume, cbb_resume),
|
||||
|
||||
/* bus methods */
|
||||
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
||||
DEVMETHOD(bus_read_ivar, cbb_read_ivar),
|
||||
DEVMETHOD(bus_write_ivar, cbb_write_ivar),
|
||||
DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
|
||||
DEVMETHOD(bus_release_resource, cbb_release_resource),
|
||||
DEVMETHOD(bus_activate_resource, cbb_activate_resource),
|
||||
DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
|
||||
DEVMETHOD(bus_driver_added, cbb_driver_added),
|
||||
DEVMETHOD(bus_child_detached, cbb_child_detached),
|
||||
DEVMETHOD(bus_setup_intr, cbb_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
|
||||
DEVMETHOD(bus_child_present, cbb_child_present),
|
||||
|
||||
/* 16-bit card interface */
|
||||
DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
|
||||
DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
|
||||
|
||||
/* power interface */
|
||||
DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
|
||||
DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
|
||||
|
||||
/* pcib compatibility interface */
|
||||
DEVMETHOD(pcib_maxslots, cbb_maxslots),
|
||||
DEVMETHOD(pcib_read_config, cbb_read_config),
|
||||
DEVMETHOD(pcib_write_config, cbb_write_config),
|
||||
{0,0}
|
||||
};
|
||||
|
||||
static driver_t cbb_driver = {
|
||||
"cbb",
|
||||
cbb_methods,
|
||||
sizeof(struct cbb_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0);
|
||||
MODULE_VERSION(cbb, 1);
|
||||
MODULE_DEPEND(cbb, exca, 1, 1, 1);
|
||||
@ -1,4 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2003-2004 Warner Losh.
|
||||
* Copyright (c) 2000,2001 Jonathan Chen.
|
||||
* All rights reserved.
|
||||
*
|
||||
@ -35,7 +36,8 @@
|
||||
struct cbb_intrhand {
|
||||
driver_intr_t *intr;
|
||||
void *arg;
|
||||
uint32_t flags;
|
||||
struct cbb_softc *sc;
|
||||
void *cookie;
|
||||
STAILQ_ENTRY(cbb_intrhand) entries;
|
||||
};
|
||||
|
||||
@ -52,10 +54,11 @@ struct cbb_reslist {
|
||||
};
|
||||
|
||||
#define CBB_AUTO_OPEN_SMALLHOLE 0x100
|
||||
#define CBB_NSLOTS 4
|
||||
|
||||
struct cbb_softc {
|
||||
device_t dev;
|
||||
struct exca_softc exca;
|
||||
struct exca_softc exca[CBB_NSLOTS];
|
||||
struct resource *base_res;
|
||||
struct resource *irq_res;
|
||||
void *intrhand;
|
||||
@ -86,6 +89,7 @@ struct cbb_softc {
|
||||
|
||||
device_t cbdev;
|
||||
struct proc *event_thread;
|
||||
void (*chipinit)(struct cbb_softc *);
|
||||
};
|
||||
|
||||
/* result of detect_card */
|
||||
@ -104,3 +108,72 @@ struct cbb_softc {
|
||||
#define YV 1
|
||||
|
||||
#define CARD_OFF (CARD_VCC(0))
|
||||
|
||||
extern int cbb_debug;
|
||||
extern devclass_t cbb_devclass;
|
||||
|
||||
int cbb_activate_resource(device_t brdev, device_t child,
|
||||
int type, int rid, struct resource *r);
|
||||
struct resource *cbb_alloc_resource(device_t brdev, device_t child,
|
||||
int type, int *rid, u_long start, u_long end, u_long count,
|
||||
u_int flags);
|
||||
void cbb_child_detached(device_t brdev, device_t child);
|
||||
int cbb_child_present(device_t self);
|
||||
int cbb_deactivate_resource(device_t brdev, device_t child,
|
||||
int type, int rid, struct resource *r);
|
||||
int cbb_detach(device_t brdev);
|
||||
void cbb_disable_func_intr(struct cbb_softc *sc);
|
||||
void cbb_driver_added(device_t brdev, driver_t *driver);
|
||||
void cbb_event_thread(void *arg);
|
||||
void cbb_intr(void *arg);
|
||||
int cbb_maxslots(device_t brdev);
|
||||
int cbb_pcic_set_memory_offset(device_t brdev, device_t child, int rid,
|
||||
uint32_t cardaddr, uint32_t *deltap);
|
||||
int cbb_pcic_set_res_flags(device_t brdev, device_t child, int type,
|
||||
int rid, uint32_t flags);
|
||||
int cbb_power(device_t brdev, int volts);
|
||||
int cbb_power_enable_socket(device_t brdev, device_t child);
|
||||
void cbb_power_disable_socket(device_t brdev, device_t child);
|
||||
uint32_t cbb_read_config(device_t brdev, int b, int s, int f,
|
||||
int reg, int width);
|
||||
int cbb_read_ivar(device_t brdev, device_t child, int which,
|
||||
uintptr_t *result);
|
||||
int cbb_release_resource(device_t brdev, device_t child,
|
||||
int type, int rid, struct resource *r);
|
||||
int cbb_resume(device_t self);
|
||||
int cbb_setup_intr(device_t dev, device_t child, struct resource *irq,
|
||||
int flags, driver_intr_t *intr, void *arg, void **cookiep);
|
||||
int cbb_shutdown(device_t brdev);
|
||||
int cbb_suspend(device_t self);
|
||||
int cbb_teardown_intr(device_t dev, device_t child, struct resource *irq,
|
||||
void *cookie);
|
||||
void cbb_write_config(device_t brdev, int b, int s, int f,
|
||||
int reg, uint32_t val, int width);
|
||||
int cbb_write_ivar(device_t brdev, device_t child, int which,
|
||||
uintptr_t value);
|
||||
|
||||
/*
|
||||
*/
|
||||
static __inline void
|
||||
cbb_set(struct cbb_softc *sc, uint32_t reg, uint32_t val)
|
||||
{
|
||||
bus_space_write_4(sc->bst, sc->bsh, reg, val);
|
||||
}
|
||||
|
||||
static __inline uint32_t
|
||||
cbb_get(struct cbb_softc *sc, uint32_t reg)
|
||||
{
|
||||
return (bus_space_read_4(sc->bst, sc->bsh, reg));
|
||||
}
|
||||
|
||||
static __inline void
|
||||
cbb_setb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)
|
||||
{
|
||||
cbb_set(sc, reg, cbb_get(sc, reg) | bits);
|
||||
}
|
||||
|
||||
static __inline void
|
||||
cbb_clrb(struct cbb_softc *sc, uint32_t reg, uint32_t bits)
|
||||
{
|
||||
cbb_set(sc, reg, cbb_get(sc, reg) & ~bits);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user