Remove the old software bit-banging MII interface, we started using
the Rhines shiftregisters in four years ago (1.60).
This commit is contained in:
Poul-Henning Kamp
parent
28a811cd5b
commit
2efc0f7f47
@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
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* multicast filter. Transmit and receive descriptors are similar
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* to the tulip.
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*
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* The Rhine has a serious flaw in its transmit DMA mechanism:
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* Some Rhine chips has a serious flaw in its transmit DMA mechanism:
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* transmit buffers must be longword aligned. Unfortunately,
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* FreeBSD doesn't guarantee that mbufs will be filled in starting
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* at longword boundaries, so we have to do a buffer copy before
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@ -103,8 +103,6 @@ MODULE_DEPEND(vr, miibus, 1, 1, 1);
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/* "device miibus" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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#undef VR_USESWSHIFT
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/*
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* Various supported device vendors/types, their names & quirks
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*/
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@ -191,10 +189,6 @@ static void vr_shutdown(device_t);
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static int vr_ifmedia_upd(struct ifnet *);
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static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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#ifdef VR_USESWSHIFT
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static void vr_mii_sync(struct vr_softc *);
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static void vr_mii_send(struct vr_softc *, uint32_t, int);
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#endif
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static int vr_mii_readreg(const struct vr_softc *, struct vr_mii_frame *);
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static int vr_mii_writereg(const struct vr_softc *, const struct vr_mii_frame *);
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static int vr_miibus_readreg(device_t, uint16_t, uint16_t);
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@ -266,136 +260,12 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
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#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#ifdef VR_USESWSHIFT
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#define CSR_READ_4(sc, reg) bus_read_4(sc->vr_res, reg)
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#define SIO_SET(x) CSR_WRITE_1(sc, VR_MIICMD, CSR_READ_1(sc, VR_MIICMD) | (x))
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#define SIO_CLR(x) CSR_WRITE_1(sc, VR_MIICMD, CSR_READ_1(sc, VR_MIICMD) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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*/
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static void
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vr_mii_sync(struct vr_softc *sc)
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{
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register int i;
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SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
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for (i = 0; i < 32; i++) {
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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}
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}
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/*
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* Clock a series of bits through the MII.
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*/
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static void
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vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
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{
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int i;
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SIO_CLR(VR_MIICMD_CLK);
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for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
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if (bits & i) {
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SIO_SET(VR_MIICMD_DATAIN);
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} else {
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SIO_CLR(VR_MIICMD_DATAIN);
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}
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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}
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}
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#endif
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/*
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* Read an PHY register through the MII.
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*/
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static int
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vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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#ifdef VR_USESWSHIFT
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{
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int i, ack;
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/* Set up frame for RX. */
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frame->mii_stdelim = VR_MII_STARTDELIM;
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frame->mii_opcode = VR_MII_READOP;
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frame->mii_turnaround = 0;
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frame->mii_data = 0;
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CSR_WRITE_1(sc, VR_MIICMD, 0);
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VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
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/* Turn on data xmit. */
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SIO_SET(VR_MIICMD_DIR);
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vr_mii_sync(sc);
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/* Send command/address info. */
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vr_mii_send(sc, frame->mii_stdelim, 2);
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vr_mii_send(sc, frame->mii_opcode, 2);
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vr_mii_send(sc, frame->mii_phyaddr, 5);
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vr_mii_send(sc, frame->mii_regaddr, 5);
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/* Idle bit. */
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SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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/* Turn off xmit. */
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SIO_CLR(VR_MIICMD_DIR);
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/* Check for ack */
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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/*
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* Now try reading data bits. If the ack failed, we still
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* need to clock through 16 cycles to keep the PHY(s) in sync.
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*/
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if (ack) {
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for(i = 0; i < 16; i++) {
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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}
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goto fail;
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}
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for (i = 0x8000; i; i >>= 1) {
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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if (!ack) {
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if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
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frame->mii_data |= i;
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DELAY(1);
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}
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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}
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fail:
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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if (ack)
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return (1);
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return (0);
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}
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#else
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{
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int i;
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@ -416,7 +286,6 @@ vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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return (0);
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}
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#endif
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/*
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@ -424,40 +293,6 @@ vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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*/
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static int
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vr_mii_writereg(const struct vr_softc *sc, const struct vr_mii_frame *frame)
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#ifdef VR_USESWSHIFT
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{
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CSR_WRITE_1(sc, VR_MIICMD, 0);
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VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
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/* Set up frame for TX. */
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frame->mii_stdelim = VR_MII_STARTDELIM;
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frame->mii_opcode = VR_MII_WRITEOP;
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frame->mii_turnaround = VR_MII_TURNAROUND;
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/* Turn on data output. */
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SIO_SET(VR_MIICMD_DIR);
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vr_mii_sync(sc);
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vr_mii_send(sc, frame->mii_stdelim, 2);
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vr_mii_send(sc, frame->mii_opcode, 2);
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vr_mii_send(sc, frame->mii_phyaddr, 5);
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vr_mii_send(sc, frame->mii_regaddr, 5);
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vr_mii_send(sc, frame->mii_turnaround, 2);
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vr_mii_send(sc, frame->mii_data, 16);
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/* Idle bit. */
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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/* Turn off xmit. */
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SIO_CLR(VR_MIICMD_DIR);
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return (0);
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}
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#else
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{
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int i;
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@ -479,7 +314,6 @@ vr_mii_writereg(const struct vr_softc *sc, const struct vr_mii_frame *frame)
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return (0);
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}
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#endif
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static int
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vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg)
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168
sys/pci/if_vr.c
168
sys/pci/if_vr.c
@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
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* multicast filter. Transmit and receive descriptors are similar
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* to the tulip.
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*
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* The Rhine has a serious flaw in its transmit DMA mechanism:
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* Some Rhine chips has a serious flaw in its transmit DMA mechanism:
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* transmit buffers must be longword aligned. Unfortunately,
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* FreeBSD doesn't guarantee that mbufs will be filled in starting
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* at longword boundaries, so we have to do a buffer copy before
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@ -103,8 +103,6 @@ MODULE_DEPEND(vr, miibus, 1, 1, 1);
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/* "device miibus" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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#undef VR_USESWSHIFT
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/*
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* Various supported device vendors/types, their names & quirks
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*/
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@ -191,10 +189,6 @@ static void vr_shutdown(device_t);
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static int vr_ifmedia_upd(struct ifnet *);
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static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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#ifdef VR_USESWSHIFT
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static void vr_mii_sync(struct vr_softc *);
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static void vr_mii_send(struct vr_softc *, uint32_t, int);
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#endif
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static int vr_mii_readreg(const struct vr_softc *, struct vr_mii_frame *);
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static int vr_mii_writereg(const struct vr_softc *, const struct vr_mii_frame *);
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static int vr_miibus_readreg(device_t, uint16_t, uint16_t);
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@ -266,136 +260,12 @@ DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0);
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#define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
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#define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
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#ifdef VR_USESWSHIFT
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#define CSR_READ_4(sc, reg) bus_read_4(sc->vr_res, reg)
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#define SIO_SET(x) CSR_WRITE_1(sc, VR_MIICMD, CSR_READ_1(sc, VR_MIICMD) | (x))
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#define SIO_CLR(x) CSR_WRITE_1(sc, VR_MIICMD, CSR_READ_1(sc, VR_MIICMD) & ~(x))
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/*
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* Sync the PHYs by setting data bit and strobing the clock 32 times.
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*/
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static void
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vr_mii_sync(struct vr_softc *sc)
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{
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register int i;
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SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
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for (i = 0; i < 32; i++) {
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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}
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}
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/*
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* Clock a series of bits through the MII.
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*/
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static void
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vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt)
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{
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int i;
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SIO_CLR(VR_MIICMD_CLK);
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for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
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if (bits & i) {
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SIO_SET(VR_MIICMD_DATAIN);
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} else {
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SIO_CLR(VR_MIICMD_DATAIN);
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}
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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}
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}
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#endif
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/*
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* Read an PHY register through the MII.
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*/
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static int
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vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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#ifdef VR_USESWSHIFT
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{
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int i, ack;
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/* Set up frame for RX. */
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frame->mii_stdelim = VR_MII_STARTDELIM;
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frame->mii_opcode = VR_MII_READOP;
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frame->mii_turnaround = 0;
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frame->mii_data = 0;
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CSR_WRITE_1(sc, VR_MIICMD, 0);
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VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
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/* Turn on data xmit. */
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SIO_SET(VR_MIICMD_DIR);
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vr_mii_sync(sc);
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/* Send command/address info. */
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vr_mii_send(sc, frame->mii_stdelim, 2);
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vr_mii_send(sc, frame->mii_opcode, 2);
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vr_mii_send(sc, frame->mii_phyaddr, 5);
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vr_mii_send(sc, frame->mii_regaddr, 5);
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/* Idle bit. */
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SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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/* Turn off xmit. */
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SIO_CLR(VR_MIICMD_DIR);
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/* Check for ack */
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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/*
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* Now try reading data bits. If the ack failed, we still
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* need to clock through 16 cycles to keep the PHY(s) in sync.
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*/
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if (ack) {
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for(i = 0; i < 16; i++) {
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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}
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goto fail;
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}
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for (i = 0x8000; i; i >>= 1) {
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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if (!ack) {
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if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
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frame->mii_data |= i;
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DELAY(1);
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}
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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}
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fail:
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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if (ack)
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return (1);
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return (0);
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}
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#else
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{
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int i;
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@ -416,7 +286,6 @@ vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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return (0);
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}
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#endif
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/*
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@ -424,40 +293,6 @@ vr_mii_readreg(const struct vr_softc *sc, struct vr_mii_frame *frame)
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*/
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static int
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vr_mii_writereg(const struct vr_softc *sc, const struct vr_mii_frame *frame)
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#ifdef VR_USESWSHIFT
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{
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CSR_WRITE_1(sc, VR_MIICMD, 0);
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VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
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/* Set up frame for TX. */
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frame->mii_stdelim = VR_MII_STARTDELIM;
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frame->mii_opcode = VR_MII_WRITEOP;
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frame->mii_turnaround = VR_MII_TURNAROUND;
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/* Turn on data output. */
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SIO_SET(VR_MIICMD_DIR);
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vr_mii_sync(sc);
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vr_mii_send(sc, frame->mii_stdelim, 2);
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vr_mii_send(sc, frame->mii_opcode, 2);
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vr_mii_send(sc, frame->mii_phyaddr, 5);
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vr_mii_send(sc, frame->mii_regaddr, 5);
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vr_mii_send(sc, frame->mii_turnaround, 2);
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vr_mii_send(sc, frame->mii_data, 16);
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/* Idle bit. */
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SIO_SET(VR_MIICMD_CLK);
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DELAY(1);
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SIO_CLR(VR_MIICMD_CLK);
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DELAY(1);
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/* Turn off xmit. */
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SIO_CLR(VR_MIICMD_DIR);
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return (0);
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}
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#else
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{
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int i;
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@ -479,7 +314,6 @@ vr_mii_writereg(const struct vr_softc *sc, const struct vr_mii_frame *frame)
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return (0);
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}
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#endif
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static int
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vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg)
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