Make interrupt dispatching MP safe. Use GPU interrupt bit in per-core
interrupt status register to process shared interrupts only if the bit is active and only on core to which they are routed. Reviewed by: imp, loos Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D3723
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@ -163,7 +163,9 @@ arm_get_next_irq(int last_irq)
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irq = 0;
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#ifdef SOC_BCM2836
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if ((ret = bcm2836_get_next_irq(irq)) >= 0)
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if ((ret = bcm2836_get_next_irq(irq)) < 0)
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return (-1);
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if (ret != BCM2836_GPU_IRQ)
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return (ret + BANK3_START);
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#endif
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@ -52,7 +52,7 @@ __FBSDID("$FreeBSD$");
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#define ARM_LOCAL_INT_TIMER(n) (0x40 + (n) * 4)
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#define ARM_LOCAL_INT_MAILBOX(n) (0x50 + (n) * 4)
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#define ARM_LOCAL_INT_PENDING(n) (0x60 + (n) * 4)
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#define INT_PENDING_MASK 0x01f
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#define INT_PENDING_MASK 0x011f
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#define MAILBOX0_IRQ 4
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#define MAILBOX0_IRQEN (1 << 0)
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@ -30,6 +30,8 @@
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#ifndef _BCM2815_BCM2836_H
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#define _BCM2815_BCM2836_H
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#define BCM2836_GPU_IRQ 8
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int bcm2836_get_next_irq(int);
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void bcm2836_mask_irq(uintptr_t);
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void bcm2836_unmask_irq(uintptr_t);
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