d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

MFH

Browse Source 
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Glen Barber 2016-02-10 04:20:39 +00:00
commit 30922917c8
1065 changed files with 129762 additions and 21062 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
Makefile
View File

@ -468,7 +468,8 @@ _THINNER=cat
_THINNER=xargs grep -L "^.NO_UNIVERSE" || true
.endif
KERNCONFS!= cd ${KERNSRCDIR}/${TARGET}/conf && \
find [A-Z0-9]*[A-Z0-9] -type f -maxdepth 0 \
find [[:upper:][:digit:]]*[[:upper:][:digit:]] \
-type f -maxdepth 0 \
! -name DEFAULTS ! -name NOTES | \
${_THINNER}
universe_kernconfs:

14
bin/dd/args.c
View File

@ -360,10 +360,10 @@ c_conv(const void *a, const void *b)
((const struct conv *)b)->name));
}
static uintmax_t
static intmax_t
postfix_to_mult(const char expr)
{
uintmax_t mult;
intmax_t mult;
mult = 0;
switch (expr) {
@ -407,8 +407,10 @@ postfix_to_mult(const char expr)
* 3) A positive decimal number followed by a 'k' or 'K' (mult by 1 << 10).
* 4) A positive decimal number followed by a 'm' or 'M' (mult by 1 << 20).
* 5) A positive decimal number followed by a 'g' or 'G' (mult by 1 << 30).
* 5) A positive decimal number followed by a 'w' or 'W' (mult by sizeof int).
* 6) Two or more positive decimal numbers (with/without [BbKkMmGgWw])
* 6) A positive decimal number followed by a 't' or 'T' (mult by 1 << 40).
* 7) A positive decimal number followed by a 'p' or 'P' (mult by 1 << 50).
* 8) A positive decimal number followed by a 'w' or 'W' (mult by sizeof int).
* 9) Two or more positive decimal numbers (with/without [BbKkMmGgWw])
* separated by 'x' or 'X' (also '*' for backwards compatibility),
* specifying the product of the indicated values.
*/
@ -419,7 +421,7 @@ get_num(const char *val)
char *expr;
errno = 0;
num = strtouq(val, &expr, 0);
num = strtoumax(val, &expr, 0);
if (errno != 0) /* Overflow or underflow. */
err(1, "%s", oper);
@ -469,7 +471,7 @@ get_off_t(const char *val)
char *expr;
errno = 0;
num = strtoq(val, &expr, 0);
num = strtoimax(val, &expr, 0);
if (errno != 0) /* Overflow or underflow. */
err(1, "%s", oper);

2
bin/pkill/pkill.c
View File

@ -71,7 +71,7 @@ __FBSDID("$FreeBSD$");
/* Ignore system-processes (if '-S' flag is not specified) and myself. */
#define PSKIP(kp) ((kp)->ki_pid == mypid || \
(!kthreads && ((kp)->ki_flag & P_KTHREAD) != 0))
(!kthreads && ((kp)->ki_flag & P_KPROC) != 0))
enum listtype {
LT_GENERIC,

2
bin/ps/ps.1
View File

@ -318,7 +318,7 @@ the include file
.Bl -column P_SINGLE_BOUNDARY 0x40000000
.It Dv "P_ADVLOCK" Ta No "0x00001" Ta "Process may hold a POSIX advisory lock"
.It Dv "P_CONTROLT" Ta No "0x00002" Ta "Has a controlling terminal"
.It Dv "P_KTHREAD" Ta No "0x00004" Ta "Kernel thread"
.It Dv "P_KPROC" Ta No "0x00004" Ta "Kernel process"
.It Dv "P_FOLLOWFORK" Ta No "0x00008" Ta "Attach debugger to new children"
.It Dv "P_PPWAIT" Ta No "0x00010" Ta "Parent is waiting for child to exec/exit"
.It Dv "P_PROFIL" Ta No "0x00020" Ta "Has started profiling"

2
etc/periodic/security/520.pfdenied
View File

@ -44,7 +44,7 @@ rc=0
if check_yesno_period security_status_pfdenied_enable
then
TMP=`mktemp -t security`
if pfctl -sr -v 2>/dev/null | nawk '{if (/^block/) {buf=$0; getline; gsub(" +"," ",$0); if ($5 > 0) print buf$0;} }' > ${TMP}; then
if pfctl -sr -v -z 2>/dev/null | nawk '{if (/^block/) {buf=$0; getline; gsub(" +"," ",$0); if ($5 > 0) print buf$0;} }' > ${TMP}; then
check_diff new_only pf ${TMP} "${host} pf denied packets:"
fi
rc=$?

1
lib/libmemstat/memstat_uma.c
View File

@ -29,7 +29,6 @@
#include <sys/param.h>
#include <sys/cpuset.h>
#include <sys/sysctl.h>
#include <sys/_task.h>
#include <vm/vm.h>
#include <vm/vm_page.h>

46
share/examples/jails/README
View File

@ -1,5 +1,49 @@
# $FreeBSD$
See under share/examples/netgraph for some examples of
Sample 1: jail.conf(5)
$ cp jib jng /usr/sbin/
$ cat jail.xxx.conf >> /etc/jail.conf
$ vi /etc/jail.conf
# NB: Customize root directory and bridge interface
$ sysrc jail_enable=YES
# NB: Assumes jail_list="" (meaning ``all jails in jail.conf'')
# NB: Assumes rc_conf_files="" (``below rc.conf(5) samples not used'')
$ service jail start
Sample 2: rc.conf(5)
$ cp jib jng /usr/sbin/
$ cp rc.conf.jails /etc/
$ vi /etc/rc.conf.jails
# NB: Customize root directory and bridge interface
$ sysrc rc_conf_files+=/etc/rc.conf.jails
# NB: Assumes /etc/jail.conf does not exist and jail_list=""
$ service jail start
Sample 3: Per-jail jail.conf(5)
$ cp jib jng /usr/sbin/
$ cp jail.xxx.conf /etc/
$ vi /etc/jail.xxx.conf
# NB: Customize root directory and bridge interface
$ sysrc jail_enable=YES
$ sysrc jail_list+=xxx
# NB: Assumes rc_conf_files=""
$ service jail start
Sample 4: Per-jail rc.conf(5)
$ cp jib jng /usr/sbin/
$ cp rcjail.xxx.conf /etc/
$ vi /etc/rcjail.xxx.conf
# NB: Customize root directory and bridge interface
$ sysrc jail_enable=YES
$ sysrc jail_list+=xxx
$ sysrc rc_conf_files+=/etc/rcjail.xxx.conf
# NB: Assumes neither /etc/jail.conf nor /etc/jail.xxx.conf exist
$ service jail start
For additional recipes, see share/examples/netgraph for
making and hooking together jails using netgraph as the
virtual networking fabric.

35
share/examples/jails/jail.xxx.conf Normal file
View File

@ -0,0 +1,35 @@
# $FreeBSD$
xxx {
host.hostname = "xxx.yyy"; # hostname
path = "/vm/xxx"; # root directory
exec.clean;
exec.system_user = "root";
exec.jail_user = "root";
#
# NB: Below 4-lines required
#
vnet;
# netgraph
vnet.interface = "ng0_xxx"; # vnet interface(s)
exec.prestart += "jng bridge xxx em0"; # bridge interface(s)
exec.poststop += "jng shutdown xxx"; # destroy interface(s)
# if_bridge
#vnet.interface = "e0b_xxx"; # vnet interface(s)
#exec.prestart += "jib addm xxx em0"; # bridge interface(s)
#exec.poststop += "jib destroy xxx"; # destroy interface(s)
# Standard recipe
exec.start += "/bin/sh /etc/rc";
exec.stop = "/bin/sh /etc/rc.shutdown";
exec.consolelog = "/var/log/jail_xxx_console.log";
mount.devfs; # mount devfs
# Optional (default off)
#devfs_ruleset = "11"; # rule to unhide bpf for DHCP
#allow.mount; # mount /etc/fstab.xxx
#allow.set_hostname = 1; # Allow hostname to change
#allow.sysvipc = 1; # Allow SysV Interprocess Comm.
}

30
share/examples/jails/jib
View File

@ -122,7 +122,7 @@
# add include $devfsrules_hide_all
# add include $devfsrules_unhide_basic
# add include $devfsrules_unhide_login
# add include $devfsrules_unhide_bpf
# add path 'bpf*' unhide
#
# And set ether devfs.ruleset="11" (jail.conf(5)) or
# jail_{name}_devfs_ruleset="11" (rc.conf(5)).
@ -198,7 +198,8 @@ jib_addm()
mustberoot_to_continue
local iface iface_devid eiface_devid_a eiface_devid_b
local iface iface_devid eiface_devid
local eiface_devid_a eiface_devid_b
local new num quad i=0
for iface in $*; do
@ -213,6 +214,7 @@ jib_addm()
new=$( ifconfig bridge create ) || return
ifconfig $new addm $iface || return
ifconfig $new name "$iface$bridge" || return
ifconfig "$iface$bridge" up || return
fi
# 4. Create a new interface to the bridge
@ -222,6 +224,8 @@ jib_addm()
# 5. Rename the new interface
ifconfig $new name "e${i}a_$name" || return
ifconfig ${new%a}b name "e${i}b_$name" || return
ifconfig "e${i}a_$name" up || return
ifconfig "e${i}b_$name" up || return
#
# 6. Set the MAC address of the new interface using a sensible
@ -248,32 +252,28 @@ jib_addm()
# unique value preventing conflict.
#
iface_devid=$( ifconfig $iface ether | awk '/ether/,$0=$2' )
eiface_devid_a=${iface_devid#??:??:??}
eiface_devid_b=${iface_devid#??:??:??}
eiface_devid=${iface_devid#??:??:??}
num=$( set -- `echo -n $name | sum` && echo $1 )
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=$quad$eiface_devid_a
eiface_devid_b=$quad$eiface_devid_b
eiface_devid=$quad$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=$quad$eiface_devid_a
eiface_devid_b=$quad$eiface_devid_b
eiface_devid=$quad$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=$quad:$eiface_devid_a
eiface_devid_b=$quad:$eiface_devid_b
eiface_devid=$quad:$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
@ -281,13 +281,13 @@ jib_addm()
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
case "$iface_devid" in
?2:*|?6:*)
eiface_devid_a=a:$quad$eiface_devid_a
eiface_devid_b=e:$quad$eiface_devid_b
?[Ee]:*)
eiface_devid_a=2:$quad$eiface_devid
eiface_devid_b=6:$quad$eiface_devid
;;
*)
eiface_devid_a=2:$quad$eiface_devid_a
eiface_devid_b=6:$quad$eiface_devid_b
eiface_devid_a=2:$quad$eiface_devid
eiface_devid_b=e:$quad$eiface_devid
esac
eval num=\$_${iface}_num
if [ "$num" ]; then

3
share/examples/jails/jng
View File

@ -122,7 +122,7 @@
# add include $devfsrules_hide_all
# add include $devfsrules_unhide_basic
# add include $devfsrules_unhide_login
# add include $devfsrules_unhide_bpf
# add path 'bpf*' unhide
#
# And set ether devfs.ruleset="11" (jail.conf(5)) or
# jail_{name}_devfs_ruleset="11" (rc.conf(5)).
@ -255,6 +255,7 @@ jng_bridge()
echo $2 ) || return
ngctl name "$iface$bridge:link$num" $eiface || return
ifconfig $new name $eiface || return
ifconfig $eiface up || return
#
# 6. Set the MAC address of the new interface using a sensible

76
share/examples/jails/rc.conf.jails Normal file
View File

@ -0,0 +1,76 @@
# $FreeBSD$
###############################################################################
############################# JAIL CONFIGURATIONS #############################
###############################################################################
jail_enable="YES"
jail_list="xxx"
#
# Global presets for all jails
#
jail_devfs_enable="YES" # mount devfs
# Optional (default off)
#jail_sysvipc_allow="YES" # Allow SysV Interprocess Comm.
#jail_set_hostname_allow="YES" # Allow hostname to change
#
# To allow dhclient(8) to work inside a jail, make sure the following appears
# in /etc/devfs.rules (which should be created if it doesn't exist):
#
# [devfsrules_jail=11]
# add include $devfsrules_hide_all
# add include $devfsrules_unhide_basic
# add include $devfsrules_unhide_login
# add path 'bpf*' unhide
#
############################################################ JAILS
# NETGRAPH TEMPLATE (copy/pate; then replace {name} with short name for jail)
#
# {name}
#
#jail_{name}_hostname="{name}.shxd.cx" # hostname
#jail_{name}_rootdir="/vm/{name}" # root directory
#jail_{name}_vnet_interfaces="ng0_{name}" # vnet interface(s)
#jail_{name}_exec_prestart0="jng bridge {name} em0" # bridge interface(s)
#jail_{name}_exec_poststop0="jng shutdown {name}" # destroy interface(s)
# Optional (default off)
#jail_{name}_devfs_ruleset="11" # rule to unhide bpf for DHCP
#jail_{name}_mount_enable="YES" # mount /etc/fstab.{name}
# IF_BRIDGE TEMPLATE (copy/pate; then replace {name} with short name for jail)
#
# {name}
#
#jail_{name}_hostname="{name}.shxd.cx" # hostname
#jail_{name}_rootdir="/vm/{name}" # root directory
#jail_{name}_vnet_interfaces="e0b_{name}" # vnet interface(s)
#jail_{name}_exec_prestart0="jib addm {name} em0" # bridge interface(s)
#jail_{name}_exec_poststop0="jib destroy {name}" # destroy interface(s)
# Optional (default off)
#jail_{name}_devfs_ruleset="11" # rule to unhide bpf for DHCP
#jail_{name}_mount_enable="YES" # mount /etc/fstab.{name}
#
# XXX
#
jail_xxx_hostname="xxx.yyy" # hostname
jail_xxx_rootdir="/vm/xxx" # root directory
# netgraph
jail_xxx_vnet_interface="ng0_xxx" # vnet interface(s)
jail_xxx_exec_prestart0="jng bridge xxx em0" # bridge interface(s)
jail_xxx_exec_poststop0="jng shutdown xxx" # destroy interface(s)
# if_bridge
#jail_xxx_vnet_interface="e0b_xxx" # vnet interface(s)
#jail_xxx_exec_prestart0="jib addm xxx em0" # bridge interface(s)
#jail_xxx_exec_poststop0="jib destroy xxx" # destroy interface(s)
# Optional (default off)
#jail_xxx_devfs_ruleset="11" # rule to unhide bpf for DHCP
#jail_xxx_mount_enable="YES" # mount /etc/fstab.xxx
################################################################################
# END
################################################################################

25
share/examples/jails/rcjail.xxx.conf Normal file
View File

@ -0,0 +1,25 @@
# $FreeBSD$
jail_xxx_hostname="xxx.yyy" # hostname
jail_xxx_rootdir="/vm/xxx" # root directory
#
# NB: Below 3 lines required
#
# netgraph
jail_xxx_vnet_interface="ng0_xxx" # vnet interface(s)
jail_xxx_exec_prestart0="jng bridge xxx em0" # bridge interface(s)
jail_xxx_exec_poststop0="jng shutdown xxx" # destroy interface(s)
# if_bridge
#jail_xxx_vnet_interface="e0b_xxx" # vnet interface(s)
#jail_xxx_exec_prestart0="jib addm xxx em0" # bridge interface(s)
#jail_xxx_exec_poststop0="jib destroy xxx" # destroy interface(s)
# Standard recipe
jail_xxx_devfs_enable="YES" # mount devfs
# Optional (default off)
#jail_xxx_devfs_ruleset="11" # rule to unhide bpf for DHCP
#jail_xxx_mount_enable="YES" # mount /etc/fstab.xxx
#jail_xxx_set_hostname_allow="YES" # Allow hostname to change
#jail_xxx_sysvipc_allow="YES" # Allow SysV Interprocess Comm.

1
sys/amd64/amd64/uma_machdep.c
View File

@ -32,7 +32,6 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/systm.h>
#include <sys/taskqueue.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>

2
sys/arm/allwinner/allwinner_machdep.h
View File

@ -2,8 +2,6 @@
* Copyright (c) 2015 Emmanuel Vadot <manu@bidouilliste.com>
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:

1
sys/arm/arm/vm_machdep.c
View File

@ -54,7 +54,6 @@ __FBSDID("$FreeBSD$");
#include <sys/sysctl.h>
#include <sys/sysent.h>
#include <sys/unistd.h>
#include <sys/taskqueue.h>
#include <machine/acle-compat.h>
#include <machine/cpu.h>

6
sys/arm64/arm64/db_disasm.c
View File

@ -41,9 +41,9 @@ static void db_disasm_printaddr(vm_offset_t);
/* Glue code to interface db_disasm to the generic ARM disassembler */
static const struct disasm_interface db_disasm_interface = {
db_disasm_read_word,
db_disasm_printaddr,
db_printf
.di_readword = db_disasm_read_word,
.di_printaddr = db_disasm_printaddr,
.di_printf = db_printf,
};
static u_int

12
sys/arm64/arm64/pmap.c
View File

@ -3074,7 +3074,11 @@ pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
l1p = pmap_l1(pmap, addr);
if (l1p == NULL) /* No l1 */
goto done;
l1 = pmap_load(l1p);
if ((l1 & ATTR_DESCR_MASK) == L1_INVAL)
goto done;
if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) {
pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET);
managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
@ -3089,7 +3093,11 @@ pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
l2p = pmap_l1_to_l2(l1p, addr);
if (l2p == NULL) /* No l2 */
goto done;
l2 = pmap_load(l2p);
if ((l2 & ATTR_DESCR_MASK) == L2_INVAL)
goto done;
if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) {
pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET);
managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;
@ -3104,7 +3112,11 @@ pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
l3p = pmap_l2_to_l3(l2p, addr);
if (l3p == NULL) /* No l3 */
goto done;
l3 = pmap_load(l2p);
if ((l3 & ATTR_DESCR_MASK) == L3_INVAL)
goto done;
if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) {
pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET);
managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED;

1
sys/arm64/arm64/uma_machdep.c
View File

@ -32,7 +32,6 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/systm.h>
#include <sys/taskqueue.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>

1
sys/arm64/arm64/vm_machdep.c
View File

@ -35,7 +35,6 @@ __FBSDID("$FreeBSD$");
#include <sys/sf_buf.h>
#include <sys/signal.h>
#include <sys/unistd.h>
#include <sys/taskqueue.h>
#include <vm/vm.h>
#include <vm/vm_page.h>

7
sys/boot/common/load_elf.c
View File

@ -353,7 +353,7 @@ __elfN(loadimage)(struct preloaded_file *fp, elf_file_t ef, u_int64_t off)
#endif
} else
off = 0;
#elif defined(__arm__)
#elif defined(__arm__) && !defined(EFI)
/*
* The elf headers in arm kernels specify virtual addresses in all
* header fields, even the ones that should be physical addresses.
@ -364,6 +364,11 @@ __elfN(loadimage)(struct preloaded_file *fp, elf_file_t ef, u_int64_t off)
* translates it to a physical address. We do the va->pa conversion on
* the entry point address in the header now, so that later we can
* launch the kernel by just jumping to that address.
*
* When booting from UEFI the copyin and copyout functions handle
* adjusting the location relative to the first virtual address.
* Because of this there is no need to adjust the offset or entry
* point address as these will both be handled by the efi code.
*/
off -= ehdr->e_entry & ~PAGE_MASK;
ehdr->e_entry += off;

2
sys/compat/ndis/ntoskrnl_var.h
View File

@ -337,7 +337,7 @@ typedef struct nt_dispatch_header nt_dispatch_header;
#define SYNC_LEVEL_MP (IPI_LEVEL - 1)
#define AT_PASSIVE_LEVEL(td) \
((td)->td_proc->p_flag & P_KTHREAD == FALSE)
((td)->td_proc->p_flag & P_KPROC == FALSE)
#define AT_DISPATCH_LEVEL(td) \
((td)->td_base_pri == PI_REALTIME)

2
sys/dev/hwpmc/hwpmc_mod.c
View File

@ -1009,7 +1009,7 @@ pmc_attach_one_process(struct proc *p, struct pmc *pm)
/* issue an attach event to a configured log file */
if (pm->pm_owner->po_flags & PMC_PO_OWNS_LOGFILE) {
if (p->p_flag & P_KTHREAD) {
if (p->p_flag & P_KPROC) {
fullpath = kernelname;
freepath = NULL;
} else {

59
sys/dev/ofw/ofw_bus_subr.c
View File

@ -629,13 +629,16 @@ ofw_bus_find_child_device_by_phandle(device_t bus, phandle_t node)
* node - consumers device node
* list_name - name of parsed list - "clocks"
* cells_name - name of size property - "#clock-cells"
* idx - the index of the requested list entry, or, if -1, an indication
* to return the number of entries in the parsed list.
* Output arguments:
* producer - handle of producer
* ncells - number of cells in result
* ncells - number of cells in result or the number of items in the list when
* idx == -1.
* cells - array of decoded cells
*/
int
ofw_bus_parse_xref_list_alloc(phandle_t node, const char *list_name,
static int
ofw_bus_parse_xref_list_internal(phandle_t node, const char *list_name,
const char *cells_name, int idx, phandle_t *producer, int *ncells,
pcell_t **cells)
{
@ -649,7 +652,7 @@ ofw_bus_parse_xref_list_alloc(phandle_t node, const char *list_name,
(void **)&elems);
if (nelems <= 0)
return (ENOENT);
rv = ENOENT;
rv = (idx == -1) ? 0 : ENOENT;
for (i = 0, cnt = 0; i < nelems; i += pcells, cnt++) {
pnode = elems[i++];
if (OF_getencprop(OF_node_from_xref(pnode),
@ -678,9 +681,57 @@ ofw_bus_parse_xref_list_alloc(phandle_t node, const char *list_name,
}
if (elems != NULL)
free(elems, M_OFWPROP);
if (idx == -1 && rv == 0)
*ncells = cnt;
return (rv);
}
/*
* Parse property that contain list of xrefs and values
* (like standard "clocks" and "resets" properties)
* Input arguments:
* node - consumers device node
* list_name - name of parsed list - "clocks"
* cells_name - name of size property - "#clock-cells"
* idx - the index of the requested list entry (>= 0)
* Output arguments:
* producer - handle of producer
* ncells - number of cells in result
* cells - array of decoded cells
*/
int
ofw_bus_parse_xref_list_alloc(phandle_t node, const char *list_name,
const char *cells_name, int idx, phandle_t *producer, int *ncells,
pcell_t **cells)
{
KASSERT(idx >= 0,
("ofw_bus_parse_xref_list_alloc: negative index supplied"));
return (ofw_bus_parse_xref_list_internal(node, list_name, cells_name,
idx, producer, ncells, cells));
}
/*
* Parse property that contain list of xrefs and values
* (like standard "clocks" and "resets" properties)
* and determine the number of items in the list
* Input arguments:
* node - consumers device node
* list_name - name of parsed list - "clocks"
* cells_name - name of size property - "#clock-cells"
* Output arguments:
* count - number of items in list
*/
int
ofw_bus_parse_xref_list_get_length(phandle_t node, const char *list_name,
const char *cells_name, int *count)
{
return (ofw_bus_parse_xref_list_internal(node, list_name, cells_name,
-1, NULL, count, NULL));
}
/*
* Find index of string in string list property (case sensitive).
*/

2
sys/dev/ofw/ofw_bus_subr.h
View File

@ -118,6 +118,8 @@ device_t ofw_bus_find_child_device_by_phandle(device_t bus, phandle_t node);
int ofw_bus_parse_xref_list_alloc(phandle_t node, const char *list_name,
const char *cells_name, int idx, phandle_t *producer, int *ncells,
pcell_t **cells);
int ofw_bus_parse_xref_list_get_length(phandle_t node, const char *list_name,
const char *cells_name, int *count);
int ofw_bus_find_string_index(phandle_t node, const char *list_name,
const char *name, int *idx);
int ofw_bus_string_list_to_array(phandle_t node, const char *list_name,

440
sys/dev/sound/pcm/sndstat.c
View File

@ -37,77 +37,51 @@
SND_DECLARE_FILE("$FreeBSD$");
#define SS_TYPE_MODULE 0
#define SS_TYPE_FIRST 1
#define SS_TYPE_PCM 1
#define SS_TYPE_MIDI 2
#define SS_TYPE_SEQUENCER 3
#define SS_TYPE_LAST 3
static d_open_t sndstat_open;
static d_close_t sndstat_close;
static void sndstat_close(void *);
static d_read_t sndstat_read;
static d_write_t sndstat_write;
static struct cdevsw sndstat_cdevsw = {
.d_version = D_VERSION,
.d_open = sndstat_open,
.d_close = sndstat_close,
.d_read = sndstat_read,
.d_write = sndstat_write,
.d_name = "sndstat",
.d_flags = D_TRACKCLOSE,
};
struct sndstat_entry {
SLIST_ENTRY(sndstat_entry) link;
TAILQ_ENTRY(sndstat_entry) link;
device_t dev;
char *str;
sndstat_handler handler;
int type, unit;
};
struct sndstat_file {
TAILQ_ENTRY(sndstat_file) entry;
struct sbuf sbuf;
int out_offset;
int in_offset;
};
static struct sx sndstat_lock;
static struct sbuf sndstat_sbuf;
static struct cdev *sndstat_dev = NULL;
static int sndstat_bufptr = -1;
static int sndstat_maxunit = -1;
static int sndstat_files = 0;
static struct cdev *sndstat_dev;
#define SNDSTAT_PID(x) ((pid_t)((intptr_t)((x)->si_drv1)))
#define SNDSTAT_PID_SET(x, y) (x)->si_drv1 = (void *)((intptr_t)(y))
#define SNDSTAT_FLUSH() do { \
if (sndstat_bufptr != -1) { \
sbuf_delete(&sndstat_sbuf); \
sndstat_bufptr = -1; \
} \
} while (0)
#define SNDSTAT_LOCK() sx_xlock(&sndstat_lock)
#define SNDSTAT_UNLOCK() sx_xunlock(&sndstat_lock)
static SLIST_HEAD(, sndstat_entry) sndstat_devlist = SLIST_HEAD_INITIALIZER(sndstat_devlist);
static TAILQ_HEAD(, sndstat_entry) sndstat_devlist = TAILQ_HEAD_INITIALIZER(sndstat_devlist);
static TAILQ_HEAD(, sndstat_file) sndstat_filelist = TAILQ_HEAD_INITIALIZER(sndstat_filelist);
int snd_verbose = 0;
#ifdef SND_DEBUG
static int
sysctl_hw_snd_sndstat_pid(SYSCTL_HANDLER_ARGS)
{
int err, val;
if (sndstat_dev == NULL)
return (EINVAL);
sx_xlock(&sndstat_lock);
val = (int)SNDSTAT_PID(sndstat_dev);
err = sysctl_handle_int(oidp, &val, 0, req);
if (err == 0 && req->newptr != NULL && val == 0) {
SNDSTAT_FLUSH();
SNDSTAT_PID_SET(sndstat_dev, 0);
}
sx_unlock(&sndstat_lock);
return (err);
}
SYSCTL_PROC(_hw_snd, OID_AUTO, sndstat_pid, CTLTYPE_INT | CTLFLAG_RWTUN,
0, sizeof(int), sysctl_hw_snd_sndstat_pid, "I", "sndstat busy pid");
#endif
static int sndstat_prepare(struct sbuf *s);
static int sndstat_prepare(struct sndstat_file *);
static int
sysctl_hw_sndverbose(SYSCTL_HANDLER_ARGS)
@ -122,7 +96,7 @@ sysctl_hw_sndverbose(SYSCTL_HANDLER_ARGS)
else
snd_verbose = verbose;
}
return error;
return (error);
}
SYSCTL_PROC(_hw_snd, OID_AUTO, verbose, CTLTYPE_INT | CTLFLAG_RWTUN,
0, sizeof(int), sysctl_hw_sndverbose, "I", "verbosity level");
@ -130,128 +104,135 @@ SYSCTL_PROC(_hw_snd, OID_AUTO, verbose, CTLTYPE_INT | CTLFLAG_RWTUN,
static int
sndstat_open(struct cdev *i_dev, int flags, int mode, struct thread *td)
{
if (sndstat_dev == NULL || i_dev != sndstat_dev)
return EBADF;
struct sndstat_file *pf;
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(i_dev) != 0) {
sx_unlock(&sndstat_lock);
return EBUSY;
pf = malloc(sizeof(*pf), M_DEVBUF, M_WAITOK | M_ZERO);
SNDSTAT_LOCK();
if (sbuf_new(&pf->sbuf, NULL, 4096, SBUF_AUTOEXTEND) == NULL) {
SNDSTAT_UNLOCK();
free(pf, M_DEVBUF);
return (ENOMEM);
}
SNDSTAT_PID_SET(i_dev, td->td_proc->p_pid);
if (sbuf_new(&sndstat_sbuf, NULL, 4096, SBUF_AUTOEXTEND) == NULL) {
SNDSTAT_PID_SET(i_dev, 0);
sx_unlock(&sndstat_lock);
return ENXIO;
}
sndstat_bufptr = 0;
sx_unlock(&sndstat_lock);
return 0;
TAILQ_INSERT_TAIL(&sndstat_filelist, pf, entry);
SNDSTAT_UNLOCK();
devfs_set_cdevpriv(pf, &sndstat_close);
return (0);
}
static int
sndstat_close(struct cdev *i_dev, int flags, int mode, struct thread *td)
static void
sndstat_close(void *sndstat_file)
{
if (sndstat_dev == NULL || i_dev != sndstat_dev)
return EBADF;
struct sndstat_file *pf = (struct sndstat_file *)sndstat_file;
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(i_dev) == 0) {
sx_unlock(&sndstat_lock);
return EBADF;
}
SNDSTAT_LOCK();
sbuf_delete(&pf->sbuf);
TAILQ_REMOVE(&sndstat_filelist, pf, entry);
SNDSTAT_UNLOCK();
SNDSTAT_FLUSH();
SNDSTAT_PID_SET(i_dev, 0);
sx_unlock(&sndstat_lock);
return 0;
free(pf, M_DEVBUF);
}
static int
sndstat_read(struct cdev *i_dev, struct uio *buf, int flag)
{
int l, err;
struct sndstat_file *pf;
int err;
int len;
if (sndstat_dev == NULL || i_dev != sndstat_dev)
return EBADF;
err = devfs_get_cdevpriv((void **)&pf);
if (err != 0)
return (err);
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(i_dev) != buf->uio_td->td_proc->p_pid ||
sndstat_bufptr == -1) {
sx_unlock(&sndstat_lock);
return EBADF;
}
/* skip zero-length reads */
if (buf->uio_resid == 0)
return (0);
if (sndstat_bufptr == 0) {
err = (sndstat_prepare(&sndstat_sbuf) > 0) ? 0 : ENOMEM;
if (err) {
SNDSTAT_FLUSH();
sx_unlock(&sndstat_lock);
return err;
SNDSTAT_LOCK();
if (pf->out_offset != 0) {
/* don't allow both reading and writing */
err = EINVAL;
goto done;
} else if (pf->in_offset == 0) {
err = sndstat_prepare(pf);
if (err <= 0) {
err = ENOMEM;
goto done;
}
}
len = sbuf_len(&pf->sbuf) - pf->in_offset;
if (len > buf->uio_resid)
len = buf->uio_resid;
if (len > 0)
err = uiomove(sbuf_data(&pf->sbuf) + pf->in_offset, len, buf);
pf->in_offset += len;
done:
SNDSTAT_UNLOCK();
return (err);
}
l = min(buf->uio_resid, sbuf_len(&sndstat_sbuf) - sndstat_bufptr);
err = (l > 0)? uiomove(sbuf_data(&sndstat_sbuf) + sndstat_bufptr, l, buf) : 0;
sndstat_bufptr += l;
sx_unlock(&sndstat_lock);
static int
sndstat_write(struct cdev *i_dev, struct uio *buf, int flag)
{
struct sndstat_file *pf;
uint8_t temp[64];
int err;
int len;
return err;
err = devfs_get_cdevpriv((void **)&pf);
if (err != 0)
return (err);
/* skip zero-length writes */
if (buf->uio_resid == 0)
return (0);
/* don't allow writing more than 64Kbytes */
if (buf->uio_resid > 65536)
return (ENOMEM);
SNDSTAT_LOCK();
if (pf->in_offset != 0) {
/* don't allow both reading and writing */
err = EINVAL;
} else {
/* only remember the last write - allows for updates */
sbuf_clear(&pf->sbuf);
while (1) {
len = sizeof(temp);
if (len > buf->uio_resid)
len = buf->uio_resid;
if (len > 0) {
err = uiomove(temp, len, buf);
if (err)
break;
} else {
break;
}
if (sbuf_bcat(&pf->sbuf, temp, len) < 0) {
err = ENOMEM;
break;
}
}
sbuf_finish(&pf->sbuf);
if (err == 0)
pf->out_offset = sbuf_len(&pf->sbuf);
else
pf->out_offset = 0;
}
SNDSTAT_UNLOCK();
return (err);
}
/************************************************************************/
static struct sndstat_entry *
sndstat_find(int type, int unit)
{
struct sndstat_entry *ent;
SLIST_FOREACH(ent, &sndstat_devlist, link) {
if (ent->type == type && ent->unit == unit)
return ent;
}
return NULL;
}
int
sndstat_acquire(struct thread *td)
{
if (sndstat_dev == NULL)
return EBADF;
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(sndstat_dev) != 0) {
sx_unlock(&sndstat_lock);
return EBUSY;
}
SNDSTAT_PID_SET(sndstat_dev, td->td_proc->p_pid);
sx_unlock(&sndstat_lock);
return 0;
}
int
sndstat_release(struct thread *td)
{
if (sndstat_dev == NULL)
return EBADF;
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(sndstat_dev) != td->td_proc->p_pid) {
sx_unlock(&sndstat_lock);
return EBADF;
}
SNDSTAT_PID_SET(sndstat_dev, 0);
sx_unlock(&sndstat_lock);
return 0;
}
int
sndstat_register(device_t dev, char *str, sndstat_handler handler)
{
struct sndstat_entry *ent;
struct sndstat_entry *pre;
const char *devtype;
int type, unit;
@ -265,7 +246,7 @@ sndstat_register(device_t dev, char *str, sndstat_handler handler)
else if (!strcmp(devtype, "sequencer"))
type = SS_TYPE_SEQUENCER;
else
return EINVAL;
return (EINVAL);
} else {
type = SS_TYPE_MODULE;
unit = -1;
@ -278,71 +259,87 @@ sndstat_register(device_t dev, char *str, sndstat_handler handler)
ent->unit = unit;
ent->handler = handler;
sx_xlock(&sndstat_lock);
SLIST_INSERT_HEAD(&sndstat_devlist, ent, link);
if (type == SS_TYPE_MODULE)
sndstat_files++;
sndstat_maxunit = (unit > sndstat_maxunit)? unit : sndstat_maxunit;
sx_unlock(&sndstat_lock);
SNDSTAT_LOCK();
/* sorted list insertion */
TAILQ_FOREACH(pre, &sndstat_devlist, link) {
if (pre->unit > unit)
break;
else if (pre->unit < unit)
continue;
if (pre->type > type)
break;
else if (pre->type < unit)
continue;
}
if (pre == NULL) {
TAILQ_INSERT_TAIL(&sndstat_devlist, ent, link);
} else {
TAILQ_INSERT_BEFORE(pre, ent, link);
}
SNDSTAT_UNLOCK();
return 0;
return (0);
}
int
sndstat_registerfile(char *str)
{
return sndstat_register(NULL, str, NULL);
return (sndstat_register(NULL, str, NULL));
}
int
sndstat_unregister(device_t dev)
{
struct sndstat_entry *ent;
int error = ENXIO;
sx_xlock(&sndstat_lock);
SLIST_FOREACH(ent, &sndstat_devlist, link) {
SNDSTAT_LOCK();
TAILQ_FOREACH(ent, &sndstat_devlist, link) {
if (ent->dev == dev) {
SLIST_REMOVE(&sndstat_devlist, ent, sndstat_entry, link);
sx_unlock(&sndstat_lock);
TAILQ_REMOVE(&sndstat_devlist, ent, link);
free(ent, M_DEVBUF);
return 0;
error = 0;
break;
}
}
sx_unlock(&sndstat_lock);
SNDSTAT_UNLOCK();
return ENXIO;
return (error);
}
int
sndstat_unregisterfile(char *str)
{
struct sndstat_entry *ent;
int error = ENXIO;
sx_xlock(&sndstat_lock);
SLIST_FOREACH(ent, &sndstat_devlist, link) {
SNDSTAT_LOCK();
TAILQ_FOREACH(ent, &sndstat_devlist, link) {
if (ent->dev == NULL && ent->str == str) {
SLIST_REMOVE(&sndstat_devlist, ent, sndstat_entry, link);
sndstat_files--;
sx_unlock(&sndstat_lock);
TAILQ_REMOVE(&sndstat_devlist, ent, link);
free(ent, M_DEVBUF);
return 0;
error = 0;
break;
}
}
sx_unlock(&sndstat_lock);
SNDSTAT_UNLOCK();
return ENXIO;
return (error);
}
/************************************************************************/
static int
sndstat_prepare(struct sbuf *s)
sndstat_prepare(struct sndstat_file *pf_self)
{
struct sbuf *s = &pf_self->sbuf;
struct sndstat_entry *ent;
struct snddev_info *d;
int i, j;
struct sndstat_file *pf;
int k;
/* make sure buffer is reset */
sbuf_clear(s);
if (snd_verbose > 0) {
sbuf_printf(s, "FreeBSD Audio Driver (%ubit %d/%s)\n",
@ -350,96 +347,79 @@ sndstat_prepare(struct sbuf *s)
MACHINE_ARCH);
}
if (SLIST_EMPTY(&sndstat_devlist)) {
sbuf_printf(s, "No devices installed.\n");
sbuf_finish(s);
return sbuf_len(s);
}
sbuf_printf(s, "Installed devices:\n");
for (i = 0; i <= sndstat_maxunit; i++) {
for (j = SS_TYPE_FIRST; j <= SS_TYPE_LAST; j++) {
ent = sndstat_find(j, i);
if (!ent)
/* generate list of installed devices */
k = 0;
TAILQ_FOREACH(ent, &sndstat_devlist, link) {
if (ent->dev == NULL)
continue;
d = device_get_softc(ent->dev);
if (!PCM_REGISTERED(d))
continue;
/* XXX Need Giant magic entry ??? */
PCM_ACQUIRE_QUICK(d);
if (!k++)
sbuf_printf(s, "Installed devices:\n");
sbuf_printf(s, "%s:", device_get_nameunit(ent->dev));
sbuf_printf(s, " <%s>", device_get_desc(ent->dev));
if (snd_verbose > 0)
sbuf_printf(s, " %s", ent->str);
if (ent->handler)
if (ent->handler) {
/* XXX Need Giant magic entry ??? */
PCM_ACQUIRE_QUICK(d);
ent->handler(s, ent->dev, snd_verbose);
sbuf_printf(s, "\n");
PCM_RELEASE_QUICK(d);
}
sbuf_printf(s, "\n");
}
if (k == 0)
sbuf_printf(s, "No devices installed.\n");
if (snd_verbose >= 3 && sndstat_files > 0) {
/* append any input from userspace */
k = 0;
TAILQ_FOREACH(pf, &sndstat_filelist, entry) {
if (pf == pf_self)
continue;
if (pf->out_offset == 0)
continue;
if (!k++)
sbuf_printf(s, "Installed devices from userspace:\n");
sbuf_bcat(s, sbuf_data(&pf->sbuf),
sbuf_len(&pf->sbuf));
}
if (k == 0)
sbuf_printf(s, "No devices installed from userspace.\n");
/* append any file versions */
if (snd_verbose >= 3) {
k = 0;
TAILQ_FOREACH(ent, &sndstat_devlist, link) {
if (ent->dev == NULL && ent->str != NULL) {
if (!k++)
sbuf_printf(s, "\nFile Versions:\n");
SLIST_FOREACH(ent, &sndstat_devlist, link) {
if (ent->dev == NULL && ent->str != NULL)
sbuf_printf(s, "%s\n", ent->str);
}
}
sbuf_finish(s);
return sbuf_len(s);
}
static int
sndstat_init(void)
{
if (sndstat_dev != NULL)
return EINVAL;
sx_init(&sndstat_lock, "sndstat lock");
sndstat_dev = make_dev(&sndstat_cdevsw, SND_DEV_STATUS,
UID_ROOT, GID_WHEEL, 0444, "sndstat");
return 0;
}
static int
sndstat_uninit(void)
{
if (sndstat_dev == NULL)
return EINVAL;
sx_xlock(&sndstat_lock);
if (SNDSTAT_PID(sndstat_dev) != curthread->td_proc->p_pid) {
sx_unlock(&sndstat_lock);
return EBUSY;
if (k == 0)
sbuf_printf(s, "\nNo file versions.\n");
}
/* XXXPHO: use destroy_dev_sched() */
destroy_dev(sndstat_dev);
sndstat_dev = NULL;
SNDSTAT_FLUSH();
sx_unlock(&sndstat_lock);
sx_destroy(&sndstat_lock);
return 0;
sbuf_finish(s);
return (sbuf_len(s));
}
static void
sndstat_sysinit(void *p)
{
sndstat_init();
sx_init(&sndstat_lock, "sndstat lock");
sndstat_dev = make_dev(&sndstat_cdevsw, SND_DEV_STATUS,
UID_ROOT, GID_WHEEL, 0644, "sndstat");
}
SYSINIT(sndstat_sysinit, SI_SUB_DRIVERS, SI_ORDER_FIRST, sndstat_sysinit, NULL);
static void
sndstat_sysuninit(void *p)
{
int error;
error = sndstat_uninit();
KASSERT(error == 0, ("%s: error = %d", __func__, error));
if (sndstat_dev != NULL) {
/* destroy_dev() will wait for all references to go away */
destroy_dev(sndstat_dev);
}
sx_destroy(&sndstat_lock);
}
SYSINIT(sndstat_sysinit, SI_SUB_DRIVERS, SI_ORDER_FIRST, sndstat_sysinit, NULL);
SYSUNINIT(sndstat_sysuninit, SI_SUB_DRIVERS, SI_ORDER_FIRST, sndstat_sysuninit, NULL);

17
sys/dev/sound/pcm/sound.c
View File

@ -1153,18 +1153,12 @@ pcm_unregister(device_t dev)
return (0);
}
if (sndstat_acquire(td) != 0) {
device_printf(dev, "unregister: sndstat busy\n");
return (EBUSY);
}
PCM_LOCK(d);
PCM_WAIT(d);
if (d->inprog != 0) {
device_printf(dev, "unregister: operation in progress\n");
PCM_UNLOCK(d);
sndstat_release(td);
return (EBUSY);
}
@ -1179,7 +1173,6 @@ pcm_unregister(device_t dev)
ch->name, ch->pid);
CHN_UNLOCK(ch);
PCM_RELEASE_QUICK(d);
sndstat_release(td);
return (EBUSY);
}
CHN_UNLOCK(ch);
@ -1189,7 +1182,6 @@ pcm_unregister(device_t dev)
if (snd_clone_busy(d->clones) != 0) {
device_printf(dev, "unregister: clone busy\n");
PCM_RELEASE_QUICK(d);
sndstat_release(td);
return (EBUSY);
} else {
PCM_LOCK(d);
@ -1205,10 +1197,12 @@ pcm_unregister(device_t dev)
(void)snd_clone_enable(d->clones);
PCM_RELEASE(d);
PCM_UNLOCK(d);
sndstat_release(td);
return (EBUSY);
}
/* remove /dev/sndstat entry first */
sndstat_unregister(dev);
PCM_LOCK(d);
d->flags |= SD_F_DYING;
d->flags &= ~SD_F_REGISTERED;
@ -1242,8 +1236,6 @@ pcm_unregister(device_t dev)
cv_destroy(&d->cv);
PCM_UNLOCK(d);
snd_mtxfree(d->lock);
sndstat_unregister(dev);
sndstat_release(td);
if (snd_unit == device_get_unit(dev)) {
snd_unit = pcm_best_unit(-1);
@ -1415,9 +1407,6 @@ sound_modevent(module_t mod, int type, void *data)
pcmsg_unrhdr = new_unrhdr(1, INT_MAX, NULL);
break;
case MOD_UNLOAD:
ret = sndstat_acquire(curthread);
if (ret != 0)
break;
if (pcmsg_unrhdr != NULL) {
delete_unrhdr(pcmsg_unrhdr);
pcmsg_unrhdr = NULL;

2
sys/dev/sound/pcm/sound.h
View File

@ -350,8 +350,6 @@ void snd_mtxassert(void *m);
#define snd_mtxunlock(m) mtx_unlock(m)
typedef int (*sndstat_handler)(struct sbuf *s, device_t dev, int verbose);
int sndstat_acquire(struct thread *td);
int sndstat_release(struct thread *td);
int sndstat_register(device_t dev, char *str, sndstat_handler handler);
int sndstat_registerfile(char *str);
int sndstat_unregister(device_t dev);

13
sys/gnu/dts/arm/alphascale-asm9260-devkit.dts Normal file
View File

@ -0,0 +1,13 @@
/*
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
*
* Licensed under the X11 license or the GPL v2 (or later)
*/
/dts-v1/;
#include "alphascale-asm9260.dtsi"
/ {
model = "Alphascale asm9260 Development Kit";
compatible = "alphascale,asm9260devkit", "alphascale,asm9260";
};

63
sys/gnu/dts/arm/alphascale-asm9260.dtsi Normal file
View File

@ -0,0 +1,63 @@
/*
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
*
* Licensed under the X11 license or the GPL v2 (or later)
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/alphascale,asm9260.h>
/ {
interrupt-parent = <&icoll>;
memory {
device_type = "memory";
reg = <0x20000000 0x2000000>;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm926ej-s";
device_type = "cpu";
clocks = <&acc CLKID_SYS_CPU>;
};
};
osc24m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-accuracy = <30000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
acc: clock-controller@80040000 {
compatible = "alphascale,asm9260-clock-controller";
#clock-cells = <1>;
clocks = <&osc24m>;
reg = <0x80040000 0x204>;
};
icoll: interrupt-controller@80054000 {
compatible = "alphascale,asm9260-icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80054000 0x200>;
};
timer0: timer@80088000 {
compatible = "alphascale,asm9260-timer";
reg = <0x80088000 0x4000>;
clocks = <&acc CLKID_AHB_TIMER0>;
interrupts = <29>;
};
};
};

35
sys/gnu/dts/arm/alpine-db.dts Normal file
View File

@ -0,0 +1,35 @@
/*
* Copyright 2015 Annapurna Labs Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* Alternatively, redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/dts-v1/;
#include "alpine.dtsi"
/ {
model = "Annapurna Labs Alpine Dev Board";
/* no need for anything outside SOC */
};

160
sys/gnu/dts/arm/alpine.dtsi Normal file
View File

@ -0,0 +1,160 @@
/*
* Copyright 2015 Annapurna Labs Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* Alternatively, redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton64.dtsi"
/ {
/* SOC compatibility */
compatible = "al,alpine";
/* CPU Configuration */
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "al,alpine-smp";
cpu@0 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <0>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@1 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <1>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@2 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <2>;
clock-frequency = <0>; /* Filled by loader */
};
cpu@3 {
compatible = "arm,cortex-a15";
device_type = "cpu";
reg = <3>;
clock-frequency = <0>; /* Filled by loader */
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
arch-timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
interrupts =
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <0>; /* Filled by loader */
};
/* Interrupt Controller */
gic: gic@fb001000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
#size-cells = <0>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfb001000 0x0 0x1000>,
<0x0 0xfb002000 0x0 0x2000>,
<0x0 0xfb004000 0x0 0x1000>,
<0x0 0xfb006000 0x0 0x2000>;
interrupts =
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
/* CPU Resume registers */
cpu-resume@fbff5ec0 {
compatible = "al,alpine-cpu-resume";
reg = <0x0 0xfbff5ec0 0x0 0x30>;
};
/* North Bridge Service Registers */
sysfabric-service@fb070000 {
compatible = "al,alpine-sysfabric-service", "syscon";
reg = <0x0 0xfb070000 0x0 0x10000>;
};
/* Performance Monitor Unit */
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
uart0:uart@fd883000 {
compatible = "ns16550a";
reg = <0x0 0xfd883000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uart1:uart@0xfd884000 {
compatible = "ns16550a";
reg = <0x0 0xfd884000 0x0 0x1000>;
clock-frequency = <0>; /* Filled by loader */
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
/* Internal PCIe Controller */
pcie-internal@0xfbc00000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#size-cells = <2>;
#address-cells = <3>;
#interrupt-cells = <1>;
reg = <0x0 0xfbc00000 0x0 0x100000>;
interrupt-map-mask = <0xf800 0 0 7>;
/* Add legacy interrupts for SATA devices only */
interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
<0x4800 0 0 1 &gic 0 44 4>;
/* 32 bit non prefetchable memory space */
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
};
};
};

528
sys/gnu/dts/arm/am335x-baltos-ir5221.dts Normal file
View File

@ -0,0 +1,528 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* VScom OnRISC
* http://www.vscom.de
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "OnRISC Baltos iR 5221";
compatible = "vscom,onrisc", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
wl12xx_vmmc: fixedregulator@2 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 8 0>;
startup-delay-us = <70000>;
enable-active-high;
};
};
&am33xx_pinmux {
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
>;
};
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
>;
};
tps65910_pins: pinmux_tps65910_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
>;
};
tca6416_pins: pinmux_tca6416_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
>;
};
dcan1_pins: pinmux_dcan1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */
AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
/* Slave 2 */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value*/
AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&elm {
status = "okay";
};
&gpmc {
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
status = "okay";
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
elm_id = <&elm>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@2d {
reg = <0x2d>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <28 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tps65910_pins>;
};
at24@50 {
compatible = "at24,24c02";
pagesize = <8>;
reg = <0x50>;
};
tca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio0>;
interrupts = <20 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
};
&usb1 {
status = "okay";
dr_mode = "otg";
};
&cppi41dma {
status = "okay";
};
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
ti,en-ck32k-xtal = <1>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-always-on;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <7>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
};
&phy_sel {
rmii-clock-ext = <1>;
};
&mmc1 {
vmmc-supply = <&vmmc_reg>;
status = "okay";
};
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
ti,non-removable;
bus-width = <4>;
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&gpio0 {
ti,no-reset-on-init;
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};

48
sys/gnu/dts/arm/am335x-base0033.dts
View File

@ -46,39 +46,39 @@
&am33xx_pinmux {
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
>;
};
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
pinctrl-single,pins = <
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
>;
};
leds_base_pins: pinmux_leds_base_pins {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
>;
};
};

207
sys/gnu/dts/arm/am335x-bone-common.dtsi
View File

@ -67,105 +67,112 @@
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
};
@ -195,6 +202,7 @@
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
&usb1 {
@ -217,18 +225,99 @@
reg = <0x24>;
};
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
#address-cells = <1>;
#size-cells = <1>;
baseboard_data: baseboard_data@0 {
reg = <0 0x100>;
};
};
};
/include/ "tps65217.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <100000>;
cape_eeprom0: cape_eeprom0@54 {
compatible = "at,24c256";
reg = <0x54>;
#address-cells = <1>;
#size-cells = <1>;
cape0_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom1: cape_eeprom1@55 {
compatible = "at,24c256";
reg = <0x55>;
#address-cells = <1>;
#size-cells = <1>;
cape1_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom2: cape_eeprom2@56 {
compatible = "at,24c256";
reg = <0x56>;
#address-cells = <1>;
#size-cells = <1>;
cape2_data: cape_data@0 {
reg = <0 0x100>;
};
};
cape_eeprom3: cape_eeprom3@57 {
compatible = "at,24c256";
reg = <0x57>;
#address-cells = <1>;
#size-cells = <1>;
cape3_data: cape_data@0 {
reg = <0 0x100>;
};
};
};
&tps {
compatible = "ti,tps65217";
/*
* Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only
* mode") at poweroff. Most BeagleBone versions do not support RTC-only
* mode and risk hardware damage if this mode is entered.
*
* For details, see linux-omap mailing list May 2015 thread
* [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller
* In particular, messages:
* http://www.spinics.net/lists/linux-omap/msg118585.html
* http://www.spinics.net/lists/linux-omap/msg118615.html
*
* You can override this later with
* &tps { /delete-property/ ti,pmic-shutdown-controller; }
* if you want to use RTC-only mode and made sure you are not affected
* by the hardware problems. (Tip: double-check by performing a current
* measurement after shutdown: it should be less than 1 mA.)
*/
ti,pmic-shutdown-controller;
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr";
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
@ -238,6 +327,7 @@
};
dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
@ -247,21 +337,25 @@
};
ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8";
regulator-always-on;
};
ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3a";
regulator-always-on;
};
@ -297,6 +391,13 @@
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&aes {
status = "okay";
};
&sham {
status = "okay";
};

8
sys/gnu/dts/arm/am335x-bone.dts
View File

@ -24,11 +24,3 @@
&mmc1 {
vmmc-supply = <&ldo3_reg>;
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};

64
sys/gnu/dts/arm/am335x-boneblack.dts
View File

@ -36,48 +36,58 @@
&am33xx_pinmux {
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr0 */
>;
};
};
&lcdc {
status = "okay";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&hdmi_0>;
};
};
};
/ {
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
&i2c0 {
tda19988 {
compatible = "nxp,tda998x";
reg = <0x70>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
status = "okay";
port {
hdmi_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
};

53
sys/gnu/dts/arm/am335x-bonegreen.dts Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
/ {
model = "TI AM335x BeagleBone Green";
compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
};
&ldo3_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
&mmc1 {
vmmc-supply = <&vmmcsd_fixed>;
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
};
&am33xx_pinmux {
uart2_pins: uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&rtc {
system-power-controller;
};

112
sys/gnu/dts/arm/am335x-chiliboard.dts Normal file
View File

@ -0,0 +1,112 @@
/*
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am335x-chilisom.dtsi"
/ {
model = "AM335x Chiliboard";
compatible = "grinn,am335x-chiliboard", "grinn,am335x-chilisom",
"ti,am33xx";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_gpio_pins>;
led0 {
label = "led0";
gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "heartbeat";
};
led1 {
label = "led1";
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
};
};
&am33xx_pinmux {
usb1_drvvbus: usb1_drvvbus {
pinctrl-single,pins = <
AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
>;
};
sd_pins: pinmux_sd_card {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
led_gpio_pins: led_gpio_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */
AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
>;
};
};
&ldo4_reg {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/* Ethernet */
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};
/* USB */
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_drvvbus>;
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
/* microSD */
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sd_pins>;
vmmc-supply = <&ldo4_reg>;
bus-width = <0x4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};

249
sys/gnu/dts/arm/am335x-chilisom.dtsi Normal file
View File

@ -0,0 +1,249 @@
/*
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am33xx.dtsi"
/ {
model = "Grinn AM335x ChiliSOM";
compatible = "grinn,am335x-chilisom", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&am33xx_pinmux {
pinctrl-names = "default";
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nandflash_pins: nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
};
&tps {
compatible = "ti,tps65217";
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr";
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds";
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux";
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8";
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3d";
regulator-boot-on;
regulator-always-on;
};
};
};
/* Ethernet MAC */
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
/* NAND Flash */
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
nand@0,0 {
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
};
};

396
sys/gnu/dts/arm/am335x-cm-t335.dts Normal file
View File

@ -0,0 +1,396 @@
/*
* am335x-cm-t335.dts - Device Tree file for Compulab CM-T335
*
* Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "CompuLab CM-T335";
compatible = "compulab,cm-t335", "ti,am33xx";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>; /* 128 MB */
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&gpio_led_pins>;
led@0 {
label = "cm_t335:green";
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */
linux,default-trigger = "heartbeat";
};
};
/* regulator for mmc */
vmmc_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmc_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&bluetooth_pins>;
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
/* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
/* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
/* uart0_ctsn.i2c1_sda */
AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE2)
/* uart0_rtsn.i2c1_scl */
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2)
>;
};
gpio_led_pins: pinmux_gpio_led_pins {
pinctrl-single,pins = <
/* gpmc_csn3.gpio2_0 */
AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7)
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
/* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)
/* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)
/* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
/* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
/* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
/* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
/* gpmc_ben0_cle.gpmc_ben0_cle */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
/* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
/* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
/* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)
/* uart1_rtsn.uart1_rtsn */
AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
/* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
/* uart1_txd.uart1_txd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
ecap0_pins: pinmux_ecap0_pins {
pinctrl-single,pins = <
/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
AM33XX_IOPAD(0x964, 0x0)
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
/* mii1_tx_en.rgmii1_tctl */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)
/* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)
/* mii1_rxd0.rgmii1_rd0 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
/* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
/* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
>;
};
/* wl1271 bluetooth */
bluetooth_pins: pinmux_bluetooth_pins {
pinctrl-single,pins = <
/* XDMA_EVENT_INTR0.gpio0_19 - bluetooth enable */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
/* WLS1271 bluetooth */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
/* CM-T335 board EEPROM */
eeprom: 24c02@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
/* Real Time Clock */
ext_rtc: em3027@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb0 {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&epwmss0 {
status = "okay";
ecap0: ecap@48300100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
};
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "spl";
reg = <0x00000000 0x00200000>;
};
partition@1 {
label = "uboot";
reg = <0x00200000 0x00100000>;
};
partition@2 {
label = "uboot environment";
reg = <0x00300000 0x00100000>;
};
partition@3 {
label = "dtb";
reg = <0x00400000 0x00100000>;
};
partition@4 {
label = "splash";
reg = <0x00500000 0x00400000>;
};
partition@5 {
label = "linux";
reg = <0x00900000 0x00600000>;
};
partition@6 {
label = "rootfs";
reg = <0x00F00000 0>;
};
};
};
&elm {
status = "okay";
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <1>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmc_fixed>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
};

311
sys/gnu/dts/arm/am335x-evm.dts
View File

@ -8,6 +8,7 @@
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x EVM";
@ -38,6 +39,20 @@
regulator-boot-on;
};
wlan_en_reg: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/* WLAN_EN GPIO for this board - Bank1, pin16 */
gpio = <&gpio1 16 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
@ -68,14 +83,14 @@
label = "volume-up";
linux,code = <115>;
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
switch@10 {
label = "volume-down";
linux,code = <114>;
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
};
@ -121,16 +136,29 @@
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <12000000>;
ti,audio-routing =
compatible = "simple-audio-card";
simple-audio-card,name = "AM335x-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <12000000>;
};
};
};
@ -140,178 +168,215 @@
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = <
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
>;
};
volume_keys_s0: volume_keys_s0 {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
mmc3_pins: pinmux_mmc3_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
>;
};
wlan_pins: pinmux_wlan_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
>;
};
lcd_pins_s0: lcd_pins_s0 {
pinctrl-single,pins = <
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
am335x_evm_audio_pins: am335x_evm_audio_pins {
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
>;
};
};
@ -323,6 +388,13 @@
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@ -410,6 +482,7 @@
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@ -525,8 +598,10 @@
#include "tps65910.dtsi"
&mcasp1 {
pinctrl-names = "default";
pinctrl-0 = <&am335x_evm_audio_pins>;
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
@ -662,7 +737,33 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mmc3 {
/* these are on the crossbar and are outlined in the
xbar-event-map element */
dmas = <&edma_xbar 12 0 1
&edma_xbar 13 0 2>;
dma-names = "tx", "rx";
status = "okay";
vmmc-supply = <&wlan_en_reg>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlan_pins>;
ti,non-removable;
ti,needs-special-hs-handling;
cap-power-off-card;
keep-power-in-suspend;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio3>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
};
};
&sham {

323
sys/gnu/dts/arm/am335x-evmsk.dts
View File

@ -15,6 +15,7 @@
#include "am33xx.dtsi"
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "TI AM335x EVM-SK";
@ -122,7 +123,7 @@
label = "button2";
linux,code = <0x102>;
gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
gpio-key,wakeup;
wakeup-source;
};
switch@4 {
@ -140,14 +141,26 @@
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-EVMSK";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <24000000>;
ti,audio-routing =
compatible = "simple-audio-card";
simple-audio-card,name = "AM335x-EVMSK";
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24000000>;
};
};
panel {
@ -191,225 +204,234 @@
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
lcd_pins_sleep: lcd_pins_sleep {
pinctrl-single,pins = <
0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
>;
};
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
>;
};
gpio_keys_s0: gpio_keys_s0 {
pinctrl-single,pins = <
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
ecap2_pins: backlight_pins {
pinctrl-single,pins = <
0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
/* Slave 2 */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value*/
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
>;
};
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
>;
};
};
@ -461,6 +483,7 @@
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@ -624,7 +647,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&sham {
@ -647,11 +670,23 @@
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio0>;
interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
ref-clock-frequency = <38400000>;
};
};
&mcasp1 {
pinctrl-names = "default";
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";

40
sys/gnu/dts/arm/am335x-igep0033.dtsi
View File

@ -56,41 +56,41 @@
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
nandflash_pins: pinmux_nandflash_pins {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
leds_pins: pinmux_leds_pins {
pinctrl-single,pins = <
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
>;
};
};

124
sys/gnu/dts/arm/am335x-lxm.dts
View File

@ -46,109 +46,109 @@
&am33xx_pinmux {
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */
/* Slave 2 */
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */
/* Slave 2 reset value*/
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */
AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */
AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */
AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */
AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
};
@ -328,6 +328,10 @@
dual_emac_res_vlan = <3>;
};
&phy_sel {
rmii-clock-ext;
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;

164
sys/gnu/dts/arm/am335x-nano.dts
View File

@ -41,121 +41,121 @@
misc_pins: misc_pins {
pinctrl-single,pins = <
0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
>;
};
gpmc_pins: gpmc_pins {
pinctrl-single,pins = <
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
>;
};
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: uart1_pins {
pinctrl-single,pins = <
0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
uart2_pins: uart2_pins {
pinctrl-single,pins = <
0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
AM33XX_IOPAD(0x8c0, PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
>;
};
uart3_pins: uart3_pins {
pinctrl-single,pins = <
0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
AM33XX_IOPAD(0x8c8, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
AM33XX_IOPAD(0x964, PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
>;
};
uart4_pins: uart4_pins {
pinctrl-single,pins = <
0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
AM33XX_IOPAD(0x8d0, PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
AM33XX_IOPAD(0x968, PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
>;
};
uart5_pins: uart5_pins {
pinctrl-single,pins = <
0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
AM33XX_IOPAD(0x944, PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
>;
};
mmc1_pins: mmc1_pins {
pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
>;
};
};
@ -213,7 +213,9 @@
pinctrl-0 = <&i2c0_pins>;
gpio@20 {
compatible = "mcp,mcp23017";
compatible = "microchip,mcp23017";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
};
@ -222,7 +224,7 @@
};
eeprom@53 {
compatible = "mcp,24c02";
compatible = "microchip,24c02";
reg = <0x53>;
pagesize = <8>;
};
@ -297,8 +299,8 @@
| |-->0x004FFFFF-> Kernel end
| |-->0x00500000-> File system start
| |
| |-->0x014FFFFF-> File system end
| |-->0x01500000-> User data start
| |-->0x01FFFFFF-> File system end
| |-->0x02000000-> User data start
| |
| |-->0x03FFFFFF-> User data end
| |-->0x04000000-> Data storage start
@ -327,12 +329,12 @@
partition@4 {
label = "rootfs";
reg = <0x00500000 0x01000000>; /* 16MB */
reg = <0x00500000 0x01b00000>; /* 27MB */
};
partition@5 {
label = "user";
reg = <0x01500000 0x02b00000>; /* 43MB */
reg = <0x02000000 0x02000000>; /* 32MB */
};
partition@6 {
@ -343,7 +345,7 @@
};
&mac {
dual_emac = <1>;
dual_emac;
status = "okay";
};
@ -353,11 +355,13 @@
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};
@ -371,11 +375,15 @@
wp-gpios = <&gpio3 18 0>;
};
#include "tps65217.dtsi"
&tps {
compatible = "ti,tps65217";
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
/* +1.5V voltage with ±4% tolerance */
regulator-min-microvolt = <1450000>;
regulator-max-microvolt = <1550000>;
@ -384,6 +392,7 @@
};
dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <915000>;
@ -393,6 +402,7 @@
};
dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <915000>;
@ -402,6 +412,7 @@
};
ldo1_reg: regulator@3 {
reg = <3>;
/* +1.8V voltage with ±4% tolerance */
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <1870000>;
@ -410,6 +421,7 @@
};
ldo2_reg: regulator@4 {
reg = <4>;
/* +3.3V voltage with ±4% tolerance */
regulator-min-microvolt = <3175000>;
regulator-max-microvolt = <3430000>;
@ -418,6 +430,7 @@
};
ldo3_reg: regulator@5 {
reg = <5>;
/* +1.8V voltage with ±4% tolerance */
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <1870000>;
@ -426,6 +439,7 @@
};
ldo4_reg: regulator@6 {
reg = <6>;
/* +3.3V voltage with ±4% tolerance */
regulator-min-microvolt = <3175000>;
regulator-max-microvolt = <3430000>;

247
sys/gnu/dts/arm/am335x-pepper.dts
View File

@ -74,6 +74,7 @@
audio_codec: tlv320aic3106@1b {
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
ai3x-micbias-vg = <0x2>;
};
accel: lis331dlh@1d {
@ -92,14 +93,14 @@
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0 {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1 {
pinctrl-single,pins = <
0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
AM33XX_IOPAD(0x90C, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
>;
};
};
@ -129,7 +130,7 @@
&am33xx_pinmux {
accel_pins: pinmux_accel {
pinctrl-single,pins = <
0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
AM33XX_IOPAD(0x898, PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
>;
};
};
@ -153,7 +154,7 @@
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In";
"MIC3L", "Mic3L Switch";
};
&mcasp0 {
@ -176,12 +177,12 @@
&am33xx_pinmux {
audio_pins: pinmux_audio {
pinctrl-single,pins = <
0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
>;
};
};
@ -227,36 +228,36 @@
&am33xx_pinmux {
lcd_pins: pinmux_lcd {
pinctrl-single,pins = <
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
/* Display Enable */
0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
>;
};
};
@ -290,29 +291,29 @@
&am33xx_pinmux {
ethernet_pins: pinmux_ethernet {
pinctrl-single,pins = <
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
/* ethernet interrupt */
0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
/* ethernet PHY nReset */
0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
>;
};
mdio_pins: pinmux_mdio {
pinctrl-single,pins = <
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
@ -338,13 +339,6 @@
ti,non-removable;
};
&edma {
/* Map eDMA MMC2 Events from Crossbar */
ti,edma-xbar-event-map = /bits/ 16 <1 12
2 13>;
};
&mmc3 {
/* Wifi & Bluetooth on MMC #3 */
status = "okay";
@ -353,8 +347,8 @@
vmmmc-supply = <&v3v3c_reg>;
bus-width = <4>;
ti,non-removable;
dmas = <&edma 12
&edma 13>;
dmas = <&edma_xbar 12 0 1
&edma_xbar 13 0 2>;
dma-names = "tx", "rx";
};
@ -362,45 +356,45 @@
&am33xx_pinmux {
sd_pins: pinmux_sd_card {
pinctrl-single,pins = <
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
emmc_pins: pinmux_emmc {
pinctrl-single,pins = <
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
/* EMMC nReset */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
>;
};
wireless_pins: pinmux_wireless {
pinctrl-single,pins = <
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
/* WLAN nReset */
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
AM33XX_IOPAD(0x860, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
/* WLAN nPower down */
0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
AM33XX_IOPAD(0x870, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
/* 32kHz Clock */
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};
};
@ -426,9 +420,9 @@
vin-supply = <&vbat>;
};
/include/ "tps65217.dtsi"
&tps {
compatible = "ti,tps65217";
backlight {
isel = <1>; /* ISET1 */
fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
@ -436,43 +430,62 @@
};
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
/* VDD_1V8 system supply */
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
reg = <3>;
/* VRTC 1.8V always-on supply */
regulator-name = "vrtc,vdds";
regulator-always-on;
};
ldo2_reg: regulator@4 {
reg = <4>;
/* 3.3V rail */
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3_reg: regulator@5 {
reg = <5>;
/* VDD_3V3A 3.3V rail */
regulator-name = "vdd_3v3a";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo4_reg: regulator@6 {
reg = <6>;
/* VDD_3V3B 3.3V rail */
regulator-name = "vdd_3v3b";
regulator-always-on;
};
};
};
@ -487,10 +500,10 @@
&am33xx_pinmux {
spi0_pins: pinmux_spi0 {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
>;
};
};
@ -528,16 +541,16 @@
&am33xx_pinmux {
uart0_pins: pinmux_uart0 {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1 {
pinctrl-single,pins = <
0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};
};
@ -580,9 +593,9 @@
usb_pins: pinmux_usb {
pinctrl-single,pins = <
/* USB0 Over-Current (active low) */
0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
/* USB1 Over-Current (active low) */
0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
>;
};
};
@ -617,37 +630,37 @@
label = "home";
linux,code = <KEY_HOME>;
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
button@1 {
label = "menu";
linux,code = <KEY_MENU>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
buttons@2 {
label = "power";
linux,code = <KEY_POWER>;
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
};
&am33xx_pinmux {
user_leds_pins: pinmux_user_leds {
pinctrl-single,pins = <
0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
>;
};
user_buttons_pins: pinmux_user_buttons {
pinctrl-single,pins = <
0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
AM33XX_IOPAD(0x85C, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
>;
};
};

370
sys/gnu/dts/arm/am335x-phycore-som.dtsi Normal file
View File

@ -0,0 +1,370 @@
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am33xx.dtsi"
/ {
model = "Phytec AM335x phyCORE";
compatible = "phytec,am335x-phycore-som", "ti,am33xx";
aliases {
rtc0 = &i2c_rtc;
rtc1 = &rtc;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
regulators {
compatible = "simple-bus";
vcc5v: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
};
/* Crypto Module */
&aes {
status = "okay";
};
&sham {
status = "okay";
};
/* Ethernet */
&am33xx_pinmux {
ethernet0_pins: pinmux_ethernet0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>;
};
mdio_pins: pinmux_mdio {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
};
&mac {
slaves = <1>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet0_pins>;
status = "okay";
};
&phy_sel {
rmii-clock-ext;
};
/* I2C Busses */
&am33xx_pinmux {
i2c0_pins: pinmux_i2c0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
status = "okay";
tps: pmic@2d {
reg = <0x2d>;
};
i2c_eeprom: eeprom@52 {
compatible = "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
status = "disabled";
};
i2c_rtc: rtc@68 {
compatible = "rv4162";
reg = <0x68>;
status = "disabled";
};
};
/* NAND memory */
&am33xx_pinmux {
nandflash_pins: pinmux_nandflash {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
nandflash: nand@0,0 {
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true";
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <30>;
gpmc,cs-wr-off-ns = <30>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <30>;
gpmc,adv-wr-off-ns = <30>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <10>;
gpmc,oe-off-ns = <30>;
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <30>;
gpmc,wr-cycle-ns = <30>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <50>;
gpmc,cycle2cycle-diffcsen;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <30>;
gpmc,wr-data-mux-bus-ns = <0>;
elm_id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "xload";
reg = <0x0 0x20000>;
};
partition@1 {
label = "xload_backup1";
reg = <0x20000 0x20000>;
};
partition@2 {
label = "xload_backup2";
reg = <0x40000 0x20000>;
};
partition@3 {
label = "xload_backup3";
reg = <0x60000 0x20000>;
};
partition@4 {
label = "barebox";
reg = <0x80000 0x80000>;
};
partition@5 {
label = "bareboxenv";
reg = <0x100000 0x40000>;
};
partition@6 {
label = "oftree";
reg = <0x140000 0x40000>;
};
partition@7 {
label = "kernel";
reg = <0x180000 0x800000>;
};
partition@8 {
label = "root";
reg = <0x980000 0x0>;
};
};
};
/* Power */
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vcc5v>;
vcc2-supply = <&vcc5v>;
vcc3-supply = <&vcc5v>;
vcc4-supply = <&vcc5v>;
vcc5-supply = <&vcc5v>;
vcc6-supply = <&vcc5v>;
vcc7-supply = <&vcc5v>;
vccio-supply = <&vcc5v>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-name = "vdig1_1p8v";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* SPI Busses */
&am33xx_pinmux {
spi0_pins: pinmux_spi0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
serial_flash: m25p80@0 {
compatible = "m25p80";
spi-max-frequency = <48000000>;
reg = <0x0>;
m25p,fast-read;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "xload";
reg = <0x0 0x20000>;
};
partition@1 {
label = "barebox";
reg = <0x20000 0x80000>;
};
partition@2 {
label = "bareboxenv";
reg = <0xa0000 0x20000>;
};
partition@3 {
label = "oftree";
reg = <0xc0000 0x20000>;
};
partition@4 {
label = "kernel";
reg = <0xe0000 0x0>;
};
};
};

219
sys/gnu/dts/arm/am335x-sbc-t335.dts Normal file
View File

@ -0,0 +1,219 @@
/*
* am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335
*
* Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am335x-cm-t335.dts"
/ {
model = "CompuLab CM-T335 on SB-T335";
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx";
/* DRM display driver */
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
/* Timing selection performed by U-Boot */
timing0: lcd {/* 800x480p62 */
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <39>;
hback-porch = <39>;
hsync-len = <47>;
vback-porch = <29>;
vfront-porch = <13>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
};
timing1: dvi { /* 1024x768p60 */
clock-frequency = <65000000>;
hactive = <1024>;
hfront-porch = <24>;
hback-porch = <160>;
hsync-len = <136>;
vactive = <768>;
vfront-porch = <3>;
vback-porch = <29>;
vsync-len = <6>;
hsync-active = <0>;
vsync-active = <0>;
};
};
};
};
&am33xx_pinmux {
/* Display */
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
/* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
/* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)
/* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
/* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
/* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
/* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
/* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
/* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
/* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)
/* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)
/* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)
/* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)
/* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)
>;
};
lcd_pins_sleep: lcd_pins_sleep {
pinctrl-single,pins = <
/* gpmc_ad8.lcd_data23 */
AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad9.lcd_data22 */
AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad10.lcd_data21 */
AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad11.lcd_data20 */
AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad12.lcd_data19 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad13.lcd_data18 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad14.lcd_data17 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* gpmc_ad15.lcd_data16 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_data0.lcd_data0 */
AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)
/* lcd_data1.lcd_data1 */
AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)
/* lcd_data2.lcd_data2 */
AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)
/* lcd_data3.lcd_data3 */
AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)
/* lcd_data4.lcd_data4 */
AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)
/* lcd_data5.lcd_data5 */
AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)
/* lcd_data6.lcd_data6 */
AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)
/* lcd_data7.lcd_data7 */
AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)
/* lcd_data8.lcd_data8 */
AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)
/* lcd_data9.lcd_data9 */
AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)
/* lcd_data10.lcd_data10 */
AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)
/* lcd_data11.lcd_data11 */
AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)
/* lcd_data12.lcd_data12 */
AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)
/* lcd_data13.lcd_data13 */
AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)
/* lcd_data14.lcd_data14 */
AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)
/* lcd_data15.lcd_data15 */
AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)
/* lcd_vsync.lcd_vsync */
AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_hsync.lcd_hsync */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_pclk.lcd_pclk */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* lcd_ac_bias_en.lcd_ac_bias_en */
AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
};
&i2c0 {
/* GPIO extender */
gpio_ext: pca9555@26 {
compatible = "nxp,pca9555";
pinctrl-names = "default";
gpio-controller;
#gpio-cells = <2>;
reg = <0x26>;
dvi_ena {
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dvi-enable";
};
lcd_ena {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "lcd-enable";
};
};
};
/* Display */
&lcdc {
status = "okay";
};

577
sys/gnu/dts/arm/am335x-shc.dts Normal file
View File

@ -0,0 +1,577 @@
/*
* support for the bosch am335x based shc c3 board
*
* Copyright, C) 2015 Heiko Schocher <hs@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Bosch SHC";
compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
aliases {
mmcblk0 = &mmc1;
mmcblk1 = &mmc2;
};
cpus {
cpu@0 {
/*
* To consider voltage drop between PMIC and SoC,
* tolerance value is reduced to 2% from 4% and
* voltage value is increased as a precaution.
*/
operating-points = <
/* kHz uV */
594000 1225000
294000 1125000
>;
voltage-tolerance = <2>; /* 2 percentage */
cpu0-supply = <&dcdc2_reg>;
};
};
gpio_keys {
compatible = "gpio-keys";
back_button {
label = "Back Button";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_BACK>;
debounce-interval = <1000>;
gpio-key,wakeup;
};
front_button {
label = "Front Button";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_FRONT>;
debounce-interval = <1000>;
gpio-key,wakeup;
};
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
compatible = "gpio-leds";
led@1 {
label = "shc:power:red";
gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "shc:power:bl";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
default-state = "on";
};
led@3 {
label = "shc:lan:red";
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@4 {
label = "shc:lan:bl";
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "shc:cloud:red";
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@6 {
label = "shc:cloud:bl";
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&aes {
status = "okay";
};
&cppi41dma {
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
ethernetphy0: ethernet-phy@0 {
reg = <0>;
smsc,disable-energy-detect;
};
};
&epwmss1 {
status = "okay";
ehrpwm1: ehrpwm@48302200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
};
};
&gpio1 {
hmtc_rst {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_reset";
};
hmtc_prog {
gpio-hog;
gpios = <27 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_program";
};
};
&gpio3 {
zgb_rst {
gpio-hog;
gpios = <18 GPIO_ACTIVE_LOW>;
output-low;
line-name = "zigbee_reset";
};
zgb_boot {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "zigbee_boot";
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
at24@50 {
compatible = "at24,24c32";
pagesize = <32>;
reg = <0x50>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
cpsw_emac0: slave@4a100200 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
phy-handle = <&ethernetphy0>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <0x4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
max-frequency = <26000000>;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
max-frequency = <26000000>;
sd-uhs-sdr25;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&mmc3 {
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins>;
bus-width = <4>;
cap-power-off-card;
max-frequency = <26000000>;
sd-uhs-sdr25;
vmmc-supply = <&vmmcsd_fixed>;
status = "okay";
};
&rtc {
ti,no-init;
};
&sham {
status = "okay";
};
&tps {
compatible = "ti,tps65217";
ti,pmic-shutdown-controller;
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
regulator-name = "vdds_dpr";
regulator-compatible = "dcdc1";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1450000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/*
* VDD_MPU voltage limits 0.95V - 1.26V with
* +/-4% tolerance
*/
regulator-compatible = "dcdc2";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <70000>;
};
dcdc3_reg: regulator@2 {
reg = <2>;
/*
* VDD_CORE voltage limits 0.95V - 1.1V with
* +/-4% tolerance
*/
regulator-name = "vdd_core";
regulator-compatible = "dcdc3";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1125000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
reg = <3>;
regulator-name = "vio,vrtc,vdds";
regulator-compatible = "ldo1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo2_reg: regulator@4 {
reg = <4>;
regulator-name = "vdd_3v3aux";
regulator-compatible = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo3_reg: regulator@5 {
reg = <5>;
regulator-name = "vdd_1v8";
regulator-compatible = "ldo3";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
reg = <6>;
regulator-name = "vdd_3v3a";
regulator-compatible = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "okay";
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
/* xdma_event_intr1.clkout2 */
AM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
ehrpwm1_pins: pinmux_ehrpwm1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)
>;
};
mmc3_pins: pinmux_mmc3_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)
AM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)
>;
};
uart1_pins: pinmux_uart1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)
AM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)
AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)
>;
};
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)
AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)
AM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)
>;
};
};

491
sys/gnu/dts/arm/am335x-sl50.dts Normal file
View File

@ -0,0 +1,491 @@
/*
* Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "Toby Churchill SL50 Series";
compatible = "tcl,am335x-sl50", "ti,am33xx";
cpus {
cpu@0 {
cpu0-supply = <&dcdc2_reg>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
led@0 {
label = "sl50:green:usr0";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@1 {
label = "sl50:red:usr1";
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@2 {
label = "sl50:green:usr2";
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led@3 {
label = "sl50:red:usr3";
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
backlight0: disp0 {
compatible = "pwm-backlight";
pwms = <&ehrpwm1 0 500000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
default-brightness-level = <6>;
};
backlight1: disp1 {
compatible = "pwm-backlight";
pwms = <&ehrpwm1 1 500000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
default-brightness-level = <6>;
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM335x-SL50";
ti,audio-codec = <&audio_codec>;
ti,mcasp-controller = <&mcasp0>;
ti,codec-clock-rate = <12000000>;
ti,audio-routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1R", "Line In",
"LINE1L", "Line In";
};
emmc_pwrseq: pwrseq@0 {
compatible = "mmc-pwrseq-emmc";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pwrseq_pins>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
vmmcsd_fixed: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&lwb_pins>;
led_pins: pinmux_led_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* gpmc_a6.gpio1_22 */
AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* gpmc_a7.gpio1_23 */
AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* gpmc_a8.gpio1_24 */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* gpmc_wait0.uart4_rxd */
AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpmc_wpn.uart4_txd */
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rxd.i2c1_sda */
AM33XX_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_txdi2c1_scl */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
AM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
AM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a4.gpio1_20 */
>;
};
emmc_pins: pinmux_emmc_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
audio_pins: pinmux_audio_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
>;
};
ehrpwm1_pins: pinmux_ehrpwm1a_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* gpmc_a2.ehrpwm1a */
AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.ehrpwm1b */
>;
};
lwb_pins: pinmux_lwb_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) /* SoundPA_en - mcasp0_fsr.gpio3_19 */
AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7) /* nKbdOnC - gpmc_ad10.gpio0_26 */
AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdInt - gpmc_ad12.gpio1_12 */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7) /* nKbdReset - gpmc_ad13.gpio1_13 */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7) /* nDispReset - gpmc_ad14.gpio1_14 */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* USB1_enPower - gpmc_a1.gpio1_17 */
/* AVR Programming - SPI Bus (bit bang) - Screen and Keyboard */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMOSI spi0_d0.gpio0_3 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattMISO spi0_d1.gpio0_4 */
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE7) /* Kbd/Disp/BattSCLK spi0_clk.gpio0_2 */
/* PDI Bus - Battery system */
AM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7) /* nBattReset gpmc_a0.gpio1_16 */
AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7) /* BattPDIData gpmc_ad15.gpio1_15 */
>;
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <400000>;
tps: tps@24 {
reg = <0x24>;
};
eeprom: eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
audio_codec: tlv320aic3106@1b {
status = "okay";
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
AVDD-supply = <&ldo4_reg>;
IOVDD-supply = <&ldo4_reg>;
DRVDD-supply = <&ldo4_reg>;
DVDD-supply = <&ldo3_reg>;
};
};
&usb {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1_phy {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
&usb1 {
status = "okay";
dr_mode = "host";
};
&cppi41dma {
status = "okay";
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vmmcsd_fixed>;
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
vmmc-supply = <&vmmcsd_fixed>;
mmc-pwrseq = <&emmc_pwrseq>;
};
&mcasp0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&audio_pins>;
op-mode = <0>; /* MCASP_ISS_MODE */
tdm-slots = <2>;
serial-dir = <
2 0 1 0
0 0 0 0
0 0 0 0
0 0 0 0
>;
tx-num-evt = <1>;
rx-num-evt = <1>;
};
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&tps {
compatible = "ti,tps65217";
ti,pmic-shutdown-controller;
interrupt-parent = <&intc>;
interrupts = <7>; /* NNMI */
regulators {
#address-cells = <1>;
#size-cells = <0>;
dcdc1_reg: regulator@0 {
reg = <0>;
/* VDDS_DDR */
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
dcdc2_reg: regulator@1 {
reg = <1>;
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: regulator@2 {
reg = <2>;
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@3 {
reg = <3>;
/* VRTC / VIO / VDDS*/
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2_reg: regulator@4 {
reg = <4>;
/* VDD_3V3AUX */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo3_reg: regulator@5 {
reg = <5>;
/* VDD_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4_reg: regulator@6 {
reg = <6>;
/* VDD_3V3A */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
};
&davinci_mdio {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&sham {
status = "okay";
};
&aes {
status = "okay";
};
&epwmss1 {
status = "okay";
};
&ehrpwm1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
};

22
sys/gnu/dts/arm/am335x-wega-rdk.dts Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "am335x-phycore-som.dtsi"
#include "am335x-wega.dtsi"
/* SoM */
&i2c_eeprom {
status = "okay";
};
&i2c_rtc {
status = "okay";
};

162
sys/gnu/dts/arm/am335x-wega.dtsi Normal file
View File

@ -0,0 +1,162 @@
/*
* Copyright (C) 2015 Phytec Messtechnik GmbH
* Author: Teresa Remmet <t.remmet@phytec.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
model = "Phytec AM335x phyBOARD-WEGA";
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
regulators {
compatible = "simple-bus";
vcc3v3: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
/* CAN Busses */
&am33xx_pinmux {
dcan1_pins: pinmux_dcan1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
>;
};
};
&dcan1 {
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins>;
status = "okay";
};
/* Ethernet */
&am33xx_pinmux {
ethernet1_pins: pinmux_ethernet1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
>;
};
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
dual_emac_res_vlan = <2>;
};
&mac {
slaves = <2>;
pinctrl-names = "default";
pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
dual_emac = <1>;
};
/* MMC */
&am33xx_pinmux {
mmc1_pins: pinmux_mmc1 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
>;
};
};
&mmc1 {
vmmc-supply = <&vcc3v3>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* UARTs */
&am33xx_pinmux {
uart0_pins: pinmux_uart0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
/* USB */
&cppi41dma {
status = "okay";
};
&usb_ctrl_mod {
status = "okay";
};
&usb {
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
status = "okay";
};
&usb0_phy {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&usb1_phy {
status = "okay";
};

8
sys/gnu/dts/arm/am33xx-clocks.dtsi
View File

@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -99,7 +99,7 @@
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
@ -107,7 +107,7 @@
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
@ -115,7 +115,7 @@
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};

200
sys/gnu/dts/arm/am33xx.dtsi
View File

@ -83,20 +83,6 @@
};
};
am33xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7fc>;
};
am33xx_pinmux: pinmux@44e10800 {
compatible = "pinctrl-single";
reg = <0x44e10800 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
@ -111,9 +97,24 @@
ranges;
ti,hwmods = "l3_main";
prcm: prcm@44e00000 {
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am3-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
reg = <0x44e00000 0x4000>;
reg = <0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -124,22 +125,53 @@
};
};
scrm: scrm@44e10000 {
compatible = "ti,am3-scrm";
reg = <0x44e10000 0x2000>;
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x2000>;
scrm_clocks: clocks {
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
cm: syscon@44e10000 {
compatible = "ti,am33xx-controlmodule", "syscon";
reg = <0x44e10000 0x800>;
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <32>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
intc: interrupt-controller@48200000 {
@ -150,12 +182,44 @@
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x40>;
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
#dma-cells = <1>;
interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <20 21>;
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
gpio0: gpio@44e07000 {
@ -203,40 +267,40 @@
};
uart0: serial@44e09000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26>, <&edma 27>;
dmas = <&edma 26 0>, <&edma 27 0>;
dma-names = "tx", "rx";
};
uart1: serial@48022000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28>, <&edma 29>;
dmas = <&edma 28 0>, <&edma 29 0>;
dma-names = "tx", "rx";
};
uart2: serial@48024000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30>, <&edma 31>;
dmas = <&edma 30 0>, <&edma 31 0>;
dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
@ -245,7 +309,7 @@
};
uart4: serial@481a8000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
@ -254,7 +318,7 @@
};
uart5: serial@481aa000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
@ -298,8 +362,8 @@
ti,dual-volt;
ti,needs-special-reset;
ti,needs-special-hs-handling;
dmas = <&edma 24
&edma 25>;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
interrupts = <64>;
interrupt-parent = <&intc>;
@ -311,8 +375,8 @@
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2
&edma 3>;
dmas = <&edma 2 0
&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <28>;
interrupt-parent = <&intc>;
@ -350,7 +414,7 @@
reg = <0x481cc000 0x2000>;
clocks = <&dcan0_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
@ -361,7 +425,7 @@
reg = <0x481d0000 0x2000>;
clocks = <&dcan1_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
@ -450,10 +514,10 @@
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
dmas = <&edma 16
&edma 17
&edma 18
&edma 19>;
dmas = <&edma 16 0
&edma 17 0
&edma 18 0
&edma 19 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@ -466,10 +530,10 @@
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
dmas = <&edma 42
&edma 43
&edma 44
&edma 45>;
dmas = <&edma 42 0
&edma 43 0
&edma 44 0
&edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@ -693,7 +757,7 @@
};
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
compatible = "ti,am335x-cpsw","ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
@ -720,7 +784,7 @@
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&cm>;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@4a101000 {
@ -755,14 +819,6 @@
reg = <0x40300000 0x10000>; /* 64k */
};
wkup_m3: wkup_m3@44d00000 {
compatible = "ti,am3353-wkup-m3";
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
ti,no-reset-on-init;
};
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
@ -803,6 +859,8 @@
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
@ -815,7 +873,7 @@
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
@ -824,8 +882,8 @@
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6>,
<&edma 5>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
@ -838,8 +896,8 @@
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8>,
<&edma 9>;
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
@ -852,8 +910,8 @@
interrupts = <82>, <83>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10>,
<&edma 11>;
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};

2
sys/gnu/dts/arm/am3517-craneboard.dts
View File

@ -77,7 +77,7 @@
&omap3_pmx_core {
tps_pins: pinmux_tps_pins {
pinctrl-single,pins = <
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
OMAP3_CORE1_IOPAD(0x21e0, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
>;
};
};

13
sys/gnu/dts/arm/am3517.dtsi
View File

@ -31,7 +31,7 @@
status = "disabled";
reg = <0x5c000000 0x30000>;
interrupts = <67 68 69 70>;
syscon = <&omap3_scm_general>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0x10000>;
ti,davinci-ctrl-mod-reg-offset = <0>;
ti,davinci-ctrl-ram-offset = <0x20000>;
@ -60,6 +60,17 @@
dma-names = "tx", "rx";
clock-frequency = <48000000>;
};
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};

16
sys/gnu/dts/arm/am35xx-clocks.dtsi
View File

@ -7,12 +7,12 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
emac_ick: emac_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <1>;
};
@ -20,7 +20,7 @@
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&rmii_ck>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <9>;
};
@ -28,7 +28,7 @@
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <2>;
};
@ -36,7 +36,7 @@
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pclk_ck>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <10>;
};
@ -44,7 +44,7 @@
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <0>;
};
@ -52,7 +52,7 @@
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <8>;
};
@ -60,7 +60,7 @@
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&sys_ck>;
reg = <0x059c>;
reg = <0x032c>;
ti,bit-shift = <3>;
};
};

243
sys/gnu/dts/arm/am4372.dtsi
View File

@ -15,7 +15,7 @@
/ {
compatible = "ti,am4372", "ti,am43";
interrupt-parent = <&gic>;
interrupt-parent = <&wakeupgen>;
aliases {
@ -23,8 +23,14 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
spi0 = &qspi;
};
cpus {
@ -48,6 +54,36 @@
#interrupt-cells = <3>;
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48281000 0x1000>;
interrupt-parent = <&gic>;
};
scu: scu@48240000 {
compatible = "arm,cortex-a9-scu";
reg = <0x48240000 0x100>;
};
global_timer: timer@48240200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x48240200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&mpu_periphclk>;
};
local_timer: timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x48240600 0x100>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&mpu_periphclk>;
};
l2-cache-controller@48242000 {
@ -57,22 +93,6 @@
cache-level = <2>;
};
am43xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7f4>;
};
am43xx_pinmux: pinmux@44e10800 {
compatible = "ti,am437-padconf", "pinctrl-single";
reg = <0x44e10800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
ocp {
compatible = "ti,am4372-l3-noc", "simple-bus";
#address-cells = <1>;
@ -84,9 +104,25 @@
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prcm: prcm@44df0000 {
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
wkup_m3: wkup_m3@100000 {
compatible = "ti,am4372-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
reg = <0x44df0000 0x11000>;
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -97,28 +133,105 @@
};
};
scrm: scrm@44e10000 {
compatible = "ti,am4-scrm";
reg = <0x44e10000 0x2000>;
scm: scm@210000 {
compatible = "ti,am4-scm", "simple-bus";
reg = <0x210000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x4000>;
scrm_clocks: clocks {
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am4372-wkup-m3-ipc";
reg = <0x1324 0x44>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <64>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am4372";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x10>;
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <32 33>;
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
uart0: serial@44e09000 {
@ -280,11 +393,14 @@
};
rtc: rtc@44e3e000 {
compatible = "ti,am4372-rtc","ti,da830-rtc";
compatible = "ti,am4372-rtc", "ti,am3352-rtc",
"ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "rtc";
clocks = <&clk_32768_ck>;
clock-names = "int-clk";
status = "disabled";
};
@ -420,8 +536,8 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&edma 24
&edma 25>;
dmas = <&edma 24 0>,
<&edma 25 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -432,8 +548,8 @@
reg = <0x481d8000 0x1000>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2
&edma 3>;
dmas = <&edma 2 0>,
<&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@ -499,8 +615,11 @@
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
<&dpll_clksel_mac_clk>;
clock-names = "fck", "cpts", "50mclk";
assigned-clocks = <&dpll_clksel_mac_clk>;
assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
@ -513,6 +632,7 @@
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
ranges;
syscon = <&scm_conf>;
davinci_mdio: mdio@4a101000 {
compatible = "ti,am4372-mdio","ti,davinci_mdio";
@ -697,7 +817,7 @@
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x300>;
dmas = <&edma 36>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
@ -707,8 +827,8 @@
ti,hwmods = "aes";
reg = <0x53501000 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6
&edma 5>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
@ -717,8 +837,8 @@
ti,hwmods = "des";
reg = <0x53701000 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34
&edma 33>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
};
@ -731,8 +851,8 @@
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8>,
<&edma 9>;
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
@ -745,8 +865,8 @@
interrupts = <82>, <83>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10>,
<&edma 11>;
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
@ -763,6 +883,8 @@
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
dmas = <&edma 52>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
@ -787,7 +909,7 @@
};
ocp2scp0: ocp2scp@483a8000 {
compatible = "ti,omap-ocp2scp";
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -806,7 +928,7 @@
};
ocp2scp1: ocp2scp@483e8000 {
compatible = "ti,omap-ocp2scp";
compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -837,7 +959,12 @@
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@ -861,7 +988,12 @@
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x10000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral",
"host",
"otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@ -874,7 +1006,9 @@
qspi: qspi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>;
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
@ -884,7 +1018,7 @@
};
hdq: hdq@48347000 {
compatible = "ti,am43xx-hdq";
compatible = "ti,am4372-hdq";
reg = <0x48347000 0x1000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&func_12m_clk>;
@ -919,6 +1053,7 @@
ti,hwmods = "dss_rfbi";
clocks = <&disp_clk>;
clock-names = "fck";
status = "disabled";
};
};
@ -933,7 +1068,7 @@
clocks = <&dcan0_fck>;
clock-names = "fck";
reg = <0x481cc000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@ -944,7 +1079,7 @@
clocks = <&dcan1_fck>;
clock-names = "fck";
reg = <0x481d0000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};

422
sys/gnu/dts/arm/am437x-cm-t43.dts Normal file
View File

@ -0,0 +1,422 @@
/*
* Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am4372.dtsi"
/ {
model = "CompuLab CM-T43";
compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
leds {
compatible = "gpio-leds";
ledb {
label = "cm-t43:green";
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
vmmc_3v3: fixedregulator-v3_3 {
compatible = "regulator-fixed";
regulator-name = "vmmc_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
enable-active-high;
};
};
&am43xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&cm_t43_led_pins>;
cm_t43_led_pins: cm_t43_led_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa78, MUX_MODE7)
>;
};
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
emmc_pins: emmc_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
AM4372_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1 */
AM4372_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2 */
AM4372_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3 */
AM4372_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad12.mmc1_dat4 */
AM4372_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad13.mmc1_dat5 */
AM4372_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad14.mmc1_dat6 */
AM4372_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad15.mmc1_dat7 */
AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_sclk.spi0_sclk */
AM4372_IOPAD(0x954, PIN_INPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
AM4372_IOPAD(0x958, PIN_OUTPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
AM4372_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
AM4372_IOPAD(0x800, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x804, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x808, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x80c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x810, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x814, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x818, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x81c, PIN_INPUT | PULL_DISABLE | MUX_MODE0)
AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x898, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM4372_IOPAD(0x894, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM4372_IOPAD(0x890, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
AM4372_IOPAD(0x89c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
AM4372_IOPAD(0xa74, MUX_MODE3)
/* Slave 2 */
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.txen */
AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rxctl */
AM4372_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.txd3 */
AM4372_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.txd2 */
AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.txd1 */
AM4372_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.txd0 */
AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */
AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rclk */
AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rxd3 */
AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rxd2 */
AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rxd1 */
AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rxd0 */
AM4372_IOPAD(0xa38, MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0x08000000 0x1000000>;
nand@0,0 {
reg = <0 0 0>;
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <40>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wait-on-read = "true";
gpmc,wait-on-write = "true";
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
gpmc,wait-pin = <0>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table */
partition@0 {
label = "kernel";
reg = <0x0 0x00980000>;
};
partition@980000 {
label = "dtb";
reg = <0x00980000 0x00080000>;
};
partition@a00000 {
label = "rootfs";
reg = <0x00a00000 0x0>;
};
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
clock-frequency = <100000>;
tps65218: tps65218@24 {
compatible = "ti,tps65218";
reg = <0x24>;
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
dcdc1: regulator-dcdc1 {
compatible = "ti,tps65218-dcdc1";
regulator-name = "vdd_core";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2: regulator-dcdc2 {
compatible = "ti,tps65218-dcdc2";
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <1378000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3: regulator-dcdc3 {
compatible = "ti,tps65218-dcdc3";
regulator-name = "vdcdc3";
regulator-suspend-enable;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
dcdc6: regulator-dcdc6 {
compatible = "ti,tps65218-dcdc6";
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: regulator-ldo1 {
compatible = "ti,tps65218-ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
eeprom_module: at24@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&gpio5 {
status = "okay";
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmc_3v3>;
bus-width = <8>;
ti,non-removable;
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
dmas = <&edma 16
&edma 17>;
dma-names = "tx0", "rx0";
flash: w25q64cvzpig@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partition@0 {
label = "uboot";
reg = <0x0 0xc0000>;
};
partition@c0000 {
label = "uboot environment";
reg = <0xc0000 0x40000>;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x100000>;
};
};
};
&mac {
pinctrl-names = "default";
pinctrl-0 = <&cpsw_default>;
dual_emac = <1>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default";
pinctrl-0 = <&davinci_mdio_default>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii-txid";
dual_emac_res_vlan = <2>;
};
&dwc3_1 {
status = "okay";
};
&usb2_phy1 {
status = "okay";
};
&usb1 {
dr_mode = "host";
status = "okay";
};
&dwc3_2 {
status = "okay";
};
&usb2_phy2 {
status = "okay";
};
&usb2 {
dr_mode = "host";
status = "okay";
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "peripheral", "host", "otg";
};
&elm {
status = "okay";
};
&uart0 {
status = "okay";
};
&tscadc {
status = "okay";
tsc {
ti,wires = <4>;
ti,x-plate-resistance = <200>;
ti,coordiante-readouts = <5>;
ti,wire-config = <0x00 0x11 0x22 0x33>;
};
adc {
ti,adc-channels = <4 5 6 7>;
};
};
&cpu {
cpu0-supply = <&dcdc2>;
operating-points = <1000000 1330000>,
<800000 1260000>,
<720000 1200000>,
<600000 1100000>,
<300000 950000>;
};

637
sys/gnu/dts/arm/am437x-gp-evm.dts
View File

@ -23,9 +23,9 @@
display0 = &lcd0;
};
vmmcsd_fixed: fixedregulator-sd {
evm_v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-name = "evm_v3_3d";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
@ -42,6 +42,15 @@
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
};
vmmcwl_fixed: fixedregulator-mmcwl {
compatible = "regulator-fixed";
regulator-name = "vmmcwl_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@ -73,17 +82,6 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
/*
* SelLCDorHDMI, LOW to select HDMI. This is not really the
* panel's enable GPIO, but we don't have HDMI driver support nor
* support to switch between two displays, so using this gpio as
* panel's enable should be safe.
*/
enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@ -106,238 +104,397 @@
};
};
};
/* fixed 12MHz oscillator */
refclk: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12000000>;
};
/* fixed 32k external oscillator clock */
clk_32k_rtc: clk_32k_rtc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM437x-GP-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-frequency = <12000000>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <12000000>;
};
};
};
&am43xx_pinmux {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&wlan_pins_default>;
pinctrl-1 = <&wlan_pins_sleep>;
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
dss_pins: dss_pins {
pinctrl-single,pins = <
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
>;
};
lcd_pins: lcd_pins {
display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPIO 5_8 to select LCD / HDMI */
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
dcan0_default: dcan0_default_pins {
pinctrl-single,pins = <
0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
>;
};
dcan0_sleep: dcan0_sleep_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
>;
};
dcan1_default: dcan1_default_pins {
pinctrl-single,pins = <
0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
>;
};
dcan1_sleep: dcan1_sleep_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
>;
};
vpfe0_pins_default: vpfe0_pins_default {
pinctrl-single,pins = <
0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
>;
};
vpfe0_pins_sleep: vpfe0_pins_sleep {
pinctrl-single,pins = <
0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
>;
};
vpfe1_pins_default: vpfe1_pins_default {
pinctrl-single,pins = <
0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
>;
};
vpfe1_pins_sleep: vpfe1_pins_sleep {
pinctrl-single,pins = <
0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
>;
};
mmc3_pins_default: pinmux_mmc3_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
>;
};
mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
>;
};
wlan_pins_default: pinmux_wlan_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
>;
};
wlan_pins_sleep: pinmux_wlan_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
>;
};
uart3_pins: uart3_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
mcasp1_sleep_pins: mcasp1_sleep_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
gpio0_pins: gpio0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
>;
};
emmc_pins_default: emmc_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
>;
};
emmc_pins_sleep: emmc_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
>;
};
};
@ -352,7 +509,6 @@
reg = <0x24>;
compatible = "ti,tps65218";
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
@ -387,6 +543,8 @@
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
dcdc6: regulator-dcdc6 {
@ -394,6 +552,8 @@
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: regulator-ldo1 {
@ -404,6 +564,21 @@
regulator-always-on;
};
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&refclk 0>;
clock-names = "xvclk";
port {
ov2659_0: endpoint {
remote-endpoint = <&vpfe1_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
};
&i2c1 {
@ -420,8 +595,45 @@
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
/*
* 0x264 represents the offset of padconf register of
* gpio3_22 from am43xx_pinmux base.
*/
interrupts-extended = <&gpio3 22 IRQ_TYPE_NONE>,
<&am43xx_pinmux 0x264>;
interrupt-names = "tsc", "wakeup";
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
wakeup-source;
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&refclk 0>;
clock-names = "xvclk";
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe0_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
/* Regulators */
IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
};
};
@ -444,6 +656,26 @@
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins>;
status = "okay";
p23 {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
/* SelEMMCorNAND selects between eMMC and NAND:
* Low: NAND
* High: eMMC
* When changing this line make sure the newly
* selected device node is enabled and the previously
* selected device node is disabled.
*/
output-low;
line-name = "SelEMMCorNAND";
};
};
&gpio1 {
status = "okay";
};
@ -456,17 +688,78 @@
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
ti,no-reset-on-init;
p8 {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
* High: LCD display with analog audio via aic3111 codec
*/
gpio-hog;
gpios = <8 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SelLCDorHDMI";
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmcsd_fixed>;
vmmc-supply = <&evm_v3_3d>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
/* eMMC sits on mmc2 */
&mmc2 {
/*
* When enabling eMMC, disable GPMC/NAND and set
* SelEMMCorNAND to output-high
*/
status = "disabled";
vmmc-supply = <&evm_v3_3d>;
bus-width = <8>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_sleep>;
ti,non-removable;
};
&mmc3 {
status = "okay";
/* these are on the crossbar and are outlined in the
xbar-event-map element */
dmas = <&edma_xbar 30 0 1>,
<&edma_xbar 31 0 2>;
dma-names = "tx", "rx";
vmmc-supply = <&vmmcwl_fixed>;
bus-width = <4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mmc3_pins_default>;
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
ti,non-removable;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@0 {
compatible = "ti,wl1835";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
};
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&usb2_phy1 {
@ -512,6 +805,10 @@
};
&gpmc {
/*
* When enabling GPMC, disable eMMC and set
* SelEMMCorNAND to output-low
*/
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
@ -607,14 +904,16 @@
};
&dcan0 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan0_default>;
pinctrl-1 = <&dcan0_sleep>;
status = "okay";
};
&dcan1 {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dcan1_default>;
pinctrl-1 = <&dcan1_sleep>;
status = "okay";
};
@ -626,7 +925,7 @@
port {
vpfe0_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
@ -643,7 +942,7 @@
port {
vpfe1_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_0>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;
@ -651,3 +950,27 @@
};
};
};
&mcasp1 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_sleep_pins>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
0 0 1 2
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&rtc {
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
clock-names = "ext-clk", "int-clk";
status = "okay";
};

162
sys/gnu/dts/arm/am437x-idk-evm.dts
View File

@ -110,142 +110,149 @@
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
};
};
/* fixed 32k external oscillator clock */
clk_32k_rtc: clk_32k_rtc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
};
&am43xx_pinmux {
gpio_keys_pins_default: gpio_keys_pins_default {
pinctrl-single,pins = <
0x1b8 (PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
>;
};
i2c0_pins_default: i2c0_pins_default {
pinctrl-single,pins = <
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c0_pins_sleep: i2c0_pins_sleep {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x18c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
i2c1_pins_default: i2c1_pins_default {
i2c2_pins_default: i2c2_pins_default {
pinctrl-single,pins = <
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
>;
};
i2c1_pins_sleep: i2c1_pins_sleep {
i2c2_pins_sleep: i2c2_pins_sleep {
pinctrl-single,pins = <
0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
mmc1_pins_default: pinmux_mmc1_pins_default {
pinctrl-single,pins = <
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x1f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x1f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x1f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x1fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
pinctrl-single,pins = <
0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
ecap0_pins_default: backlight_pins_default {
pinctrl-single,pins = <
0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
qspi_pins_default: qspi_pins_default {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
>;
};
qspi_pins_sleep: qspi_pins_sleep{
pinctrl-single,pins = <
0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
};
@ -254,7 +261,7 @@
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c0_pins_default>;
pinctrl-1 = <&i2c0_pins_default>;
pinctrl-1 = <&i2c0_pins_sleep>;
clock-frequency = <400000>;
at24@50 {
@ -262,17 +269,10 @@
pagesize = <64>;
reg = <0x50>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_pins_default>;
pinctrl-1 = <&i2c1_pins_default>;
clock-frequency = <400000>;
tps: tps62362@60 {
compatible = "ti,tps62362";
reg = <0x60>;
regulator-name = "VDD_MPU";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1330000>;
@ -284,6 +284,14 @@
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_pins_default>;
pinctrl-1 = <&i2c2_pins_sleep>;
clock-frequency = <100000>;
};
&epwmss0 {
status = "okay";
};
@ -317,7 +325,7 @@
pinctrl-1 = <&mmc1_pins_sleep>;
vmmc-supply = <&v3_3d>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&qspi {
@ -393,6 +401,8 @@
};
&rtc {
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
clock-names = "ext-clk", "int-clk";
status = "okay";
};

180
sys/gnu/dts/arm/am437x-sbc-t43.dts Normal file
View File

@ -0,0 +1,180 @@
/*
* Copyright (C) 2015 CompuLab, Ltd. - http://www.compulab.co.il/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "am437x-cm-t43.dts"
#include "compulab-sb-som.dtsi"
/ {
model = "CompuLab CM-T43 on SB-SOM-T43";
compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43";
aliases {
display0 = &lcd0;
};
};
&am43xx_pinmux {
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM4372_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM4372_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM4372_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM4372_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM4372_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM4372_IOPAD(0x964, PIN_INPUT | MUX_MODE7) /* ecap0_in_pwm0_out.gpio0_7 */
>;
};
dss_pinctrl_default: dss_pinctrl_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam0 hd -> DSS DATA 23 */
AM4372_IOPAD(0x9b4, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9b8, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9bc, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9c0, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9c4, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9c8, PIN_OUTPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x9cc, PIN_OUTPUT_PULLUP | MUX_MODE2) /* cam1 data 9 -> DSS DATA 16 */
AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
AM4372_IOPAD(0xa20, PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
uart0_pins_default: uart0_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0)
AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0)
AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa6c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_cs0.i2c1_sda */
AM4372_IOPAD(0xa60, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE1) /* spi2_sclk.i2c1_scl */
>;
};
i2c2_pins: i2c2_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
>;
};
usb2_phy1_default: usb2_phy1_default {
pinctrl-single,pins = <
AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
usb2_phy2_default: usb2_phy2_default {
pinctrl-single,pins = <
AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom_base: at24@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
};
&mmc1 {
status = "okay";
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vsb_3v3>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&dss_pinctrl_default>;
port {
dpi_lcd_out: endpoint@0 {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_default>;
};
&dwc3_1 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_phy1_default>;
};
&dwc3_2 {
pinctrl-names = "default";
pinctrl-0 = <&usb2_phy2_default>;
};
&lcd0 {
enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
&gpio4 28 GPIO_ACTIVE_HIGH>;
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_lcd_out>;
data-lines = <24>;
};
};
};

351
sys/gnu/dts/arm/am437x-sk-evm.dts
View File

@ -24,6 +24,13 @@
display0 = &lcd0;
};
/* fixed 32k external oscillator clock */
clk_32k_rtc: clk_32k_rtc {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@ -32,14 +39,29 @@
};
sound {
compatible = "ti,da830-evm-audio";
ti,model = "AM437x-SK-EVM";
ti,audio-codec = <&tlv320aic3106>;
ti,mcasp-controller = <&mcasp1>;
ti,codec-clock-rate = <24000000>;
ti,audio-routing =
compatible = "simple-audio-card";
simple-audio-card,name = "AM437x-SK-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT";
"Headphone Jack", "HPROUT",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
system-clock-frequency = <24000000>;
};
};
matrix_keypad: matrix_keypad@0 {
@ -49,7 +71,7 @@
pinctrl-0 = <&matrix_keypad_pins>;
debounce-delay-ms = <5>;
col-scan-delay-us = <1500>;
col-scan-delay-us = <5>;
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
@ -135,250 +157,259 @@
&am43xx_pinmux {
matrix_keypad_pins: matrix_keypad_pins {
pinctrl-single,pins = <
0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
>;
};
leds_pins: leds_pins {
pinctrl-single,pins = <
0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
>;
};
i2c0_pins: i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
i2c1_pins: i2c1_pins {
pinctrl-single,pins = <
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
>;
};
edt_ft5306_ts_pins: edt_ft5306_ts_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
>;
};
vpfe0_pins_default: vpfe0_pins_default {
pinctrl-single,pins = <
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
>;
};
vpfe0_pins_sleep: vpfe0_pins_sleep {
pinctrl-single,pins = <
0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
/* Slave 2 */
0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
/* Slave 2 reset value */
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
dss_pins: dss_pins {
pinctrl-single,pins = <
0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
0x024 (PIN_OUTPUT | MUX_MODE1)
0x028 (PIN_OUTPUT | MUX_MODE1)
0x02c (PIN_OUTPUT | MUX_MODE1)
0x030 (PIN_OUTPUT | MUX_MODE1)
0x034 (PIN_OUTPUT | MUX_MODE1)
0x038 (PIN_OUTPUT | MUX_MODE1)
0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
0x0a4 (PIN_OUTPUT | MUX_MODE0)
0x0a8 (PIN_OUTPUT | MUX_MODE0)
0x0ac (PIN_OUTPUT | MUX_MODE0)
0x0b0 (PIN_OUTPUT | MUX_MODE0)
0x0b4 (PIN_OUTPUT | MUX_MODE0)
0x0b8 (PIN_OUTPUT | MUX_MODE0)
0x0bc (PIN_OUTPUT | MUX_MODE0)
0x0c0 (PIN_OUTPUT | MUX_MODE0)
0x0c4 (PIN_OUTPUT | MUX_MODE0)
0x0c8 (PIN_OUTPUT | MUX_MODE0)
0x0cc (PIN_OUTPUT | MUX_MODE0)
0x0d0 (PIN_OUTPUT | MUX_MODE0)
0x0d4 (PIN_OUTPUT | MUX_MODE0)
0x0d8 (PIN_OUTPUT | MUX_MODE0)
0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)
AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)
AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
>;
};
qspi_pins: qspi_pins {
pinctrl-single,pins = <
0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>;
};
mcasp1_pins_sleep: mcasp1_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
lcd_pins: lcd_pins {
pinctrl-single,pins = <
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
>;
};
usb1_pins: usb1_pins {
pinctrl-single,pins = <
0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
>;
};
usb2_pins: usb2_pins {
pinctrl-single,pins = <
0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
>;
};
};
@ -392,7 +423,6 @@
tps@24 {
compatible = "ti,tps65218";
reg = <0x24>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
@ -472,15 +502,16 @@
reg = <0x38>;
interrupt-parent = <&gpio0>;
interrupts = <31 0>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
};
tlv320aic3106: tlv320aic3106@1b {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@ -532,7 +563,7 @@
vmmc-supply = <&dcdc4>;
bus-width = <4>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&usb2_phy1 {
@ -641,8 +672,10 @@
};
&mcasp1 {
pinctrl-names = "default";
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
@ -671,6 +704,8 @@
};
&rtc {
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
clock-names = "ext-clk", "int-clk";
status = "okay";
};

555
sys/gnu/dts/arm/am43x-epos-evm.dts
View File

@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
/ {
model = "TI AM43x EPOS EVM";
@ -31,21 +32,18 @@
enable-active-high;
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
/*
* SelLCDorHDMI, LOW to select HDMI. This is not really the
* panel's enable GPIO, but we don't have HDMI driver support nor
* support to switch between two displays, so using this gpio as
* panel's enable should be safe.
*/
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@ -69,218 +67,6 @@
};
};
am43xx_pinmux: pinmux@44e10800 {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
qspi1_default: qspi1_default {
pinctrl-single,pins = <
0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
>;
};
pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
>;
};
hdq_pins: pinmux_hdq_pins {
pinctrl-single,pins = <
0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
>;
};
dss_pins: dss_pins {
pinctrl-single,pins = <
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
>;
};
lcd_pins: lcd_pins {
pinctrl-single,pins = <
/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
vpfe1_pins_default: vpfe1_pins_default {
pinctrl-single,pins = <
0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
>;
};
vpfe1_pins_sleep: vpfe1_pins_sleep {
pinctrl-single,pins = <
0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
@ -320,6 +106,268 @@
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM43-EPOS-EVM";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Speaker", "Speaker";
simple-audio-card,routing =
"MIC1LP", "Microphone Jack",
"MIC1RP", "Microphone Jack",
"MIC1LP", "MICBIAS",
"MIC1RP", "MICBIAS",
"Headphone Jack", "HPL",
"Headphone Jack", "HPR",
"Speaker", "SPL",
"Speaker", "SPR";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp1>;
system-clock-frequency = <12000000>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3111>;
system-clock-frequency = <12000000>;
};
};
};
&am43xx_pinmux {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};
ecap0_pins: backlight_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
>;
};
spi0_pins: pinmux_spi0_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
>;
};
qspi1_default: qspi1_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
>;
};
pixcir_ts_pins: pixcir_ts_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
>;
};
hdq_pins: pinmux_hdq_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
>;
};
dss_pins: dss_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
>;
};
display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
vpfe1_pins_default: vpfe1_pins_default {
pinctrl-single,pins = <
AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
>;
};
vpfe1_pins_sleep: vpfe1_pins_sleep {
pinctrl-single,pins = <
AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
>;
};
mcasp1_sleep_pins: mcasp1_sleep_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
};
&mmc1 {
@ -328,7 +376,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&mac {
@ -369,7 +417,6 @@
reg = <0x24>;
compatible = "ti,tps65218";
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <2>;
@ -400,6 +447,15 @@
regulator-always-on;
};
dcdc4: regulator-dcdc4 {
compatible = "ti,tps65218-dcdc4";
regulator-name = "vdcdc4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
@ -442,6 +498,23 @@
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
};
tlv320aic3111: tlv320aic3111@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3111";
reg = <0x18>;
status = "okay";
ai31xx-micbias-vg = <MICBIAS_2_0V>;
/* Regulators */
HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
SPRVDD-supply = <&vbat>; /* vbat */
SPLVDD-supply = <&vbat>; /* vbat */
AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
};
};
&i2c2 {
@ -459,7 +532,21 @@
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
p1 {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
* High: LCD display with analog audio via aic3111 codec
*/
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "SelLCDorHDMI";
};
};
&gpio3 {
@ -687,3 +774,21 @@
};
};
};
&mcasp1 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
pinctrl-1 = <&mcasp1_sleep_pins>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

31
sys/gnu/dts/arm/am43xx-clocks.dtsi
View File

@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@ -107,7 +107,7 @@
ehrpwm0_tbclk: ehrpwm0_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
@ -115,7 +115,7 @@
ehrpwm1_tbclk: ehrpwm1_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
@ -123,7 +123,7 @@
ehrpwm2_tbclk: ehrpwm2_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
@ -131,7 +131,7 @@
ehrpwm3_tbclk: ehrpwm3_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
@ -139,7 +139,7 @@
ehrpwm4_tbclk: ehrpwm4_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
@ -147,7 +147,7 @@
ehrpwm5_tbclk: ehrpwm5_tbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m2_ck>;
clocks = <&l4ls_gclk>;
ti,bit-shift = <6>;
reg = <0x0664>;
};
@ -259,6 +259,14 @@
ti,invert-autoidle-bit;
};
mpu_periphclk: mpu_periphclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll_mpu_m2_ck>;
clock-mult = <1>;
clock-div = <2>;
};
dpll_ddr_ck: dpll_ddr_ck {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
@ -486,6 +494,15 @@
reg = <0x4238>;
};
dpll_clksel_mac_clk: dpll_clksel_mac_clk {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5_ck>;
reg = <0x4234>;
ti,bit-shift = <2>;
ti,dividers = <2>, <5>;
};
clk_32k_mosc_ck: clk_32k_mosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";

467
sys/gnu/dts/arm/am57xx-beagle-x15.dts
View File

@ -8,7 +8,6 @@
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
@ -19,6 +18,8 @@
aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
rtc2 = &rtc;
display0 = &hdmi0;
};
memory {
@ -34,6 +35,14 @@
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
compatible = "regulator-fixed";
regulator-name = "aic_dvdd_fixed";
vin-supply = <&vdd_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
@ -84,9 +93,10 @@
gpio_fan: gpio_fan {
/* Based on 5v 500mA AFB02505HHB */
compatible = "gpio-fan";
gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0>,
<13000 1>;
#cooling-cells = <2>;
};
extcon_usb1: extcon_usb1 {
@ -96,101 +106,172 @@
pinctrl-0 = <&extcon_usb1_pins>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
pinctrl-names = "default";
pinctrl-0 = <&extcon_usb2_pins>;
pinctrl-0 = <&tpd12s015_pins>;
gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */
<&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC2L", "Line In",
"MIC2R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3104>;
clocks = <&clkout2_clk>;
};
};
};
&dra7_pmx_core {
leds_pins_default: leds_pins_default {
pinctrl-single,pins = <
0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
DRA7XX_CORE_IOPAD(0x37a8, PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
DRA7XX_CORE_IOPAD(0x37ac, PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
DRA7XX_CORE_IOPAD(0x37c0, PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
DRA7XX_CORE_IOPAD(0x37c4, PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
>;
};
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
>;
};
hdmi_pins: pinmux_hdmi_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
i2c3_pins_default: i2c3_pins_default {
pinctrl-single,pins = <
0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
>;
};
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
cpsw_pins_default: cpsw_pins_default {
pinctrl-single,pins = <
/* Slave 1 */
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
/* Slave 2 */
0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
>;
};
@ -198,83 +279,115 @@
cpsw_pins_sleep: cpsw_pins_sleep {
pinctrl-single,pins = <
/* Slave 1 */
0x250 (PIN_INPUT | MUX_MODE15)
0x254 (PIN_INPUT | MUX_MODE15)
0x258 (PIN_INPUT | MUX_MODE15)
0x25c (PIN_INPUT | MUX_MODE15)
0x260 (PIN_INPUT | MUX_MODE15)
0x264 (PIN_INPUT | MUX_MODE15)
0x268 (PIN_INPUT | MUX_MODE15)
0x26c (PIN_INPUT | MUX_MODE15)
0x270 (PIN_INPUT | MUX_MODE15)
0x274 (PIN_INPUT | MUX_MODE15)
0x278 (PIN_INPUT | MUX_MODE15)
0x27c (PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
/* Slave 2 */
0x198 (PIN_INPUT | MUX_MODE15)
0x19c (PIN_INPUT | MUX_MODE15)
0x1a0 (PIN_INPUT | MUX_MODE15)
0x1a4 (PIN_INPUT | MUX_MODE15)
0x1a8 (PIN_INPUT | MUX_MODE15)
0x1ac (PIN_INPUT | MUX_MODE15)
0x1b0 (PIN_INPUT | MUX_MODE15)
0x1b4 (PIN_INPUT | MUX_MODE15)
0x1b8 (PIN_INPUT | MUX_MODE15)
0x1bc (PIN_INPUT | MUX_MODE15)
0x1c0 (PIN_INPUT | MUX_MODE15)
0x1c4 (PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
>;
};
davinci_mdio_pins_default: davinci_mdio_pins_default {
pinctrl-single,pins = <
/* MDIO */
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
>;
};
davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
pinctrl-single,pins = <
0x23c (PIN_INPUT | MUX_MODE15)
0x240 (PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
>;
};
tps659038_pins_default: tps659038_pins_default {
pinctrl-single,pins = <
0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
>;
};
tmp102_pins_default: tmp102_pins_default {
pinctrl-single,pins = <
0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
>;
};
mcp79410_pins_default: mcp79410_pins_default {
pinctrl-single,pins = <
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
extcon_usb1_pins: extcon_usb1_pins {
pinctrl-single,pins = <
0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
>;
};
extcon_usb2_pins: extcon_usb2_pins {
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
DRA7XX_CORE_IOPAD(0x3770, PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */
>;
};
clkout2_pins_default: clkout2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */
>;
};
clkout2_pins_sleep: clkout2_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */
>;
};
mcasp3_pins_default: mcasp3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
>;
};
mcasp3_pins_sleep: mcasp3_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
>;
};
};
@ -353,11 +466,12 @@
/* SMPS9 unused */
ldo1_reg: ldo1 {
/* VDD_SD */
/* VDD_SD / VDDSHV8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
@ -370,7 +484,7 @@
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
/* VDDA_1V8_PHYA */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -378,6 +492,15 @@
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_1V8_PHYB */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
@ -433,6 +556,14 @@
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb2: tps659038_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
id-gpios = <&gpio7 24 GPIO_ACTIVE_HIGH>;
};
};
tmp102: tmp102@48 {
@ -442,6 +573,23 @@
pinctrl-0 = <&tmp102_pins_default>;
interrupt-parent = <&gpio7>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
#thermal-sensor-cells = <1>;
};
tlv320aic3104: tlv320aic3104@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3104";
reg = <0x18>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&clkout2_pins_default>;
pinctrl-1 = <&clkout2_pins_sleep>;
status = "okay";
adc-settle-ms = <40>;
AVDD-supply = <&vdd_3v3>;
IOVDD-supply = <&vdd_3v3>;
DRVDD-supply = <&vdd_3v3>;
DVDD-supply = <&aic_dvdd>;
};
};
@ -454,8 +602,9 @@
mcp_rtc: rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
<&dra7_pmx_core 0x424>;
interrupt-names = "irq", "wakeup";
pinctrl-names = "default";
pinctrl-0 = <&mcp79410_pins_default>;
@ -477,8 +626,8 @@
&uart3 {
status = "okay";
interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x248>;
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3f8>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
@ -517,10 +666,8 @@
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
pbias-supply = <&pbias_mmc_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};
&mmc2 {
@ -543,6 +690,10 @@
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
@ -558,5 +709,119 @@
};
&usb2 {
/*
* Stand alone usage is peripheral only.
* However, with some resistor modifications
* this port can be used via expansion connectors
* as "host" or "dual-role". If so, provide
* the necessary dr_mode override in the expansion
* board's DT.
*/
dr_mode = "peripheral";
};
&cpu_trips {
cpu_alert1: cpu_alert1 {
temperature = <50000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
};
&cpu_cooling_maps {
map1 {
trip = <&cpu_alert1>;
cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
&thermal_zones {
board_thermal: board_thermal {
polling-delay-passive = <1250>; /* milliseconds */
polling-delay = <1500>; /* milliseconds */
/* sensor ID */
thermal-sensors = <&tmp102 0>;
board_trips: trips {
board_alert0: board_alert {
temperature = <40000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "active";
};
board_crit: board_crit {
temperature = <105000>; /* millicelsius */
hysteresis = <0>; /* millicelsius */
type = "critical";
};
};
board_cooling_maps: cooling-maps {
map0 {
trip = <&board_alert0>;
cooling-device =
<&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
&dss {
status = "ok";
vdda_video-supply = <&ldoln_reg>;
};
&hdmi {
status = "ok";
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&pcie1 {
gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins_default>;
pinctrl-1 = <&mcasp3_pins_sleep>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};

617
sys/gnu/dts/arm/am57xx-cl-som-am57x.dts Normal file
View File

@ -0,0 +1,617 @@
/*
* Support for CompuLab CL-SOM-AM57x System-on-Module
*
* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "dra74x.dtsi"
/ {
model = "CompuLab CL-SOM-AM57x";
compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB - minimal configuration */
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&leds_pins_default>;
led@0 {
label = "cl-som-am57x:green";
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
vdd_3v3: fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ads7846reg: fixedregulator-ads7846-reg {
compatible = "regulator-fixed";
regulator-name = "ads7846-reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink0_master>;
simple-audio-card,frame-master = <&dailink0_master>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Microphone", "Microphone Jack",
"Line", "Line Jack";
simple-audio-card,routing =
"Headphone Jack", "RHPOUT",
"Headphone Jack", "LHPOUT",
"LLINEIN", "Line Jack",
"MICIN", "Mic Bias",
"Mic Bias", "Microphone Jack";
dailink0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};
simple-audio-card,codec {
sound-dai = <&wm8731>;
system-clock-frequency = <12000000>;
};
};
};
&dra7_pmx_core {
leds_pins_default: leds_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
>;
};
i2c1_pins_default: i2c1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
>;
};
i2c3_pins_default: i2c3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
>;
};
i2c4_pins_default: i2c4_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
>;
};
tps659038_pins_default: tps659038_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d0 */
DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d1 */
DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
>;
};
cpsw_pins_default: cpsw_pins_default {
pinctrl-single,pins = <
/* Slave at addr 0x0 */
DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tclk */
DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_tctl */
DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3 */
DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td2 */
DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td1 */
DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td0 */
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rclk */
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rctl */
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd3 */
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd2 */
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd1 */
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rgmii0_rd0 */
/* Slave at addr 0x1 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_tclk */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_pins_sleep: cpsw_pins_sleep {
pinctrl-single,pins = <
/* Slave 1 */
DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15)
>;
};
davinci_mdio_pins_default: davinci_mdio_pins_default {
pinctrl-single,pins = <
/* MDIO */
DRA7XX_CORE_IOPAD(0x3590, PIN_OUTPUT_PULLUP | MUX_MODE3)/* vin2a_d10.mdio_mclk */
DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT_PULLUP | MUX_MODE3) /* vin2a_d11.mdio_d */
>;
};
davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3590, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3594, PIN_INPUT | MUX_MODE15)
>;
};
ads7846_pins: pinmux_ads7846_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3464, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpmc_a9.gpio1_31 */
>;
};
mcasp3_pins_default: mcasp3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */
>;
};
mcasp3_pins_sleep: mcasp3_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15)
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_default>;
clock-frequency = <400000>;
};
&i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins_default>;
clock-frequency = <400000>;
};
&i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_default>;
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&tps659038_pins_default>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
regulator-name = "smps12";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_DDR */
regulator-name = "smps3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE */
regulator-name = "smps45";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_GPU */
regulator-name = "smps6";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* VDD_CORE */
regulator-name = "smps7";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1160000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* VDD_IVA */
regulator-name = "smps8";
regulator-min-microvolt = < 850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps9_reg: smps9 {
/* PMIC_3V3 */
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: ldo1 {
/* VDD_SD / VDDSHV8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
/* VDD_1V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHYA - supplies VDDA_SATA, VDDA_USB1/2/3 */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_1V8_PHYB - supplies VDDA_HDMI, VDDA_PCIE/0/1 */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo9_reg: ldo9 {
/* VDD_RTC */
regulator-name = "ldo9";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
/* regen1 not used */
};
};
tps659038_pwr_button: tps659038_pwr_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps659038>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
ti,palmas-long-press-seconds = <12>;
};
tps659038_gpio: tps659038_gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};
rtc0: rtc@56 {
compatible = "emmicro,em3027";
reg = <0x56>;
};
eeprom_module: atmel@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
wm8731: wm8731@1a {
#sound-dai-cells = <0>;
compatible = "wlf,wm8731";
reg = <0x1a>;
status = "okay";
};
};
&cpu0 {
cpu0-supply = <&smps12_reg>;
voltage-tolerance = <1>;
};
&sata {
status = "okay";
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
status = "okay";
};
};
&mmc2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&vdd_3v3>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <20000000>;
spi_flash: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80", "jedec,spi-nor";
reg = <0>; /* CS0 */
spi-max-frequency = <20000000>;
partition@0 {
label = "uboot";
reg = <0x0 0xc0000>;
};
partition@c0000 {
label = "uboot environment";
reg = <0xc0000 0x40000>;
};
partition@100000 {
label = "reserved";
reg = <0x100000 0x0>;
};
};
/* touch controller */
ads7846@0 {
pinctrl-names = "default";
pinctrl-0 = <&ads7846_pins>;
compatible = "ti,ads7846";
vcc-supply = <&ads7846reg>;
reg = <1>; /* CS1 */
spi-max-frequency = <1500000>;
interrupt-parent = <&gpio1>;
interrupts = <31 0>;
pendown-gpio = <&gpio1 31 0>;
ti,x-min = /bits/ 16 <0x0>;
ti,x-max = /bits/ 16 <0x0fff>;
ti,y-min = /bits/ 16 <0x0>;
ti,y-max = /bits/ 16 <0x0fff>;
ti,x-plate-ohms = /bits/ 16 <180>;
ti,pressure-max = /bits/ 16 <255>;
ti,debounce-max = /bits/ 16 <30>;
ti,debounce-tol = /bits/ 16 <10>;
ti,debounce-rep = /bits/ 16 <1>;
linux,wakeup;
};
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_pins_default>;
pinctrl-1 = <&cpsw_pins_sleep>;
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <0>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_pins_default>;
pinctrl-1 = <&davinci_mdio_pins_sleep>;
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
};
&usb2 {
dr_mode = "peripheral";
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins_default>;
pinctrl-1 = <&mcasp3_pins_sleep>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&gpio3 {
status = "okay";
ti,no-reset-on-init;
};
&gpio2 {
status = "okay";
ti,no-reset-on-init;
};

179
sys/gnu/dts/arm/am57xx-sbc-am57x.dts Normal file
View File

@ -0,0 +1,179 @@
/*
* Support for CompuLab SBC-AM57x single board computer
*
* Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
#include "am57xx-cl-som-am57x.dts"
#include "compulab-sb-som.dtsi"
/ {
model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
aliases {
display0 = &lcd0;
display1 = &hdmi;
};
};
&dra7_pmx_core {
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1_sdcd.gpio6_27 */
DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14) /* mmc1_sdwp.gpio6_28 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
i2c5_pins_default: i2c5_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
lcd_pins_default: lcd_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14) /* vin2a_vsync0.gpio4_0 */
>;
};
hdmi_pins: pinmux_hdmi_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
hdmi_conn_pins: pinmux_hdmi_conn_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14) /* spi1_cs2.gpio7_12 */
>;
};
};
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3f8>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
};
&usb1 {
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins_default>;
clock-frequency = <400000>;
eeprom_base: atmel@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&dss {
status = "ok";
vdda_video-supply = <&ldoln_reg>;
port {
dpi_lcd_out: endpoint@0 {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
};
};
&lcd0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_default>;
enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
&gpio4 0 GPIO_ACTIVE_HIGH>;
port {
lcd_in: endpoint {
remote-endpoint = <&dpi_lcd_out>;
data-lines = <24>;
};
};
};
&hdmi {
status = "ok";
vdda-supply = <&ldo4_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
lanes = <1 0 3 2 5 4 7 6>;
};
};
};
&hdmi_conn {
pinctrl-names = "default";
pinctrl-0 = <&hdmi_conn_pins>;
hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
};

6
sys/gnu/dts/arm/animeo_ip.dts
View File

@ -155,21 +155,21 @@
label = "keyswitch_in";
gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
linux,code = <28>;
gpio-key,wakeup;
wakeup-source;
};
error_in {
label = "error_in";
gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
linux,code = <29>;
gpio-key,wakeup;
wakeup-source;
};
btn {
label = "btn";
gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
linux,code = <31>;
gpio-key,wakeup;
wakeup-source;
};
};
};

2
sys/gnu/dts/arm/arm-realview-pb1176.dts
View File

@ -114,7 +114,7 @@
ranges;
syscon: syscon@10000000 {
compatible = "arm,realview-pb1176-syscon", "syscon";
compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
led@08.0 {

681
sys/gnu/dts/arm/arm-realview-pb11mp.dts Normal file
View File

@ -0,0 +1,681 @@
/*
* Copyright 2015 Linaro Ltd
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include "skeleton.dtsi"
/ {
model = "ARM RealView PB11MPcore";
compatible = "arm,realview-pb11mp";
chosen { };
aliases {
serial0 = &pb11mp_serial0;
serial1 = &pb11mp_serial1;
serial2 = &pb11mp_serial2;
serial3 = &pb11mp_serial3;
};
memory {
/*
* The PB11MPCore has 512 MiB memory @ 0x70000000
* and the first 256 are also remapped @ 0x00000000
*/
reg = <0x70000000 0x20000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "arm,realview-smp";
MP11_0: cpu@0 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
reg = <0>;
next-level-cache = <&L2>;
};
MP11_1: cpu@1 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
reg = <1>;
next-level-cache = <&L2>;
};
MP11_2: cpu@2 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
reg = <2>;
next-level-cache = <&L2>;
};
MP11_3: cpu@3 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
reg = <3>;
next-level-cache = <&L2>;
};
};
/* Primary TestChip GIC synthesized with the CPU */
intc_tc11mp: interrupt-controller@1f000100 {
compatible = "arm,tc11mp-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0x1f001000 0x1000>,
<0x1f000100 0x100>;
};
L2: l2-cache {
compatible = "arm,l220-cache";
reg = <0x1f002000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
<0 30 IRQ_TYPE_LEVEL_HIGH>,
<0 31 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
/*
* Override default cache size, sets and
* associativity as these may be erroneously set
* up by boot loader(s), probably for safety
* since th outer sync operation can cause the
* cache to hang unless disabled.
*/
cache-size = <1048576>; // 1MB
cache-sets = <4096>;
cache-line-size = <32>;
arm,shared-override;
arm,parity-enable;
arm,outer-sync-disable;
};
scu@1f000000 {
compatible = "arm,arm11mp-scu";
reg = <0x1f000000 0x100>;
};
timer@1f000600 {
compatible = "arm,arm11mp-twd-timer";
reg = <0x1f000600 0x20>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <1 13 0xf04>;
};
watchdog@1f000620 {
compatible = "arm,arm11mp-twd-wdt";
reg = <0x1f000620 0x20>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <1 14 0xf04>;
};
/* PMU with one IRQ line per core */
pmu {
compatible = "arm,arm11mpcore-pmu";
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
<0 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 IRQ_TYPE_LEVEL_HIGH>,
<0 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
};
/* The voltage to the MMC card is hardwired at 3.3V */
vmmc: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
veth: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
xtal24mhz: xtal24mhz@24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
timclk: timclk@1M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
mclk: mclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
kmiclk: kmiclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
sspclk: sspclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
uartclk: uartclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
wdogclk: wdogclk@24M {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clock-mult = <1>;
clocks = <&xtal24mhz>;
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
flash0@40000000 {
/* 2 * 32MiB NOR Flash memory */
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0x40000000 0x04000000>;
bank-width = <4>;
};
flash1@44000000 {
// 2 * 32MiB NOR Flash memory
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0x44000000 0x04000000>;
bank-width = <4>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,realview-pb11mp-soc", "simple-bus";
regmap = <&pb11mp_syscon>;
ranges;
pb11mp_syscon: syscon@10000000 {
compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
reg = <0x10000000 0x1000>;
led@08.0 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x01>;
label = "versatile:0";
linux,default-trigger = "heartbeat";
default-state = "on";
};
led@08.1 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x02>;
label = "versatile:1";
linux,default-trigger = "mmc0";
default-state = "off";
};
led@08.2 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x04>;
label = "versatile:2";
linux,default-trigger = "cpu0";
default-state = "off";
};
led@08.3 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x08>;
label = "versatile:3";
linux,default-trigger = "cpu1";
default-state = "off";
};
led@08.4 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x10>;
label = "versatile:4";
linux,default-trigger = "cpu2";
default-state = "off";
};
led@08.5 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x20>;
label = "versatile:5";
linux,default-trigger = "cpu3";
default-state = "off";
};
led@08.6 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x40>;
label = "versatile:6";
default-state = "off";
};
led@08.7 {
compatible = "register-bit-led";
offset = <0x08>;
mask = <0x80>;
label = "versatile:7";
default-state = "off";
};
oscclk0: osc0@0c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x0C>;
clocks = <&xtal24mhz>;
};
oscclk1: osc1@10 {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x10>;
clocks = <&xtal24mhz>;
};
oscclk2: osc2@14 {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x14>;
clocks = <&xtal24mhz>;
};
oscclk3: osc3@18 {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x18>;
clocks = <&xtal24mhz>;
};
oscclk4: osc4@1c {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0x1c>;
clocks = <&xtal24mhz>;
};
oscclk5: osc5@d4 {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd4>;
clocks = <&xtal24mhz>;
};
oscclk6: osc6@d8 {
compatible = "arm,syscon-icst307";
#clock-cells = <0>;
lock-offset = <0x20>;
vco-offset = <0xd8>;
clocks = <&xtal24mhz>;
};
};
sp810_syscon: sysctl@10001000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x10001000 0x1000>;
clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
clock-names = "refclk", "timclk", "apb_pclk";
#clock-cells = <1>;
clock-output-names = "timerclk0",
"timerclk1",
"timerclk2",
"timerclk3";
assigned-clocks = <&sp810_syscon 0>,
<&sp810_syscon 1>,
<&sp810_syscon 2>,
<&sp810_syscon 3>;
assigned-clock-parents = <&timclk>,
<&timclk>,
<&timclk>,
<&timclk>;
};
i2c0: i2c@10002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,versatile-i2c";
reg = <0x10002000 0x1000>;
rtc@68 {
compatible = "dallas,ds1338";
reg = <0x68>;
};
};
aaci: aaci@10004000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x10004000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
mci: mmcsd@10005000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x10005000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
<0 15 IRQ_TYPE_LEVEL_HIGH>;
/* Due to frequent FIFO overruns, use just 500 kHz */
max-frequency = <500000>;
bus-width = <4>;
cap-sd-highspeed;
cap-mmc-highspeed;
clocks = <&mclk>, <&pclk>;
clock-names = "mclk", "apb_pclk";
vmmc-supply = <&vmmc>;
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
};
kmi0: kmi@10006000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x10006000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&kmiclk>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
kmi1: kmi@10007000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x10007000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&kmiclk>, <&pclk>;
clock-names = "KMIREFCLK", "apb_pclk";
};
pb11mp_serial0: serial@10009000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x10009000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
pb11mp_serial1: serial@1000a000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1000a000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
pb11mp_serial2: serial@1000b000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1000b000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
pb11mp_serial3: serial@1000c000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x1000c000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uartclk>, <&pclk>;
clock-names = "uartclk", "apb_pclk";
};
ssp@1000d000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x1000d000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sspclk>, <&pclk>;
clock-names = "SSPCLK", "apb_pclk";
};
watchdog@1000f000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x1000f000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
status = "disabled";
};
watchdog@10010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x10010000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&wdogclk>, <&pclk>;
clock-names = "wdogclk", "apb_pclk";
};
timer01: timer@10011000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10011000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
arm,sp804-has-irq = <1>;
clocks = <&sp810_syscon 0>,
<&sp810_syscon 1>,
<&pclk>;
clock-names = "timerclk0",
"timerclk1",
"apb_pclk";
};
timer23: timer@10012000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10012000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
arm,sp804-has-irq = <1>;
clocks = <&sp810_syscon 2>,
<&sp810_syscon 3>,
<&pclk>;
clock-names = "timerclk2",
"timerclk3",
"apb_pclk";
};
gpio0: gpio@10013000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x10013000 0x1000>;
gpio-controller;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio1: gpio@10014000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x10014000 0x1000>;
gpio-controller;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
gpio2: gpio@10015000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x10015000 0x1000>;
gpio-controller;
interrupt-parent = <&intc_pb11mp>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
rtc: rtc@10017000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x10017000 0x1000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pclk>;
clock-names = "apb_pclk";
};
timer45: timer@10018000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10018000 0x1000>;
clocks = <&timclk>, <&pclk>;
clock-names = "timer", "apb_pclk";
status = "disabled";
};
timer67: timer@10019000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x10019000 0x1000>;
clocks = <&timclk>, <&pclk>;
clock-names = "timer", "apb_pclk";
status = "disabled";
};
clcd@10020000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x10020000 0x1000>;
interrupt-parent = <&intc_pb11mp>;
interrupt-names = "combined";
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&oscclk4>, <&pclk>;
clock-names = "clcdclk", "apb_pclk";
max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
port {
clcd_pads: endpoint {
remote-endpoint = <&clcd_panel>;
arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
};
};
panel {
compatible = "panel-dpi";
port {
clcd_panel: endpoint {
remote-endpoint = <&clcd_pads>;
};
};
panel-timing {
clock-frequency = <63500127>;
hactive = <1024>;
hback-porch = <152>;
hfront-porch = <48>;
hsync-len = <104>;
vactive = <768>;
vback-porch = <23>;
vfront-porch = <3>;
vsync-len = <4>;
};
};
};
/*
* This GIC on the Platform Baseboard is cascaded off the
* TestChip GIC
*/
intc_pb11mp: interrupt-controller@1e000000 {
compatible = "arm,arm11mp-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0x1e001000 0x1000>,
<0x1e000000 0x100>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
};
/* SMSC 9118 ethernet with PHY and EEPROM */
ethernet@4e000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <0x4e000000 0x10000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
vdd33a-supply = <&veth>;
vddvario-supply = <&veth>;
};
usb@4f000000 {
compatible = "nxp,usb-isp1761";
reg = <0x4f000000 0x20000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
port1-otg;
};
};
};

18
sys/gnu/dts/arm/armada-370-db.dts
View File

@ -45,6 +45,15 @@
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
@ -55,7 +64,7 @@
compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -64,8 +73,9 @@
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
serial@12000 {
@ -153,7 +163,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
compatible = "mx25l25635e", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};

358
sys/gnu/dts/arm/armada-370-dlink-dns327l.dts Normal file
View File

@ -0,0 +1,358 @@
/*
* Device Tree file for D-Link DNS-327L
*
* Copyright (C) 2015, Andrew Andrianov <andrew@ncrmnt.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* Remaining unsolved:
* There's still some unknown device on i2c address 0x13
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "armada-370.dtsi"
/ {
model = "D-Link DNS-327L";
compatible = "dlink,dns327l",
"marvell,armada370",
"marvell,armada-370-xp";
chosen {
stdout-path = &uart0;
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MiB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
nand@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
/* 1.0 MiB */
reg = <0x0000000 0x100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
/* 128 KiB */
reg = <0x100000 0x20000>;
read-only;
};
partition@120000 {
label = "uImage";
/* 7 MiB */
reg = <0x120000 0x700000>;
};
partition@820000 {
label = "ubifs";
/* ~ 84 MiB */
reg = <0x820000 0x54e0000>;
};
/* Hardcoded into stock bootloader */
partition@5d00000 {
label = "failsafe-uImage";
/* 5 MiB */
reg = <0x5d00000 0x500000>;
};
partition@6200000 {
label = "failsafe-fs";
/* 29 MiB */
reg = <0x6200000 0x1d00000>;
};
partition@7f00000 {
label = "bbt";
/* 1 MiB for BBT */
reg = <0x7f00000 0x100000>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <
&backup_button_pin
&power_button_pin
&reset_button_pin>;
pinctrl-names = "default";
power-button {
label = "Power Button";
linux,code = <KEY_POWER>;
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
backup-button {
label = "Backup Button";
linux,code = <KEY_COPY>;
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
};
reset-button {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <
&sata_l_amber_pin
&sata_r_amber_pin
&backup_led_pin
/* Ensure these are managed by hardware */
&sata_l_white_pin
&sata_r_white_pin>;
pinctrl-names = "default";
sata-r-amber-pin {
label = "dns327l:amber:sata-r";
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
sata-l-amber-pin {
label = "dns327l:amber:sata-l";
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
backup-led-pin {
label = "dns327l:white:usb";
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
usb_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-0 = <&xhci_pwr_pin>;
pinctrl-names = "default";
regulator-name = "USB3.0 Port Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-boot-on;
regulator-always-on;
gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
};
sata_r_power: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-0 = <&sata_r_pwr_pin>;
pinctrl-names = "default";
regulator-name = "SATA-R Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <2000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
sata_l_power: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
pinctrl-0 = <&sata_l_pwr_pin>;
pinctrl-names = "default";
regulator-name = "SATA-L Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <4000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
};
};
};
&pinctrl {
sata_l_white_pin: sata-l-white-pin {
marvell,pins = "mpp57";
marvell,function = "sata0";
};
sata_r_white_pin: sata-r-white-pin {
marvell,pins = "mpp55";
marvell,function = "sata1";
};
sata_r_amber_pin: sata-r-amber-pin {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
sata_l_amber_pin: sata-l-amber-pin {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
backup_led_pin: backup-led-pin {
marvell,pins = "mpp61";
marvell,function = "gpo";
};
xhci_pwr_pin: xhci-pwr-pin {
marvell,pins = "mpp13";
marvell,function = "gpio";
};
sata_r_pwr_pin: sata-r-pwr-pin {
marvell,pins = "mpp54";
marvell,function = "gpio";
};
sata_l_pwr_pin: sata-l-pwr-pin {
marvell,pins = "mpp56";
marvell,function = "gpio";
};
uart1_pins: uart1-pins {
marvell,pins = "mpp60", "mpp61";
marvell,function = "uart1";
};
power_button_pin: power-button-pin {
marvell,pins = "mpp65";
marvell,function = "gpio";
};
backup_button_pin: backup-button-pin {
marvell,pins = "mpp63";
marvell,function = "gpio";
};
reset_button_pin: reset-button-pin {
marvell,pins = "mpp64";
marvell,function = "gpio";
};
};
/* Serial console */
&uart0 {
status = "okay";
};
/* Connected to Weltrend MCU */
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
reg = <0>;
marvell,reg-init = <0x0 0x16 0x0 0x0002>,
<0x0 0x19 0x0 0x0077>,
<0x0 0x18 0x0 0x5747>;
};
};
&eth1 {
phy = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
};
&i2c0 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
status = "okay";
};

9
sys/gnu/dts/arm/armada-370-mirabox.dts
View File

@ -51,7 +51,7 @@
compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -61,7 +61,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -138,6 +139,10 @@
phy-mode = "rgmii-id";
};
crypto@90000 {
status = "okay";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";

13
sys/gnu/dts/arm/armada-370-netgear-rn102.dts
View File

@ -53,7 +53,7 @@
compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -63,7 +63,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -82,6 +83,12 @@
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
serial@12000 {
status = "okay";
};
@ -120,7 +127,7 @@
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
isil,irq2-can-wakeup-machine;
wakeup-source;
};
g762: g762@3e {

13
sys/gnu/dts/arm/armada-370-netgear-rn104.dts
View File

@ -53,7 +53,7 @@
compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -63,7 +63,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";
@ -82,6 +83,12 @@
};
internal-regs {
/* RTC is provided by Intersil ISL12057 I2C RTC chip */
rtc@10300 {
status = "disabled";
};
serial@12000 {
status = "okay";
};
@ -126,7 +133,7 @@
isl12057: isl12057@68 {
compatible = "isil,isl12057";
reg = <0x68>;
isil,irq2-can-wakeup-machine;
wakeup-source;
};
g762: g762@3e {

5
sys/gnu/dts/arm/armada-370-rd.dts
View File

@ -64,7 +64,7 @@
compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -74,7 +74,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
pcie-controller {
status = "okay";

36
sys/gnu/dts/arm/armada-370-seagate-nas-2bay.dts Normal file
View File

@ -0,0 +1,36 @@
/*
* Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate NAS 2-Bay
* Code name (board/PCB) : Dart 2-Bay
* Model name (case sticker) : SRPD20
* Material desc (product spec) : STCTxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"
/ {
model = "Seagate NAS 2-Bay (Dart, SRPD20)";
compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp";
gpio-fan {
gpio-fan,speed-map =
< 0 3
950 2
1400 1
1800 0>;
};
};

133
sys/gnu/dts/arm/armada-370-seagate-nas-4bay.dts Normal file
View File

@ -0,0 +1,133 @@
/*
* Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate NAS 4-Bay
* Code name (board/PCB) : Dart 4-Bay
* Model name (case sticker) : SRPD40
* Material desc (product spec) : STCUxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-nas-xbay.dtsi"
#include <dt-bindings/leds/leds-ns2.h>
/ {
model = "Seagate NAS 4-Bay (Dart, SRPD40)";
compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
soc {
pcie-controller {
/* SATA AHCI controller 88SE9170 */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
i2c@11000 {
/* I2C GPIO expander (PCA9554A) */
pca9554: pca9554@21 {
compatible = "nxp,pca9554";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
};
};
};
};
regulators {
regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA2 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>;
};
regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA3 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>;
};
};
gpio-leds {
red-sata2 {
label = "dart:red:sata2";
gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
};
red-sata3 {
label = "dart:red:sata3";
gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
};
};
leds-ns2 {
compatible = "lacie,ns2-leds";
white-sata2 {
label = "dart:white:sata2";
cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>;
slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>;
num-modes = <4>;
modes-map = <NS_V2_LED_SATA 0 0
NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 1 1>;
};
white-sata3 {
label = "dart:white:sata3";
cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>;
num-modes = <4>;
modes-map = <NS_V2_LED_SATA 0 0
NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 1 1>;
};
};
gpio-fan {
gpio-fan,speed-map =
< 0 3
800 2
1050 1
1300 0>;
};
};

231
sys/gnu/dts/arm/armada-370-seagate-nas-xbay.dtsi Normal file
View File

@ -0,0 +1,231 @@
/*
* Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Vincent Donnefort <vdonnefort@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
*/
#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 bridge ASM1042A */
pcie@2,0 {
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
i2c@11000 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
/* RTC - NXP 8563T (second source) */
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
interrupts = <110>;
};
/* RTC - MCP7940NT */
rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupts = <110>;
};
};
nand@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
partition@0 {
label = "u-boot";
reg = <0x0 0x300000>;
};
partition@300000 {
label = "device-tree";
reg = <0x300000 0x20000>;
};
partition@320000 {
label = "linux";
reg = <0x320000 0x2000000>;
};
partition@2320000 {
label = "rootfs";
reg = <0x2320000 0xdce0000>;
};
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA0 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA1 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
gpio-fan {
compatible = "gpio-fan";
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
&gpio2 1 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@2 {
label = "Backup button";
linux,code = <KEY_OPTION>;
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
white-power {
label = "dart:white:power";
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "timer";
};
red-power {
label = "dart:red:power";
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
};
red-sata0 {
label = "dart:red:sata0";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
red-sata1 {
label = "dart:red:sata1";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
};
};
gpio_poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
pinctrl-names = "default";
hdd0_led_sata_pin: hdd0-led-sata-pin {
marvell,pins = "mpp48";
marvell,function = "sata1";
};
hdd0_led_gpio_pin: hdd0-led-gpio-pin {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
hdd1_led_sata_pin: hdd1-led-sata-pin {
marvell,pins = "mpp57";
marvell,function = "sata0";
};
hdd1_led_gpio_pin: hdd1-led-gpio-pin {
marvell,pins = "mpp57";
marvell,function = "gpio";
};
};

51
sys/gnu/dts/arm/armada-370-seagate-personal-cloud-2bay.dts Normal file
View File

@ -0,0 +1,51 @@
/*
* Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate Personal Cloud 2-Bay
* Code name (board/PCB) : Cumulus Max
* Model name (case sticker) : SRN22C
* Material desc (product spec) : STCSxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"
/ {
model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)";
compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp";
soc {
internal-regs {
sata@a0000 {
status = "okay";
nr-ports = <2>;
};
};
};
regulators {
regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA1 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
};
};
};

37
sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dts Normal file
View File

@ -0,0 +1,37 @@
/*
* Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* Here are some information allowing to identify the device:
*
* Product name : Seagate Personal Cloud
* Code name (board/PCB) : Cumulus
* Model name (case sticker) : SRN21C
* Material desc (product spec) : STCRxxxxxxx
*/
/dts-v1/;
#include "armada-370-seagate-personal-cloud.dtsi"
/ {
model = "Seagate Personal Cloud (Cumulus, SRN21C)";
compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp";
soc {
internal-regs {
sata@a0000 {
status = "okay";
nr-ports = <1>;
};
};
};
};

178
sys/gnu/dts/arm/armada-370-seagate-personal-cloud.dtsi Normal file
View File

@ -0,0 +1,178 @@
/*
* Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
* (Armada 370 SoC).
*
* Copyright (C) 2015 Seagate
*
* Author: Simon Guinot <simon.guinot@sequanux.org>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/*
* TODO: add support for the white SATA LED.
*/
#include "armada-370.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* USB 3.0 Bridge ASM1042A */
pcie@1,0 {
status = "okay";
};
};
internal-regs {
coherency-fabric@20200 {
broken-idle;
};
serial@12000 {
status = "okay";
};
mdio {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@74000 {
status = "okay";
pinctrl-0 = <&ge1_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
spi@10600 {
status = "okay";
pinctrl-0 = <&spi0_pins2>;
pinctrl-names = "default";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
/* MX25L8006E */
compatible = "mxicy,mx25l8005", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partition@0 {
label = "u-boot";
reg = <0x0 0x100000>;
};
};
};
usb@50000 {
status = "okay";
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "USB Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
};
regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA0 power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Power button";
linux,code = <KEY_POWER>;
gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
debounce-interval = <100>;
};
button@2 {
label = "Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
button@3 {
label = "USB VBUS error";
linux,code = <KEY_UNKNOWN>;
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
debounce-interval = <100>;
};
};
gpio-leds {
compatible = "gpio-leds";
red-sata0 {
label = "cumulus:red:sata0";
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
gpio_poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
};
};
&pinctrl {
pinctrl-0 = <&sata_led_pin>;
pinctrl-names = "default";
sata_led_pin: sata-led-pin {
marvell,pins = "mpp60";
marvell,function = "sata0";
};
gpio_led_pin: gpio-led-pin {
marvell,pins = "mpp60";
marvell,function = "gpio";
};
};

8
sys/gnu/dts/arm/armada-370-synology-ds213j.dts
View File

@ -67,8 +67,7 @@
"marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = &uart0;
stdout-path = "serial0:115200n8";
};
memory {
@ -78,7 +77,8 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
internal-regs {
@ -93,7 +93,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064";
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;

15
sys/gnu/dts/arm/armada-370-xp.dtsi
View File

@ -59,8 +59,8 @@
compatible = "marvell,armada-370-xp";
aliases {
eth0 = &eth0;
eth1 = &eth1;
serial0 = &uart0;
serial1 = &uart1;
};
cpus {
@ -73,6 +73,11 @@
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
#address-cells = <2>;
#size-cells = <1>;
@ -144,7 +149,6 @@
};
spi0: spi@10600 {
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
@ -155,7 +159,6 @@
};
spi1: spi@10680 {
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
@ -223,7 +226,7 @@
<0x20250 0x8>;
};
mpic: interrupt-controller@20000 {
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
@ -265,7 +268,6 @@
};
eth0: ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0x70000 0x4000>;
interrupts = <8>;
clocks = <&gateclk 4>;
@ -281,7 +283,6 @@
};
eth1: ethernet@74000 {
compatible = "marvell,armada-370-neta";
reg = <0x74000 0x4000>;
interrupts = <10>;
clocks = <&gateclk 3>;

52
sys/gnu/dts/arm/armada-370.dtsi
View File

@ -129,6 +129,7 @@
compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
cache-level = <2>;
cache-unified;
wt-override;
};
@ -138,11 +139,15 @@
* board level if a different configuration is used.
*/
spi0: spi@10600 {
compatible = "marvell,armada-370-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi0_pins1>;
pinctrl-names = "default";
};
spi1: spi@10680 {
compatible = "marvell,armada-370-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
};
@ -232,7 +237,7 @@
reg = <0x18330 0x4>;
};
interrupt-controller@20000 {
interrupt-controller@20a00 {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
@ -251,6 +256,11 @@
reg = <0x20800 0x8>;
};
cpu-config@21000 {
compatible = "marvell,armada-370-cpu-config";
reg = <0x21000 0x8>;
};
audio_controller: audio-controller@30000 {
#sound-dai-cells = <1>;
compatible = "marvell,armada370-audio";
@ -306,6 +316,46 @@
dmacap,memset;
};
};
ethernet@70000 {
compatible = "marvell,armada-370-neta";
};
ethernet@74000 {
compatible = "marvell,armada-370-neta";
};
crypto@90000 {
compatible = "marvell,armada-370-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>;
clocks = <&gateclk 23>;
clock-names = "cesa0";
marvell,crypto-srams = <&crypto_sram>;
marvell,crypto-sram-size = <0x7e0>;
};
};
crypto_sram: sa-sram {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
reg-names = "sram";
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
/*
* The Armada 370 has an erratum preventing the use of
* the standard workflow for CPU idle support (relying
* on the BootROM code to enter/exit idle state).
* Reserve some amount of the crypto SRAM to put the
* cpuidle workaround.
*/
idle-sram@0 {
reg = <0x0 0x20>;
};
};
};
};

8
sys/gnu/dts/arm/armada-375-db.dts
View File

@ -55,7 +55,7 @@
compatible = "marvell,a375-db", "marvell,armada375";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -65,7 +65,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
@ -81,7 +83,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};

60
sys/gnu/dts/arm/armada-375.dtsi
View File

@ -60,8 +60,8 @@
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
ethernet0 = &eth0;
ethernet1 = &eth1;
serial0 = &uart0;
serial1 = &uart1;
};
clocks {
@ -69,7 +69,7 @@
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
clock-frequency = <1000000000>;
};
/* 25 MHz reference crystal */
refclk: oscillator {
@ -96,6 +96,11 @@
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
compatible = "marvell,armada375-mbus", "simple-bus";
#address-cells = <2>;
@ -171,6 +176,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
};
scu@c000 {
@ -233,7 +242,8 @@
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
@ -244,7 +254,8 @@
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-375-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
@ -276,7 +287,7 @@
status = "disabled";
};
serial@12000 {
uart0: serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>;
reg-shift = <2>;
@ -286,7 +297,7 @@
status = "disabled";
};
serial@12100 {
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
@ -394,7 +405,7 @@
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
@ -502,6 +513,21 @@
};
};
crypto@90000 {
compatible = "marvell,armada-375-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 30>, <&gateclk 31>,
<&gateclk 28>, <&gateclk 29>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x5000>;
@ -608,5 +634,23 @@
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 30>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 31>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
};
};

52
sys/gnu/dts/arm/armada-385-db-ap.dts
View File

@ -46,11 +46,10 @@
/ {
model = "Marvell Armada 385 Access Point Development Board";
compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart1;
stdout-path = "serial1:115200n8";
};
memory {
@ -60,7 +59,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi1: spi@10680 {
@ -71,7 +72,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <54000000>;
};
@ -126,6 +127,13 @@
status = "okay";
};
pinctrl@18000 {
xhci0_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
@ -150,6 +158,24 @@
phy = <&phy0>;
phy-mode = "rgmii-id";
};
nfc: flash@d0000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
num-cs = <1>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
usb3@f0000 {
status = "okay";
usb-phy = <&usb3_phy>;
};
};
pcie-controller {
@ -175,4 +201,20 @@
};
};
};
usb3_phy: usb3_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_xhci0_vbus>;
};
reg_xhci0_vbus: xhci0-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
};

114
sys/gnu/dts/arm/armada-385-linksys-caiman.dts Normal file
View File

@ -0,0 +1,114 @@
/*
* Device Tree include for the Linksys WRT1200AC (Caiman)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT1200AC";
compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs{
i2c@11000 {
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
wan_amber@0 {
label = "caiman:amber:wan";
reg = <0x0>;
};
wan_white@1 {
label = "caiman:white:wan";
reg = <0x1>;
};
wlan_2g@2 {
label = "caiman:white:wlan_2g";
reg = <0x2>;
};
wlan_5g@3 {
label = "caiman:white:wlan_5g";
reg = <0x3>;
};
usb2@5 {
label = "caiman:white:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "caiman:white:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "caiman:white:usb3_2";
reg = <0x7>;
};
wps_white@8 {
label = "caiman:white:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "caiman:amber:wps";
reg = <0x9>;
};
};
};
};
};
gpio-leds {
power {
label = "caiman:white:power";
};
sata {
label = "caiman:white:sata";
};
};
};

114
sys/gnu/dts/arm/armada-385-linksys-cobra.dts Normal file
View File

@ -0,0 +1,114 @@
/*
* Device Tree file for the Linksys WRT1900ACv2 (Cobra)
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385-linksys.dtsi"
/ {
model = "Linksys WRT1900ACv2";
compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
soc {
internal-regs{
i2c@11000 {
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
wan_amber@0 {
label = "cobra:amber:wan";
reg = <0x0>;
};
wan_white@1 {
label = "cobra:white:wan";
reg = <0x1>;
};
wlan_2g@2 {
label = "cobra:white:wlan_2g";
reg = <0x2>;
};
wlan_5g@3 {
label = "cobra:white:wlan_5g";
reg = <0x3>;
};
usb2@5 {
label = "cobra:white:usb2";
reg = <0x5>;
};
usb3_1@6 {
label = "cobra:white:usb3_1";
reg = <0x6>;
};
usb3_2@7 {
label = "cobra:white:usb3_2";
reg = <0x7>;
};
wps_white@8 {
label = "cobra:white:wps";
reg = <0x8>;
};
wps_amber@9 {
label = "cobra:amber:wps";
reg = <0x9>;
};
};
};
};
};
gpio-leds {
power {
label = "cobra:white:power";
};
sata {
label = "cobra:white:sata";
};
};
};

334
sys/gnu/dts/arm/armada-385-linksys.dtsi Normal file
View File

@ -0,0 +1,334 @@
/*
* Device Tree include file for Armada 385 based Linksys boards
*
* Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>
*
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-385.dtsi"
/ {
model = "Linksys boards based on Armada 385";
compatible = "linksys,armada385", "marvell,armada385",
"marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
status = "disabled";
};
i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
tmp421@4c {
compatible = "ti,tmp421";
reg = <0x4c>;
};
pca9635@68 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,pca9635";
reg = <0x68>;
};
};
/* J10: VCC, NC, RX, NC, TX, GND */
serial@12000 {
status = "okay";
};
ethernet@70000 {
status = "okay";
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@34000 {
status = "okay";
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
mdio {
status = "okay";
};
sata@a8000 {
status = "okay";
};
/* USB part of the eSATA/USB 2.0 port */
usb@50000 {
status = "okay";
};
usb3@f8000 {
status = "okay";
usb-phy = <&usb3_phy>;
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x200000>; /* 2MB */
read-only;
};
partition@100000 {
label = "u_env";
reg = <0x200000 0x40000>; /* 256KB */
};
partition@140000 {
label = "s_env";
reg = <0x240000 0x40000>; /* 256KB */
};
partition@900000 {
label = "devinfo";
reg = <0x900000 0x100000>; /* 1MB */
read-only;
};
/* kernel1 overlaps with rootfs1 by design */
partition@a00000 {
label = "kernel1";
reg = <0xa00000 0x2800000>; /* 40MB */
};
partition@1000000 {
label = "rootfs1";
reg = <0x1000000 0x2200000>; /* 34MB */
};
/* kernel2 overlaps with rootfs2 by design */
partition@3200000 {
label = "kernel2";
reg = <0x3200000 0x2800000>; /* 40MB */
};
partition@3800000 {
label = "rootfs2";
reg = <0x3800000 0x2200000>; /* 34MB */
};
/*
* 38MB, last MB is for the BBT, not writable
*/
partition@5a00000 {
label = "syscfg";
reg = <0x5a00000 0x2600000>;
};
/*
* Unused area between "s_env" and "devinfo".
* Moved here because otherwise the renumbered
* partitions would break the bootloader
* supplied bootargs
*/
partition@180000 {
label = "unused_area";
reg = <0x280000 0x680000>; /* 6.5MB */
};
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Marvell 88W8864, 5GHz-only */
status = "okay";
};
pcie@2,0 {
/* Marvell 88W8864, 2GHz-only */
status = "okay";
};
};
};
usb3_phy: usb3_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_xhci0_vbus>;
};
reg_xhci0_vbus: xhci0-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&keys_pin>;
pinctrl-names = "default";
button@1 {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
button@2 {
label = "Factory Reset Button";
linux,code = <KEY_RESTART>;
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&power_led_pin &sata_led_pin>;
pinctrl-names = "default";
power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
sata {
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
dsa@0 {
compatible = "marvell,dsa";
#address-cells = <2>;
#size-cells = <0>;
dsa,ethernet = <&eth2>;
dsa,mii-bus = <&mdio>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0>; /* MDIO address 0, switch 0 in tree */
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
};
};
};
};
&pinctrl {
keys_pin: keys-pin {
marvell,pins = "mpp24", "mpp47";
marvell,function = "gpio";
};
power_led_pin: power-led-pin {
marvell,pins = "mpp55";
marvell,function = "gpio";
};
sata_led_pin: sata-led-pin {
marvell,pins = "mpp54";
marvell,function = "gpio";
};
xhci0_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp50";
marvell,function = "gpio";
};
};

456
sys/gnu/dts/arm/armada-388-clearfog.dts Normal file
View File

@ -0,0 +1,456 @@
/*
* Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-388.dtsi"
#include "armada-38x-solidrun-microsom.dtsi"
/ {
model = "SolidRun Clearfog A1";
compatible = "solidrun,clearfog-a1", "marvell,armada388",
"marvell,armada385", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
ethernet2 = &eth1;
ethernet3 = &eth2;
};
chosen {
stdout-path = "serial0:115200n8";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
soc {
internal-regs {
ethernet@30000 {
phy-mode = "sgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
ethernet@34000 {
phy-mode = "sgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
i2c@11000 {
/* Is there anything on this? */
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
* 1-CON3 PERST#
* 2-CON2 PERST#
* 3-CON3 W_DISABLE
* 4-CON2 CLKREQ#
* 5-USB3 overcurrent
* 6-USB3 power
* 7-CON2 W_DISABLE
* 8-JP4 P1
* 9-JP4 P4
* 10-JP4 P5
* 11-m.2 DEVSLP
* 12-SFP_LOS
* 13-SFP_TX_FAULT
* 14-SFP_TX_DISABLE
* 15-SFP_MOD_DEF0
*/
expander0: gpio-expander@20 {
/*
* This is how it should be:
* compatible = "onnn,pca9655",
* "nxp,pca9555";
* but you can't do this because of
* the way I2C works.
*/
compatible = "nxp,pca9555";
gpio-controller;
#gpio-cells = <2>;
reg = <0x20>;
pcie1_0_clkreq {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
pcie1_0_w_disable {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
pcie2_0_clkreq {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
pcie2_0_w_disable {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie2.0-w-disable";
};
usb3_ilimit {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
usb3_power {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb3-power";
};
m2_devslp {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "m.2 devslp";
};
sfp_los {
/* SFP loss of signal */
gpio-hog;
gpios = <12 GPIO_ACTIVE_HIGH>;
input;
line-name = "sfp-los";
};
sfp_tx_fault {
/* SFP laser fault */
gpio-hog;
gpios = <13 GPIO_ACTIVE_HIGH>;
input;
line-name = "sfp-tx-fault";
};
sfp_tx_disable {
/* SFP transmit disable */
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "sfp-tx-disable";
};
sfp_mod_def0 {
/* SFP module present */
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
input;
line-name = "sfp-mod-def0";
};
};
/* The MCP3021 is 100kHz clock only */
mikrobus_adc: mcp3021@4c {
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
/* Also something at 0x64 */
};
i2c@11100 {
/*
* Routed to SFP, mikrobus, and PCIe.
* SFP limits this to 100kHz, and requires
* an AT24C01A/02/04 with address pins tied
* low, which takes addresses 0x50 and 0x51.
* Mikrobus doesn't specify beyond an I2C
* bus being present.
* PCIe uses ARP to assign addresses, or
* 0x63-0x64.
*/
clock-frequency = <100000>;
pinctrl-0 = <&clearfog_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
mdio@72004 {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver
* configures the LED register, rather
* than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x101e>;
reg = <0>;
};
};
pinctrl@18000 {
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";
marvell,function = "ref";
};
clearfog_dsa0_pins: clearfog-dsa0-pins {
marvell,pins = "mpp23", "mpp41";
marvell,function = "gpio";
};
clearfog_i2c1_pins: i2c1-pins {
/* SFP, PCIe, mSATA, mikrobus */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
marvell,pins = "mpp20";
marvell,function = "gpio";
};
clearfog_sdhci_pins: clearfog-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
clearfog_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp55";
marvell,function = "spi1";
};
mikro_pins: mikro-pins {
/* int: mpp22 rst: mpp29 */
marvell,pins = "mpp22", "mpp29";
marvell,function = "gpio";
};
mikro_spi_pins: mikro-spi-pins {
marvell,pins = "mpp43";
marvell,function = "spi1";
};
mikro_uart_pins: mikro-uart-pins {
marvell,pins = "mpp24", "mpp25";
marvell,function = "ua1";
};
rear_button_pins: rear-button-pins {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
};
sata@a8000 {
/* pinctrl? */
status = "okay";
};
sata@e0000 {
/* pinctrl? */
status = "okay";
};
sdhci@d8000 {
bus-width = <4>;
cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
no-1-8-v;
pinctrl-0 = <&clearfog_sdhci_pins
&clearfog_sdhci_cd_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
serial@12100 {
/* mikrobus uart */
pinctrl-0 = <&mikro_uart_pins>;
pinctrl-names = "default";
status = "okay";
};
spi@10680 {
/*
* We don't seem to have the W25Q32 on the
* A1 Rev 2.0 boards, so disable SPI.
* CS0: W25Q32 (doesn't appear to be present)
* CS1:
* CS2: mikrobus
*/
pinctrl-0 = <&spi1_pins
&clearfog_spi1_cs_pins
&mikro_spi_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "disabled";
};
};
usb@58000 {
/* CON3, nearest power. */
status = "okay";
};
usb3@f0000 {
/* CON2, nearest CPU, USB2 only. */
status = "okay";
};
usb3@f8000 {
/* CON7 */
status = "okay";
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
pcie@2,0 {
/* Port 1, Lane 0. CON3, nearest power. */
reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0. CON2, nearest CPU. */
reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
dsa@0 {
compatible = "marvell,dsa";
dsa,ethernet = <&eth1>;
dsa,mii-bus = <&mdio>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default";
#address-cells = <2>;
#size-cells = <0>;
switch@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4 0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "lan5";
};
port@5 {
reg = <5>;
label = "cpu";
};
port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&rear_button_pins>;
pinctrl-names = "default";
button_0 {
/* The rear SW3 button */
label = "Rear Button";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
};
};

10
sys/gnu/dts/arm/armada-388-db.dts
View File

@ -54,7 +54,7 @@
"marvell,armada385", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -64,7 +64,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
@ -73,7 +75,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q32";
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
@ -99,7 +101,7 @@
phy-mode = "rgmii-id";
};
usb@50000 {
usb@58000 {
status = "ok";
};

48
sys/gnu/dts/arm/armada-388-gp.dts
View File

@ -48,8 +48,7 @@
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200";
stdout-path = &uart0;
stdout-path = "serial0:115200n8";
};
memory {
@ -59,7 +58,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
@ -70,7 +71,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
@ -82,10 +83,6 @@
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
/*
* The EEPROM located at adresse 54 is needed
* for the boot - DO NOT ERASE IT -
*/
expander0: pca9555@20 {
compatible = "nxp,pca9555";
@ -112,6 +109,10 @@
reg = <0x21>;
};
eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
};
};
serial@12000 {
@ -135,7 +136,7 @@
};
/* CON4 */
usb@50000 {
usb@58000 {
vcc-supply = <&reg_usb2_0_vbus>;
status = "okay";
};
@ -206,8 +207,21 @@
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
no-1-8-v;
/*
* A388-GP board v1.5 and higher replace
* hitherto card detection method based on GPIO
* with the one using DAT3 pin. As they are
* incompatible, software-based polling is
* enabled with 'broken-cd' property. For boards
* older than v1.5 it can be replaced with:
* 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
* whereas for the newer ones following can be
* used instead:
* 'dat3-cd;'
* 'cd-inverted;'
*/
broken-cd;
wp-inverted;
bus-width = <8>;
status = "okay";
@ -289,22 +303,14 @@
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
reg_usb2_1_vbus: v5-vbus1 {
compatible = "regulator-fixed";
regulator-name = "v5.0-vbus1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
};
reg_sata0: pwr-sata0 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
enable-active-high;
regulator-always-on;
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata0: v5-sata0 {

18
sys/gnu/dts/arm/armada-388-rd.dts
View File

@ -55,7 +55,7 @@
"marvell,armada385","marvell,armada380";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
stdout-path = "serial0:115200n8";
};
memory {
@ -65,7 +65,9 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
spi@10600 {
@ -74,7 +76,7 @@
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
compatible = "st,m25p128", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
@ -85,6 +87,16 @@
clock-frequency = <100000>;
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
broken-cd;
no-1-8-v;
wp-inverted;
bus-width = <8>;
status = "okay";
};
serial@12000 {
status = "okay";
};

115
sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi Normal file
View File

@ -0,0 +1,115 @@
/*
* Device Tree file for SolidRun Armada 38x Microsom
*
* Copyright (C) 2015 Russell King
*
* This board is in development; the contents of this file work with
* the A1 rev 2.0 of the board, which does not represent final
* production board. Things will change, don't expect this file to
* remain compatible info the future.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
internal-regs {
ethernet@70000 {
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy_dedicated>;
phy-mode = "rgmii-id";
status = "okay";
};
mdio@72004 {
/*
* Add the phy clock here, so the phy can be
* accessed to read its IDs prior to binding
* with the driver.
*/
pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
pinctrl-names = "default";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver
* configures the LED register, rather
* than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x101e>;
reg = <0>;
};
};
pinctrl@18000 {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";
marvell,function = "ref";
};
};
rtc@a3800 {
/*
* If the rtc doesn't work, run "date reset"
* twice in u-boot.
*/
status = "okay";
};
serial@12000 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
};
};
};

75
sys/gnu/dts/arm/armada-38x.dtsi
View File

@ -59,9 +59,13 @@
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
ethernet0 = &eth0;
ethernet1 = &eth1;
ethernet2 = &eth2;
serial0 = &uart0;
serial1 = &uart1;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts-extended = <&mpic 3>;
};
soc {
@ -139,6 +143,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
arm,double-linefill-incr = <1>;
arm,double-linefill-wrap = <0>;
arm,double-linefill = <1>;
prefetch-data = <1>;
};
scu@c000 {
@ -163,7 +171,8 @@
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10600 0x50>;
#address-cells = <1>;
#size-cells = <0>;
@ -174,7 +183,8 @@
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
compatible = "marvell,armada-380-spi",
"marvell,orion-spi";
reg = <0x10680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
@ -216,7 +226,7 @@
status = "disabled";
};
serial@12100 {
uart1: serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>;
reg-shift = <2>;
@ -368,7 +378,7 @@
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
mpic: interrupt-controller@20a00 {
compatible = "marvell,mpic";
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
#interrupt-cells = <1>;
@ -435,7 +445,7 @@
status = "disabled";
};
usb@50000 {
usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@ -444,7 +454,7 @@
};
xor@60800 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
@ -464,7 +474,7 @@
};
xor@60900 {
compatible = "marvell,orion-xor";
compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
@ -488,10 +498,11 @@
reg = <0x70000 0x4000>;
interrupts-extended = <&mpic 8>;
clocks = <&gateclk 4>;
tx-csum-limit = <9800>;
status = "disabled";
};
mdio@72004 {
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@ -499,6 +510,21 @@
clocks = <&gateclk 4>;
};
crypto@90000 {
compatible = "marvell,armada-38x-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 23>, <&gateclk 21>,
<&gateclk 14>, <&gateclk 16>;
clock-names = "cesa0", "cesa1",
"cesaz0", "cesaz1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
@ -548,8 +574,11 @@
sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg = <0xd8000 0x1000>, <0xdc000 0x100>;
interrupts = <0 25 0x4>;
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
<0xdc000 0x100>,
<0x18454 0x4>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 17>;
mrvl,clk-delay-cycles = <0x1F>;
status = "disabled";
@ -571,6 +600,24 @@
status = "disabled";
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
clocks = <&gateclk 21>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
};
clocks {
@ -578,7 +625,7 @@
mainpll: mainpll {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <2000000000>;
clock-frequency = <1000000000>;
};
/* 25 MHz reference crystal */

57
sys/gnu/dts/arm/armada-390.dtsi Normal file
View File

@ -0,0 +1,57 @@
/*
* Device Tree Include file for Marvell Armada 390 SoC.
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "armada-39x.dtsi"
/ {
soc {
internal-regs {
pinctrl@18000 {
compatible = "marvell,mv88f6920-pinctrl";
reg = <0x18000 0x20>;
};
};
};

153
sys/gnu/dts/arm/armada-398-db.dts Normal file
View File

@ -0,0 +1,153 @@
/*
* Device Tree Include file for Marvell Armada 398 Development Board
*
* Copyright (C) 2015 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-398.dtsi"
/ {
model = "Marvell Armada 398 Development Board";
compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10680 {
status = "okay";
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
partition@0 {
label = "U-Boot";
reg = <0 0x400000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x400000 0x1000000>;
};
};
};
i2c@11000 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@12100 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
flash@d0000 {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
partition@0 {
label = "U-Boot";
reg = <0 0x800000>;
};
partition@800000 {
label = "Linux";
reg = <0x800000 0x800000>;
};
partition@1000000 {
label = "Filesystem";
reg = <0x1000000 0x3f000000>;
};
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
status = "okay";
};
pcie@2,0 {
status = "okay";
};
pcie@3,0 {
status = "okay";
};
};
};
};

Some files were not shown because too many files have changed in this diff Show More