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Use the same terminology as the ARM docs in comments. No functional changes.

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This commit is contained in:
Ian Lepore 2014-03-16 20:34:45 +00:00
parent 1e154d409d
commit 312c48ff18
1 changed files with 5 additions and 5 deletions
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10
sys/arm/arm/cpufunc_asm_armv7.S
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@ -84,10 +84,10 @@ END(armv7_setttb)
ENTRY(armv7_tlb_flushID) ENTRY(armv7_tlb_flushID)
dsb dsb
#ifdef SMP #ifdef SMP
mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */ mcr p15, 0, r0, c8, c3, 0 /* flush Unified TLB all entries Inner Shareable */
mcr p15, 0, r0, c7, c1, 6 /* flush BTB */ mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
#else #else
mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ mcr p15, 0, r0, c8, c7, 0 /* flush Unified TLB all entries */
mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
#endif #endif
dsb dsb
@ -99,10 +99,10 @@ ENTRY(armv7_tlb_flushID_SE)
ldr r1, .Lpage_mask ldr r1, .Lpage_mask
bic r0, r0, r1 bic r0, r0, r1
#ifdef SMP #ifdef SMP
mcr p15, 0, r0, c8, c3, 3 /* flush D tlb single entry Inner Shareable*/ mcr p15, 0, r0, c8, c3, 3 /* flush Unified TLB single entry Inner Shareable */
mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
#else #else
mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */ mcr p15, 0, r0, c8, c7, 1 /* flush Unified TLB single entry */
mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
#endif #endif
dsb dsb