Add test for SATA registers writability and skip using them if it failed.
There are some systems reported, where PCI BAR(5), used for SATA registers access, is present, but not functional. Attempt to use it brakes devices detection logic. Try to detect those cases on attach by setting and testing some bits in SControl register. If bits are unsettable, fallback to legacy ATA without hot-plug detection, speed control/reporting, etc. MFC after: 2 weeks
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@ -72,6 +72,7 @@ static int ata_intel_sata_cscr_write(device_t dev, int port,
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int reg, u_int32_t result);
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static int ata_intel_sata_sidpr_write(device_t dev, int port,
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int reg, u_int32_t result);
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static int ata_intel_sata_sidpr_test(device_t dev);
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static int ata_intel_31244_ch_attach(device_t dev);
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static int ata_intel_31244_ch_detach(device_t dev);
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static int ata_intel_31244_status(device_t dev);
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@ -416,22 +417,20 @@ ata_intel_ch_attach(device_t dev)
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}
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if (ch->flags & ATA_SATA) {
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if ((ctlr->chip->cfg1 & INTEL_ICH5)) {
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ch->flags |= ATA_PERIODIC_POLL;
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ch->hw.status = ata_intel_sata_status;
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ch->hw.pm_read = ata_intel_sata_cscr_read;
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ch->hw.pm_write = ata_intel_sata_cscr_write;
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} else if (ctlr->r_res2) {
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ch->flags |= ATA_PERIODIC_POLL;
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ch->hw.status = ata_intel_sata_status;
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if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
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ch->hw.pm_read = ata_intel_sata_ahci_read;
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ch->hw.pm_write = ata_intel_sata_ahci_write;
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} else {
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} else if (ata_intel_sata_sidpr_test(dev)) {
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ch->hw.pm_read = ata_intel_sata_sidpr_read;
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ch->hw.pm_write = ata_intel_sata_sidpr_write;
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};
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}
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if (ch->hw.pm_write != NULL) {
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ch->flags |= ATA_PERIODIC_POLL;
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ch->hw.status = ata_intel_sata_status;
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ata_sata_scr_write(ch, 0,
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ATA_SERROR, 0xffffffff);
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if ((ch->flags & ATA_NO_SLAVE) == 0) {
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@ -834,6 +833,32 @@ ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value)
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return (0);
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}
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static int
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ata_intel_sata_sidpr_test(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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int port;
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uint32_t val;
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port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1;
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for (; port >= 0; port--) {
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ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val);
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if ((val & ATA_SC_IPM_MASK) ==
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(ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
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return (1);
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val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER;
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ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val);
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ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val);
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if ((val & ATA_SC_IPM_MASK) ==
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(ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
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return (1);
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}
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if (bootverbose)
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device_printf(dev,
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"SControl registers are not functional: %08x\n", val);
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return (0);
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}
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static int
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ata_intel_31244_ch_attach(device_t dev)
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{
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