Sync up the rest of the code that we use with what Intel is shipping
-Some irq/vblank related changes that hopefully will help. -A little more cleanup while I'm here. MFC after: 3 days
This commit is contained in:
parent
5a6ba2ffbc
commit
324a23e9a2
@ -193,7 +193,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap(&dev_priv->ring.map, dev);
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drm_core_ioremap_wc(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.handle == NULL) {
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i915_dma_cleanup(dev);
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@ -209,7 +209,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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dev_priv->current_page = 0;
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dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
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dev_priv->sarea_priv->pf_current_page = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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@ -721,7 +721,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data,
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DRM_DEBUG("%s\n", __func__);
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LOCK_TEST_WITH_RETURN(dev, file_priv);
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RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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ret = i915_dispatch_flip(dev);
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@ -758,7 +758,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
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value = 0;
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break;
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default:
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DRM_ERROR("Unknown parameter %d\n", param->param);
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DRM_DEBUG("Unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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@ -791,7 +791,7 @@ static int i915_setparam(struct drm_device *dev, void *data,
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dev_priv->allow_batchbuffer = param->value;
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break;
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default:
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DRM_ERROR("unknown parameter %d\n", param->param);
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DRM_DEBUG("unknown parameter %d\n", param->param);
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return -EINVAL;
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}
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@ -822,7 +822,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
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dev_priv->hws_map.flags = 0;
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dev_priv->hws_map.mtrr = 0;
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drm_core_ioremap(&dev_priv->hws_map, dev);
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drm_core_ioremap_wc(&dev_priv->hws_map, dev);
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if (dev_priv->hws_map.handle == NULL) {
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i915_dma_cleanup(dev);
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dev_priv->status_gfx_addr = 0;
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@ -880,8 +880,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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/* Init HWS */
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if (!I915_NEED_GFX_HWS(dev)) {
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ret = i915_init_phys_hws(dev);
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if (ret != 0)
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if (ret != 0) {
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drm_rmmap(dev, dev_priv->mmio_map);
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drm_free(dev_priv, sizeof(struct drm_i915_private),
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DRM_MEM_DRIVER);
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return ret;
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}
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}
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#ifdef __linux__
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/* On the 945G/GM, the chipset reports the MSI capability on the
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@ -901,6 +905,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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intel_opregion_init(dev);
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#endif
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DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
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dev_priv->user_irq_refcount = 0;
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ret = drm_vblank_init(dev, I915_NUM_PIPE);
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@ -43,21 +43,28 @@ __FBSDID("$FreeBSD$");
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
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#define I915_INTERRUPT_ENABLE_FIX (I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
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/** These are all of the interrupts used by the driver */
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#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
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I915_INTERRUPT_ENABLE_VAR)
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#define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
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I915_INTERRUPT_ENABLE_VAR)
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#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
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PIPE_VBLANK_INTERRUPT_STATUS)
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#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
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PIPE_VBLANK_INTERRUPT_ENABLE)
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#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
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DRM_I915_VBLANK_PIPE_B)
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static inline void
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i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
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{
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DRM_DEBUG("irq_enable_reg = 0x%08x, mask = 0x%08x\n",
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dev_priv->irq_mask_reg, mask);
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mask &= I915_INTERRUPT_ENABLE_VAR;
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if ((dev_priv->irq_mask_reg & mask) != 0) {
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dev_priv->irq_mask_reg &= ~mask;
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@ -189,59 +196,84 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 iir, new_iir;
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u32 pipea_stats, pipeb_stats;
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u32 vblank_status;
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u32 vblank_enable;
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int irq_received;
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atomic_inc(&dev_priv->irq_received);
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for (iir = I915_READ(IIR) ; iir != 0 ; iir = new_iir) {
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iir = I915_READ(IIR);
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pipea_stats = pipeb_stats = 0;
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if (IS_I965G(dev)) {
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vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
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vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
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} else {
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vblank_status = I915_VBLANK_INTERRUPT_STATUS;
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vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
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}
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for (;;) {
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irq_received = iir != 0;
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/* Can't rely on pipestat interrupt bit in iir as it might
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* have been cleared after the pipestat interrupt was received.
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* It doesn't set the bit in iir again, but it still produces
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* interrupts (for non-MSI).
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*/
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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pipea_stats = I915_READ(PIPEASTAT);
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pipeb_stats = I915_READ(PIPEBSTAT);
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/*
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* Clear the PIPE(A|B)STAT regs before the IIR
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*/
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if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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pipea_stats = I915_READ(PIPEASTAT);
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if (pipea_stats & 0x8000ffff) {
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I915_WRITE(PIPEASTAT, pipea_stats);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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irq_received = 1;
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}
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if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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pipeb_stats = I915_READ(PIPEBSTAT);
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if (pipeb_stats & 0x8000ffff) {
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I915_WRITE(PIPEBSTAT, pipeb_stats);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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irq_received = 1;
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}
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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if (!irq_received)
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break;
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I915_WRITE(IIR, iir);
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new_iir = I915_READ(IIR);
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DRM_DEBUG("iir = 0x%08x, pipestats a = 0x%08x, b = 0x%08x\n",
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iir, pipea_stats, pipeb_stats);
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new_iir = I915_READ(IIR); /* Flush posted writes */
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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if (iir & I915_USER_INTERRUPT) {
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#ifdef I915_HAVE_GEM
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dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
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#endif
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DRM_WAKEUP(&dev_priv->irq_queue);
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}
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if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
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PIPE_VBLANK_INTERRUPT_STATUS))
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if (pipea_stats & vblank_status)
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drm_handle_vblank(dev, 0);
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if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS |
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PIPE_VBLANK_INTERRUPT_STATUS))
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if (pipeb_stats & vblank_status)
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drm_handle_vblank(dev, 1);
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#ifdef __linux__
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if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
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(iir & I915_ASLE_INTERRUPT))
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opregion_asle_intr(dev);
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#endif
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/* With MSI, interrupts are only generated when iir
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* transitions from zero to nonzero. If another bit got
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* set while we were handling the existing iir bits, then
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* we would never get another interrupt.
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*
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* This is fine on non-MSI as well, as if we hit this path
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* we avoid exiting the interrupt handler only to generate
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* another one.
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*
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* Note that for MSI this could cause a stray interrupt report
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* if an interrupt landed in the time between writing IIR and
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* the posting read. This should be rare enough to never
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* trigger the 99% of 100,000 interrupts test for disabling
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* stray interrupts.
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*/
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iir = new_iir;
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}
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}
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@ -273,27 +305,25 @@ static int i915_emit_irq(struct drm_device * dev)
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void i915_user_irq_get(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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DRM_DEBUG("\n");
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
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i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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}
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void i915_user_irq_put(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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#ifdef __linux__
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BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
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#endif
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if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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if (dev->irq_enabled) {
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KASSERT(dev_priv->user_irq_refcount > 0, ("invalid refcount"));
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if (--dev_priv->user_irq_refcount == 0)
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i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
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}
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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}
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static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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@ -320,15 +350,14 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
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READ_BREADCRUMB(dev_priv) >= irq_nr);
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i915_user_irq_put(dev);
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if (ret == -ERESTART)
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DRM_DEBUG("restarting syscall\n");
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if (ret == -EBUSY) {
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DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
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READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
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}
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if (dev_priv->sarea_priv)
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dev_priv->sarea_priv->last_dispatch =
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READ_BREADCRUMB(dev_priv);
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return ret;
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}
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@ -341,13 +370,13 @@ int i915_irq_emit(struct drm_device *dev, void *data,
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drm_i915_irq_emit_t *emit = data;
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int result;
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RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
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result = i915_emit_irq(dev);
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if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
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@ -380,21 +409,21 @@ int i915_irq_wait(struct drm_device *dev, void *data,
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int i915_enable_vblank(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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u32 pipestat;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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u32 pipeconf;
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/*
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* Older chips didn't have the start vblank interrupt,
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* but
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*/
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if (IS_I965G (dev))
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pipestat = PIPE_START_VBLANK_INTERRUPT_ENABLE;
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pipeconf = I915_READ(pipeconf_reg);
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if (!(pipeconf & PIPEACONF_ENABLE))
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return -EINVAL;
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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if (IS_I965G(dev))
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i915_enable_pipestat(dev_priv, pipe,
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PIPE_START_VBLANK_INTERRUPT_ENABLE);
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else
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pipestat = PIPE_VBLANK_INTERRUPT_ENABLE;
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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i915_enable_pipestat(dev_priv, pipe, pipestat);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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i915_enable_pipestat(dev_priv, pipe,
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PIPE_VBLANK_INTERRUPT_ENABLE);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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return 0;
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}
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@ -404,12 +433,12 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
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void i915_disable_vblank(struct drm_device *dev, int pipe)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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unsigned long irqflags;
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DRM_SPINLOCK_IRQSAVE(&dev_priv->user_irq_lock, irqflags);
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DRM_SPINLOCK(&dev_priv->user_irq_lock);
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i915_disable_pipestat(dev_priv, pipe,
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PIPE_START_VBLANK_INTERRUPT_ENABLE | PIPE_VBLANK_INTERRUPT_ENABLE);
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DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->user_irq_lock, irqflags);
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PIPE_VBLANK_INTERRUPT_ENABLE |
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PIPE_START_VBLANK_INTERRUPT_ENABLE);
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DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
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}
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/* Set the vblank monitor pipe
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@ -463,7 +492,6 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
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* Context switching to userland and back is plenty fast enough for
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* meeting the requirements of vblank swapping.
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*/
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return -EINVAL;
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}
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@ -473,6 +501,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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atomic_set_int(&dev_priv->irq_received, 0);
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I915_WRITE(HWSTAM, 0xeffe);
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I915_WRITE(PIPEASTAT, 0);
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I915_WRITE(PIPEBSTAT, 0);
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@ -505,13 +535,6 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
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I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
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I915_WRITE(IMR, dev_priv->irq_mask_reg);
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(void) I915_READ(IER);
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#ifdef __linux__
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opregion_enable_asle(dev);
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#endif
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DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
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i915_enable_vblank(dev, 0);
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i915_enable_vblank(dev, 1);
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return 0;
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}
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