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Synchronize i915_reg.h with linux 3.8.13 version

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Keep a couple of old macros that will be removed lated when the rest of the code
will be updated to 3.8.13 equivalent.
Chase the renamed macros

Reviewed by:	dumbbell
Differential Revision:	https://reviews.freebsd.org/D3487
This commit is contained in:
bapt 2015-08-26 21:17:48 +00:00
parent cf867c21d7
commit 331e9ff82a
4 changed files with 590 additions and 179 deletions
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713
sys/dev/drm2/i915/i915_reg.h
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File diff suppressed because it is too large Load Diff

38
sys/dev/drm2/i915/intel_ddi.c
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@ -146,7 +146,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(SPLL_CTL,
SPLL_PLL_ENABLE |
SPLL_PLL_FREQ_1350MHz |
SPLL_PLL_SCC);
SPLL_PLL_SSC);
/* Use SPLL to drive the output when in FDI mode */
I915_WRITE(PORT_CLK_SEL(PORT_E),
@ -200,14 +200,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
DP_TP_CTL_ENABLE);
/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in FDI mode */
temp = I915_READ(DDI_FUNC_CTL(pipe));
temp &= ~PIPE_DDI_PORT_MASK;
temp |= PIPE_DDI_SELECT_PORT(PORT_E) |
PIPE_DDI_MODE_SELECT_FDI |
PIPE_DDI_FUNC_ENABLE |
PIPE_DDI_PORT_WIDTH_X2;
I915_WRITE(DDI_FUNC_CTL(pipe),
/* Enable PIPE_TRANS_DDI_FUNC_CTL for the pipe to work in FDI mode */
temp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
temp &= ~TRANS_DDI_PORT_MASK;
temp |= TRANS_DDI_SELECT_PORT(PORT_E) |
TRANS_DDI_MODE_SELECT_FDI |
TRANS_DDI_FUNC_ENABLE |
TRANS_DDI_PORT_WIDTH_X2;
I915_WRITE(TRANS_DDI_FUNC_CTL(pipe),
temp);
break;
} else {
@ -719,18 +719,18 @@ void intel_ddi_mode_set(struct drm_encoder *encoder,
pipe_name(intel_crtc->pipe));
}
/* Enable PIPE_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = I915_READ(DDI_FUNC_CTL(pipe));
temp &= ~PIPE_DDI_PORT_MASK;
temp &= ~PIPE_DDI_BPC_12;
temp |= PIPE_DDI_SELECT_PORT(port) |
PIPE_DDI_MODE_SELECT_HDMI |
/* Enable PIPE_TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
temp = I915_READ(TRANS_DDI_FUNC_CTL(pipe));
temp &= ~TRANS_DDI_PORT_MASK;
temp &= ~TRANS_DDI_BPC_12;
temp |= TRANS_DDI_SELECT_PORT(port) |
TRANS_DDI_MODE_SELECT_HDMI |
((intel_crtc->bpp > 24) ?
PIPE_DDI_BPC_12 :
PIPE_DDI_BPC_8) |
PIPE_DDI_FUNC_ENABLE;
TRANS_DDI_BPC_12 :
TRANS_DDI_BPC_8) |
TRANS_DDI_FUNC_ENABLE;
I915_WRITE(DDI_FUNC_CTL(pipe), temp);
I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), temp);
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);

16
sys/dev/drm2/i915/intel_display.c
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@ -974,9 +974,9 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
if (IS_HASWELL(dev_priv->dev)) {
/* On Haswell, DDI is used instead of FDI_TX_CTL */
reg = DDI_FUNC_CTL(pipe);
reg = TRANS_DDI_FUNC_CTL(pipe);
val = I915_READ(reg);
cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
} else {
reg = FDI_TX_CTL(pipe);
val = I915_READ(reg);
@ -1878,13 +1878,13 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
break;
case 16:
if (fb->depth == 15)
dspcntr |= DISPPLANE_15_16BPP;
dspcntr |= DISPPLANE_BGRX555;
else
dspcntr |= DISPPLANE_16BPP;
dspcntr |= DISPPLANE_BGRX565;
break;
case 24:
case 32:
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr |= DISPPLANE_BGRX888;
break;
default:
DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
@ -1956,14 +1956,14 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
return -EINVAL;
}
dspcntr |= DISPPLANE_16BPP;
dspcntr |= DISPPLANE_BGRX565;
break;
case 24:
case 32:
if (fb->depth == 24)
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
dspcntr |= DISPPLANE_BGRX888;
else if (fb->depth == 30)
dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
dspcntr |= DISPPLANE_BGRX101010;
else {
DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
fb->depth);

2
sys/dev/drm2/i915/intel_pm.c
View File

@ -3301,7 +3301,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
/* Bspec says we need to always set all mask bits. */
I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
_3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
/*
* According to the spec the following bits should be