Allwinner clk: factor M for mod clock is 4 bits, not 5
MFC after: 1 week
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@ -56,9 +56,9 @@ __FBSDID("$FreeBSD$");
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#define CLK_RATIO_N (0x3 << 16)
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#define CLK_RATIO_N_SHIFT 16
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#define CLK_RATIO_N_MAX 0x3
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#define CLK_RATIO_M (0x1f << 0)
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#define CLK_RATIO_M (0xf << 0)
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#define CLK_RATIO_M_SHIFT 0
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#define CLK_RATIO_M_MAX 0x1f
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#define CLK_RATIO_M_MAX 0xf
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-mod0-clk", 1 },
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