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Don't touch MSI enable bit in RL_CFG2 register. For unknown reason

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clearing MSI enable bit for MSI capable hardwares resulted in Tx
problems. MSI enable bit is set only when MSI is requested from
user.

Tested by:	remko
This commit is contained in:
Pyun YongHyeon 2008-04-15 00:46:15 +00:00
parent 23080c0bd3
commit 339a44fb62
1 changed files with 6 additions and 12 deletions
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18
sys/dev/re/if_re.c
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@ -1185,23 +1185,17 @@ re_attach(dev)
device_printf(dev, "Using %d MSI messages\n",
msic);
sc->rl_msi = 1;
/* Explicitly set MSI enable bit. */
CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
cfg = CSR_READ_1(sc, RL_CFG2);
cfg |= RL_CFG2_MSI;
CSR_WRITE_1(sc, RL_CFG2, cfg);
CSR_WRITE_1(sc, RL_EECMD, 0);
} else
pci_release_msi(dev);
}
}
/* For MSI capable hardwares, explicitily set/clear MSI enable bit. */
if (msic != 0) {
CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
cfg = CSR_READ_1(sc, RL_CFG2);
if (sc->rl_msi != 0)
cfg |= RL_CFG2_MSI;
else
cfg &= ~RL_CFG2_MSI;
CSR_WRITE_1(sc, RL_CFG2, cfg);
CSR_WRITE_1(sc, RL_EECMD, 0);
}
/* Allocate interrupt */
if (sc->rl_msi == 0) {
rid = 0;