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MFp4:

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For 32-bit SDRAM systems, enable D16 to D31 in the PIO controller.
Otherwise they read back as 0xffff.

Shave 8 bytes from the object size by using AT91C_BASE_PIOA directly
and by not assigning PIO_BSR to 0 in the DBGU init.  That's a nop in
two ways (everything defaults to peripheral A, and writing 0 changes
nothing).
This commit is contained in:
imp 2006-04-13 17:39:34 +00:00
parent 79ad9cfabd
commit 3419654b4d
1 changed files with 7 additions and 4 deletions
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11
sys/boot/arm/at91/boot0/at91rm9200_lowlevel.c
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@ -44,7 +44,6 @@ _init(void)
{
AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
AT91PS_PIO pPio = AT91C_BASE_PIOA;
register unsigned value;
int i;
@ -152,10 +151,14 @@ _init(void)
AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD;
*p = 0;
#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS
// Turn on the upper 16 bits on the SDRAM bus.
AT91C_BASE_PIOC->PIO_ASR = 0xffff0000;
AT91C_BASE_PIOC->PIO_PDR = 0xffff0000;
#endif
// Configure DBGU -use local routine optimized for space
pPio->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
pPio->PIO_BSR = 0;
pPio->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
pUSART->US_IDR = (unsigned int) -1;
pUSART->US_CR =
AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;